Analog Devices ADI ADuCM302x ADuCM302x 1p0 ARM Cortex-M3 Microcontroller based device ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontroller, but can be equally used for other suitable processor architectures. This file can be freely distributed. Modifications to this file shall be clearly marked. THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM3 r0p1 little false false 3 false system_ADuCM302x ADI_ 8 32 32 read-write 0x00000000 0xFFFFFFFF TMR0 General Purpose Timer 0x40000000 TMR0 0 0x00000040 registers TMR0_EVT 11 Event LOAD 0x00000000 16 16-bit Load Value 0x00000000 VALUE Load Value 0 16 read-write 0x00000000 0x0000FFFF CURCNT 0x00000004 16 16-bit Timer Value 0x00000000 VALUE Current Count 0 16 read-only CTL 0x00000008 16 Control 0x0000000A PRE Prescaler 0 2 read-write UP Count up 2 1 read-write MODE Timer Mode 3 1 read-write EN Timer Enable 4 1 read-write CLK Clock Select 5 2 read-write RLD Reload Control 7 1 read-write EVTRANGE Event Select Range 8 5 read-write 0x00000000 0x0000001F EVTEN Event Select 13 1 read-write RSTEN Counter and Prescale Reset Enable 14 1 read-write 0x00000000 0x00000001 SYNCBYP Synchronization Bypass 15 1 read-write CLRINT 0x0000000C 16 Clear Interrupt 0x00000000 TIMEOUT Clear Timeout Interrupt 0 1 write-only EVTCAPT Clear Captured Event Interrupt 1 1 write-only CAPTURE 0x00000010 16 Capture 0x00000000 VALUE 16-bit Captured Value 0 16 read-only ALOAD 0x00000014 16 16-bit Load Value, Asynchronous 0x00000000 VALUE Load Value, Asynchronous 0 16 read-write 0x00000000 0x0000FFFF ACURCNT 0x00000018 16 16-bit Timer Value, Asynchronous 0x00000000 VALUE Counter Value 0 16 read-only STAT 0x0000001C 16 Status 0x00000000 TIMEOUT Timeout Event Occurred 0 1 read-only CAPTURE Capture Event Pending 1 1 read-only BUSY Timer Busy 6 1 read-only PDOK Clear Interrupt Register Synchronization 7 1 read-only CNTRST Counter Reset Occurring 8 1 read-only PWMCTL 0x00000020 16 PWM Control Register 0x00000000 MATCH PWM Match Enabled 0 1 read-write PWM_TOGGLE PWM in toggle mode 0 PWM_MATCH PWM in match mode 1 IDLESTATE PWM Idle State 1 1 read-write IDLE_LOW PWM idles low 0 IDLE_HIGH PWM idles high 1 PWMMATCH 0x00000024 16 PWM Match Value 0x00000000 VALUE PWM Match Value 0 16 read-write 0x00000000 0x0000FFFF TMR1 0x40000400 TMR1_EVT 12 Event TMR2 0x40000800 TMR2_EVT 40 Event RTC0 Real-Time Clock 0x40001000 RTC0 0 0x00000100 registers RTC0_EVT 8 Event CR0 0x00000000 16 RTC Control 0 0x000003C4 CNTEN Global Enable for the RTC 0 1 read-write ALMEN Enable the RTC Alarm (Absolute) Operation 1 1 read-write ALMINTEN Enable ALMINT Sourced Alarm Interrupts to the CPU 2 1 read-write TRMEN Enable RTC Digital Trimming 3 1 read-write MOD60ALMEN Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary 4 1 read-write MOD60ALM Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary 5 6 read-write 0x00000000 0x0000003F MOD60ALMINTEN Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU 11 1 read-write ISOINTEN Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated 12 1 read-write WPNDERRINTEN Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs 13 1 read-write WSYNCINTEN Enable Write Synchronization Sourced Interrupts to the CPU 14 1 read-write WPNDINTEN Enable Write Pending Sourced Interrupts to the CPU 15 1 read-write SR0 0x00000004 16 RTC Status 0 0x00003F80 ALMINT Alarm Interrupt Source 1 1 read-write MOD60ALMINT Modulo-60 RTC Alarm Interrupt Source 2 1 read-write ISOINT RTC Power-Domain Isolation Interrupt Source 3 1 read-write WPNDERRINT Write Pending Error Interrupt Source 4 1 read-write WSYNCINT Write Synchronisation Interrupt 5 1 read-write WPNDINT Write Pending Interrupt 6 1 read-write WSYNCCR0 Synchronisation Status of Posted Writes to CR0 7 1 read-only WSYNCSR0 Synchronisation Status of Posted Writes to SR0 8 1 read-only WSYNCCNT0 Synchronisation Status of Posted Writes to CNT0 9 1 read-only WSYNCCNT1 Synchronisation Status of Posted Writes to CNT1 10 1 read-only WSYNCALM0 Synchronisation Status of Posted Writes to ALM0 11 1 read-only WSYNCALM1 Synchronisation Status of Posted Writes to ALM1 12 1 read-only WSYNCTRM Synchronisation Status of Posted Writes to TRM 13 1 read-only ISOENB Visibility of 32kHz Sourced Registers 14 1 read-only SR1 0x00000008 16 RTC Status 1 0x00000078 WPNDCR0 Pending Status of Posted Writes to CR0 7 1 read-only WPNDSR0 Pending Status of Posted Clearances of Interrupt Sources in SR0 8 1 read-only WPNDCNT0 Pending Status of Posted Writes to CNT0 9 1 read-only WPNDCNT1 Pending Status of Posted Writes to CNT1 10 1 read-only WPNDALM0 Pending Status of Posted Writes to ALM0 11 1 read-only WPNDALM1 Pending Status of Posted Writes to ALM1 12 1 read-only WPNDTRM Pending Status of Posted Writes to TRM 13 1 read-only CNT0 0x0000000C 16 RTC Count 0 0x00000000 VALUE Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count 0 16 read-write 0x00000000 0x0000FFFF CNT1 0x00000010 16 RTC Count 1 0x00000000 VALUE Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count 0 16 read-write 0x00000000 0x0000FFFF ALM0 0x00000014 16 RTC Alarm 0 0x0000FFFF VALUE Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time 0 16 read-write 0x00000000 0x0000FFFF ALM1 0x00000018 16 RTC Alarm 1 0x0000FFFF VALUE Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time 0 16 read-write 0x00000000 0x0000FFFF TRM 0x0000001C 16 RTC Trim 0x00000398 VALUE Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL 0 3 read-write ADD Trim Polarity 3 1 read-write IVL Trim Interval in Prescaled RTC Time Units 4 2 read-write IVL2EXPMIN Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select 6 4 read-write 0x00000000 0x0000000F GWY 0x00000020 16 RTC Gateway 0x00000000 SWKEY Software-keyed Command Issued by the CPU 0 16 write-only 0x00000000 0x0000FFFF CR1 0x00000028 16 RTC Control 1 0x000001E0 CNTINTEN Enable for the RTC Count Interrupt Source 0 1 read-write PSINTEN Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT 1 1 read-write TRMINTEN Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT 2 1 read-write CNTROLLINTEN Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT 3 1 read-write CNTMOD60ROLLINTEN Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT 4 1 read-write PRESCALE2EXP Prescale Power of 2 Division Factor for the RTC Base Clock 5 4 read-write SR2 0x0000002C 16 RTC Status 2 0x0000C000 CNTINT RTC Count Interrupt Source 0 1 read-write PSINT RTC Prescaled, Modulo-1 Boundary Interrupt Source 1 1 read-write TRMINT RTC Trim Interrupt Source 2 1 read-write CNTROLLINT RTC Count Roll-Over Interrupt Source 3 1 read-write CNTMOD60ROLLINT RTC Modulo-60 Count Roll-Over Interrupt Source 4 1 read-write CNTROLL RTC Count Roll-Over 5 1 read-only CNTMOD60ROLL RTC Count Modulo-60 Roll-Over 6 1 read-only TRMBDYMIR Mirror of MOD:RTCTRMBDY 7 1 read-only WPNDCR1MIR Pending Status of Posted Writes to CR1 12 1 read-only WPNDALM2MIR Pending Status of Posted Writes to ALM2 13 1 read-only WSYNCCR1MIR Synchronization Status of Posted Writes to CR1 14 1 read-only WSYNCALM2MIR Synchronization Status of Posted Writes to ALM2 15 1 read-only SNAP0 0x00000030 16 RTC Snapshot 0 0x00000000 VALUE Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 0 16 read-only SNAP1 0x00000034 16 RTC Snapshot 1 0x00000000 VALUE Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 0 16 read-only SNAP2 0x00000038 16 RTC Snapshot 2 0x00000000 VALUE Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 0 15 read-only MOD 0x0000003C 16 RTC Modulo 0x00000040 CNTMOD60 Modulo-60 Value of the RTC Count: CNT1 and CNT0 0 6 read-only INCR Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 6 4 read-only TRMBDY Trim Boundary Indicator 10 1 read-only CNT0_4TOZERO Mirror of CNT0[4:0] 11 5 read-only CNT2 0x00000040 16 RTC Count 2 0x00000000 VALUE Fractional Bits of the RTC Real-Time Count 0 15 read-only ALM2 0x00000044 16 RTC Alarm 2 0x00000000 VALUE Fractional Bits of the Alarm Target Time 0 15 read-write 0x00000000 0x00007FFF SR3 0x00000048 16 RTC Status 3 0x00000000 IC0IRQ Sticky Interrupt Source for the RTC Input Capture Channel 0 0 1 read-write IC2IRQ Sticky Interrupt Source for the RTC Input Capture Channel 2 2 1 read-write IC3IRQ Sticky Interrupt Source for the RTC Input Capture Channel 3 3 1 read-write IC4IRQ Sticky Interrupt Source for the RTC Input Capture Channel 4 4 1 read-write ALMINTMIR Read-only Mirror of the ALMINT Interrupt Source in SR0 Register 8 1 read-only SS1IRQ Sticky Interrupt Source for SensorStrobe Channel 1 9 1 read-write CR2IC 0x0000004C 16 RTC Control 2 for Configuring Input Capture Channels 0x000083A0 IC0EN Enable for the RTC Input Capture Channel 0 0 1 read-write IC2EN Enable for the RTC Input Capture Channel 2 2 1 read-write IC3EN Enable for the RTC Input Capture Channel 3 3 1 read-write IC4EN Enable for the RTC Input Capture Channel 4 4 1 read-write IC0LH Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 5 1 read-write IC2LH Polarity of the Active-going Capture Edge for the Input Capture Channel 2 7 1 read-write IC3LH Polarity of the Active-going Capture Edge for the Input Capture Channel 3 8 1 read-write IC4LH Polarity of the Active-going Capture Edge for the Input Capture Channel 4 9 1 read-write IC0IRQEN Interrupt Enable for the RTC Input Capture Channel 0 10 1 read-write IC2IRQEN Interrupt Enable for the RTC Input Capture Channel 2 12 1 read-write IC3IRQEN Interrupt Enable for the RTC Input Capture Channel 3 13 1 read-write IC4IRQEN Interrupt Enable for the RTC Input Capture Channel 4 14 1 read-write ICOWUSEN Enable Overwrite of Unread Snapshots for All Input Capture Channels 15 1 read-write CR3SS 0x00000050 16 RTC Control 3 for Configuring SensorStrobe Channel 0x00000000 SS1EN Enable for SensorStrobe Channel 1 1 1 read-write SS1IRQEN Interrupt Enable for SensorStrobe Channel 1 9 1 read-write CR4SS 0x00000054 16 RTC Control 4 for Configuring SensorStrobe Channel 0x00000000 SS1MSKEN Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 1 1 read-write NO_MSK Do not apply a mask to SensorStrobe Channel 1 Register 0 THERM_MSK Apply thermometer decoded mask 1 SS1ARLEN Enable for Auto-Reloading When SensorStrobe Match Occurs 9 1 read-write SSMSK 0x00000058 16 RTC Mask for SensorStrobe Channel 0x00000000 SSMSK Thermometer-Encoded Masks for SensorStrobe Channels 0 16 read-write 0x00000000 0x0000FFFF SS1ARL 0x0000005C 16 RTC Auto-Reload for SensorStrobe Channel 1 0x00000000 SS1ARL Auto-Reload Value When SensorStrobe Match Occurs 0 16 read-write 0x00000000 0x0000FFFF IC2 0x00000064 16 RTC Input Capture Channel 2 0x00000000 IC2 RTC Input Capture Channel 2 0 16 read-only IC3 0x00000068 16 RTC Input Capture Channel 3 0x00000000 IC3 RTC Input Capture Channel 3 0 16 read-only IC4 0x0000006C 16 RTC Input Capture Channel 4 0x00000000 IC4 RTC Input Capture Channel 4 0 16 read-only SS1 0x00000070 16 RTC SensorStrobe Channel 1 0x00008000 SS1 SensorStrobe Channel 1 0 16 read-write 0x00000000 0x0000FFFF SR4 0x00000080 16 RTC Status 4 0x000077FF WSYNCSR3 Synchronisation Status of Posted Writes to SR3 0 1 read-only WSYNCCR2IC Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WSYNCCR3SS Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register 2 1 read-only WSYNCCR4SS Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register 3 1 read-only WSYNCSSMSK Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register 4 1 read-only WSYNCSS1ARL Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register 5 1 read-only WSYNCSS1 Synchronization Status of Posted Writes to SensorStrobe Channel 1 6 1 read-only RSYNCIC0 Synchronization Status of Posted Reads of RTC Input Channel 0 10 1 read-only RSYNCIC2 Synchronization Status of Posted Reads of RTC Input Channel 2 12 1 read-only RSYNCIC3 Synchronization Status of Posted Reads of RTC Input Channel 3 13 1 read-only RSYNCIC4 Synchronization Status of Posted Reads of RTC Input Channel 4 14 1 read-only SR5 0x00000084 16 RTC Status 5 0x00000000 WPENDSR3 Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register 0 1 read-only WPENDCR2IC Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WPENDCR3SS Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register 2 1 read-only WPENDCR4SS Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register 3 1 read-only WPENDSSMSK Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register 4 1 read-only WPENDSS1ARL Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register 5 1 read-only WPENDSS1 Pending Status of Posted Writes to SensorStrobe Channel 1 6 1 read-only RPENDIC0 Pending Status of Posted Reads of Input Capture Channel 0 10 1 read-only RPENDIC2 Pending Status of Posted Reads of IC2 12 1 read-only RPENDIC3 Pending Status of Posted Reads of IC3 13 1 read-only RPENDIC4 Pending Status of Posted Reads of IC4 14 1 read-only SR6 0x00000088 16 RTC Status 6 0x00007900 IC0UNR Sticky Unread Status of the Input Capture Channel 0 0 1 read-only IC2UNR Sticky Unread Status of the Input Capture Channel 2 2 1 read-only IC3UNR Sticky Unread Status of the Input Capture Channel 3 3 1 read-only IC4UNR Sticky Unread Status of the Input Capture Channel 4 4 1 read-only IC0SNAP Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 8 1 read-only FRZCNTPTR Pointer for the Triple-Read Sequence of FRZCNT 9 2 read-only SS1TGT 0x0000008C 16 RTC SensorStrobe Channel 1 Target 0x00008000 SS1TGT Current Target Value for the SensorStrobe Channel 1 0 16 read-only FRZCNT 0x00000090 16 RTC Freeze Count 0x00000000 FRZCNT RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count 0 16 read-only RTC1 0x40001400 RTC1_EVT 0 Event SYS System Identification and Debug Enable 0x40002000 SYS 0 0x00000080 registers SYS_GPIO_INTA 9 GPIO Interrupt A SYS_GPIO_INTB 10 GPIO Interrupt B ADIID 0x00000020 16 ADI Identification 0x00004144 VALUE ADI Cortex Device 0 16 read-only CHIPID 0x00000024 16 Chip Identifier 0x00000282 REV Silicon Revision 0 4 read-only PARTID Part Identifier 4 12 read-only SWDEN 0x00000040 16 Serial Wire Debug Enable 0x00007072 VALUE SWD Interface Enable 0 16 write-only 0x00000000 0x0000FFFF WDT0 Watchdog Timer 0x40002C00 WDT0 0 0x00000020 registers WDT_EXP 5 Expiration LOAD 0x00000000 16 Load Value 0x00001000 VALUE Load Value 0 16 read-write 0x00000000 0x0000FFFF CCNT 0x00000004 16 Current Count Value 0x00001000 VALUE Current Count Value 0 16 read-only CTL 0x00000008 16 Control 0x000000E9 IRQ Timer Interrupt 1 1 read-write RST WDT asserts reset when timed out 0 INT WDT generates interrupt when timed out 1 PRE Prescaler 2 2 read-write div1 Source clock/1 0 div16 Source clock/16 1 div256 Source clock/256 (default) 2 EN Timer Enable 5 1 read-write WDT_DIS WDT not enabled 0 WDT_EN WDT enabled 1 MODE Timer Mode 6 1 read-write FREE_RUN Free running mode 0 PERIODIC Periodic mode 1 SPARE Unused Spare Bit 7 1 read-write 0x00000000 0x00000001 RESTART 0x0000000C 16 Clear Interrupt 0x00000000 CLRWORD Clear Watchdog 0 16 write-only 0x00000000 0x0000FFFF STAT 0x00000018 16 Status 0x00000000 IRQ WDT Interrupt 0 1 read-only CLRIRQ Clear Interrupt Register Write Sync in Progress 1 1 read-only LOADING Load Register Write Sync in Progress 2 1 read-only LOAD_MATCH APB and WDT clock domains LOAD values match. 0 LOAD_SYNCING APB LOAD value is being synchronized to WDT clock domain. 1 COUNTING Control Register Write Sync in Progress 3 1 read-only COUNT_MATCH APB and WDT clock domain CTRL values match 0 COUNT_SYNCING APB CTRL register values are being synchronized to WDT clock domain. 1 LOCKED Lock Status Bit 4 1 read-only I2C0 I2C Master/Slave 0x40003000 I2C0 0 0x00000080 registers I2C_SLV_EVT 17 Slave Event I2C_MST_EVT 18 Master Event MCTL 0x00000000 16 Master Control 0x00000000 MASEN Master Enable 0 1 read-write 0x00000000 0x00000001 COMPLETE Start Back-off Disable 1 1 read-write 0x00000000 0x00000001 LOOPBACK Internal Loopback Enable 2 1 read-write 0x00000000 0x00000001 STRETCHSCL Stretch SCL Enable 3 1 read-write 0x00000000 0x00000001 IENMRX Receive Request Interrupt Enable 4 1 read-write 0x00000000 0x00000001 IENMTX Transmit Request Interrupt Enable 5 1 read-write 0x00000000 0x00000001 IENALOST Arbitration Lost Interrupt Enable 6 1 read-write 0x00000000 0x00000001 IENACK ACK Not Received Interrupt Enable 7 1 read-write 0x00000000 0x00000001 IENCMP Transaction Completed (or Stop Detected) Interrupt Enable 8 1 read-write 0x00000000 0x00000001 MXMITDEC Decrement Master Tx FIFO Status When a Byte Txed 9 1 read-write 0x00000000 0x00000001 MRXDMA Enable Master Rx DMA Request 10 1 write-only 0x00000000 0x00000001 MTXDMA Enable Master Tx DMA Request 11 1 write-only 0x00000000 0x00000001 BUSCLR Bus-Clear Enable 12 1 read-write 0x00000000 0x00000001 STOPBUSCLR Prestop Bus Clear 13 1 read-write 0x00000000 0x00000001 MSTAT 0x00000004 16 Master Status 0x00006000 MTXF Master Transmit FIFO Status 0 2 read-only FIFO_EMPTY FIFO Empty. 0 FIFO_1BYTE 1 byte in FIFO. 2 FIFO_FULL FIFO Full. 3 MTXREQ Master Transmit Request/Clear Master Transmit Interrupt 2 1 read-write 0x00000000 0x00000001 MRXREQ Master Receive Request 3 1 read-only NACKADDR ACK Not Received in Response to an Address 4 1 read-only ALOST Arbitration Lost 5 1 read-only MBUSY Master Busy 6 1 read-only NACKDATA ACK Not Received in Response to Data Write 7 1 read-only TCOMP Transaction Complete or Stop Detected 8 1 read-only MRXOVR Master Receive FIFO Overflow 9 1 read-only LINEBUSY Line is Busy 10 1 read-only MSTOP STOP Driven by This I2C Master 11 1 read-only MTXUNDR Master Transmit Underflow 12 1 read-only SDAFILT State of SDA Line 13 1 read-only SCLFILT State of SCL Line 14 1 read-only MRX 0x00000008 16 Master Receive Data 0x00000000 VALUE Master Receive Register 0 8 read-only MTX 0x0000000C 16 Master Transmit Data 0x00000000 VALUE Master Transmit Register 0 8 read-write 0x00000000 0x000000FF MRXCNT 0x00000010 16 Master Receive Data Count 0x00000000 VALUE Receive Count 0 8 read-write 0x00000000 0x000000FF EXTEND Extended Read 8 1 read-write 0x00000000 0x00000001 MCRXCNT 0x00000014 16 Master Current Receive Data Count 0x00000000 VALUE Current Receive Count 0 8 read-only ADDR1 0x00000018 16 Master Address Byte 1 0x00000000 VALUE Address Byte 1 0 8 read-write 0x00000000 0x000000FF ADDR2 0x0000001C 16 Master Address Byte 2 0x00000000 VALUE Address Byte 2 0 8 read-write 0x00000000 0x000000FF BYT 0x00000020 16 Start Byte 0x00000000 SBYTE Start Byte 0 8 read-write 0x00000000 0x000000FF DIV 0x00000024 16 Serial Clock Period Divisor 0x00001F1F LOW Serial Clock Low Time 0 8 read-write 0x00000000 0x000000FF HIGH Serial Clock High Time 8 8 read-write 0x00000000 0x000000FF SCTL 0x00000028 16 Slave Control 0x00000000 SLVEN Slave Enable 0 1 read-write 0x00000000 0x00000001 ADR10EN Enabled 10-bit Addressing 1 1 read-write 0x00000000 0x00000001 GCEN General Call Enable 2 1 read-write 0x00000000 0x00000001 HGCEN Hardware General Call Enable 3 1 read-write 0x00000000 0x00000001 GCSBCLR General Call Status Bit Clear 4 1 write-only 0x00000000 0x00000001 EARLYTXR Early Transmit Request Mode 5 1 read-write 0x00000000 0x00000001 NACK NACK Next Communication 7 1 read-write 0x00000000 0x00000001 IENSTOP Stop Condition Detected Interrupt Enable 8 1 read-write 0x00000000 0x00000001 IENSRX Slave Receive Request Interrupt Enable 9 1 read-write 0x00000000 0x00000001 IENSTX Slave Transmit Request Interrupt Enable 10 1 read-write 0x00000000 0x00000001 STXDEC Decrement Slave Tx FIFO Status When a Byte is Txed 11 1 read-write 0x00000000 0x00000001 IENREPST Repeated Start Interrupt Enable 12 1 read-write 0x00000000 0x00000001 SRXDMA Enable Slave Rx DMA Request 13 1 read-write 0x00000000 0x00000001 STXDMA Enable Slave Tx DMA Request 14 1 read-write 0x00000000 0x00000001 SSTAT 0x0000002C 16 Slave I2C Status/Error/IRQ 0x00000001 STXFSEREQ Slave Tx FIFO Status or Early Request 0 1 read-write 0x00000000 0x00000001 STXUNDR Slave Transmit FIFO Underflow 1 1 read-only STXREQ Slave Transmit Request/Slave Transmit Interrupt 2 1 read-only SRXREQ Slave Receive Request 3 1 read-only SRXOVR Slave Receive FIFO Overflow 4 1 read-only NOACK ACK Not Generated by the Slave 5 1 read-only SBUSY Slave Busy 6 1 read-only GCINT General Call Interrupt 7 1 read-only GCID General ID 8 2 read-only STOP Stop After Start and Matching Address 10 1 read-only IDMAT Device ID Matched 11 2 read-only REPSTART Repeated Start and Matching Address 13 1 read-only START Start and Matching Address 14 1 read-only SRX 0x00000030 16 Slave Receive 0x00000000 VALUE Slave Receive Register 0 8 read-only STX 0x00000034 16 Slave Transmit 0x00000000 VALUE Slave Transmit Register 0 8 read-write 0x00000000 0x000000FF ALT 0x00000038 16 Hardware General Call ID 0x00000000 ID Slave Alt 0 8 read-write 0x00000000 0x000000FF ID0 0x0000003C 16 First Slave Address Device ID 0x00000000 VALUE Slave Device ID 0 0 8 read-write 0x00000000 0x000000FF ID1 0x00000040 16 Second Slave Address Device ID 0x00000000 VALUE Slave Device ID 1 0 8 read-write 0x00000000 0x000000FF ID2 0x00000044 16 Third Slave Address Device ID 0x00000000 VALUE Slave Device ID 2 0 8 read-write 0x00000000 0x000000FF ID3 0x00000048 16 Fourth Slave Address Device ID 0x00000000 VALUE Slave Device ID 3 0 8 read-write 0x00000000 0x000000FF STAT 0x0000004C 16 Master and Slave FIFO Status 0x00000000 STXF Slave Transmit FIFO Status 0 2 read-only SRXF Slave Receive FIFO Status 2 2 read-only MTXF Master Transmit FIFO Status 4 2 read-only MRXF Master Receive FIFO Status 6 2 read-only SFLUSH Flush the Slave Transmit FIFO 8 1 write-only 0x00000000 0x00000001 MFLUSH Flush the Master Transmit FIFO 9 1 write-only 0x00000000 0x00000001 SHCTL 0x00000050 16 Shared Control 0x00000000 RST Reset START STOP Detect Circuit 0 1 write-only 0x00000000 0x00000001 TCTL 0x00000054 16 Timing Control Register 0x00000005 THDATIN Data in Hold Start 0 5 read-write 0x00000000 0x0000001F FILTEROFF Input Filter Control 8 1 read-write ASTRETCH_SCL 0x00000058 16 Automatic Stretch SCL 0x00000000 MST Master Automatic Stretch Mode 0 4 read-write 0x00000000 0x0000000F SLV Slave Automatic Stretch Mode 4 4 read-write 0x00000000 0x0000000F MSTTMO Master Automatic Stretch Timeout 8 1 read-only SLVTMO Slave Automatic Stretch Timeout 9 1 read-only SPI0 Serial Peripheral Interface 0x40004000 SPI0 0 0x00000100 registers SPI0_EVT 15 Event STAT 0x00000000 16 Status 0x00000800 IRQ SPI Interrupt Status 0 1 read-only XFRDONE SPI Transfer Completion 1 1 read-only TXEMPTY SPI Tx FIFO Empty Interrupt 2 1 read-only TXDONE SPI Tx Done in Read Command Mode 3 1 read-only TXUNDR SPI Tx FIFO Underflow 4 1 read-only TXIRQ SPI Tx IRQ 5 1 read-only RXIRQ SPI Rx IRQ 6 1 read-only RXOVR SPI Rx FIFO Overflow 7 1 read-only CS CS Status 11 1 read-only CSERR Detected a CS Error Condition in Slave Mode 12 1 read-only CSRISE Detected a Rising Edge on CS, in Slave CON Mode 13 1 read-only CSFALL Detected a Falling Edge on CS, in Slave CON Mode 14 1 read-only RDY Detected an Edge on Ready Indicator for Flow Control 15 1 read-only RX 0x00000004 16 Receive 0x00000000 BYTE1 8-bit Receive Buffer 0 8 read-only BYTE2 8-bit Receive Buffer, Used Only in DMA Modes 8 8 read-only TX 0x00000008 16 Transmit 0x00000000 BYTE1 8-bit Transmit Buffer 0 8 write-only 0x00000000 0x000000FF BYTE2 8-bit Transmit Buffer, Used Only in DMA Modes 8 8 write-only 0x00000000 0x000000FF DIV 0x0000000C 16 SPI Baud Rate Selection 0x00000000 VALUE SPI Clock Divider 0 6 read-write 0x00000000 0x0000003F CTL 0x00000010 16 SPI Configuration 0x00000000 SPIEN SPI Enable 0 1 read-write MASEN Master Mode Enable 1 1 read-write CPHA Serial Clock Phase Mode 2 1 read-write CPOL Serial Clock Polarity 3 1 read-write WOM SPI Wired-OR Mode 4 1 read-write LSB LSB First Transfer Enable 5 1 read-write TIM SPI Transfer and Interrupt Mode 6 1 read-write 0x00000000 0x00000001 ZEN Transmit Zeros Enable 7 1 read-write 0x00000000 0x00000001 RXOF Rx Overflow Overwrite Enable 8 1 read-write 0x00000000 0x00000001 OEN Slave MISO Output Enable 9 1 read-write 0x00000000 0x00000001 LOOPBACK Loopback Enable 10 1 read-write 0x00000000 0x00000001 CON Continuous Transfer Enable 11 1 read-write 0x00000000 0x00000001 RFLUSH SPI Rx FIFO Flush Enable 12 1 read-write 0x00000000 0x00000001 TFLUSH SPI Tx FIFO Flush Enable 13 1 read-write 0x00000000 0x00000001 CSRST Reset Mode for CS Error Bit 14 1 read-write 0x00000000 0x00000001 IEN 0x00000014 16 SPI Interrupts Enable 0x00000000 IRQMODE SPI IRQ Mode Bits 0 3 read-write CS Enable Interrupt on Every CS Edge in Slave CON Mode 8 1 read-write 0x00000000 0x00000001 TXUNDR Tx Underflow Interrupt Enable 9 1 read-write RXOVR Rx Overflow Interrupt Enable 10 1 read-write RDY Ready Signal Edge Interrupt Enable 11 1 read-write TXDONE SPI Transmit Done Interrupt Enable 12 1 read-write XFRDONE SPI Transfer Completion Interrupt Enable 13 1 read-write TXEMPTY Tx FIFO Empty Interrupt Enable 14 1 read-write CNT 0x00000018 16 Transfer Byte Count 0x00000000 VALUE Transfer Byte Count 0 14 read-write 0x00000000 0x00003FFF FRAMECONT Continue Frame 15 1 read-write DMA 0x0000001C 16 SPI DMA Enable 0x00000000 EN Enable DMA for Data Transfer 0 1 read-write 0x00000000 0x00000001 TXEN Enable Transmit DMA Request 1 1 read-write 0x00000000 0x00000001 RXEN Enable Receive DMA Request 2 1 read-write 0x00000000 0x00000001 FIFO_STAT 0x00000020 16 FIFO Status 0x00000000 TX SPI Tx FIFO Status 0 4 read-only RX SPI Rx FIFO Dtatus 8 4 read-only RD_CTL 0x00000024 16 Read Control 0x00000000 CMDEN Read Command Enable 0 1 read-write OVERLAP Tx/Rx Overlap Mode 1 1 read-write TXBYTES Transmit Byte Count - 1 (Read Command) 2 4 read-write 0x00000000 0x0000000F THREEPIN Three Pin SPI Mode 8 1 read-write FLOW_CTL 0x00000028 16 Flow Control 0x00000000 MODE Flow Control Mode 0 2 read-write RDYPOL Polarity of RDY/MISO Line 4 1 read-write RDBURSTSZ Read Data Burst Size - 1 8 4 read-write 0x00000000 0x0000000F WAIT_TMR 0x0000002C 16 Wait Timer for Flow Control 0x00000000 VALUE Wait Timer 0 16 read-write 0x00000000 0x0000FFFF CS_CTL 0x00000030 16 Chip Select Control for Multi-slave Connections 0x00000001 SEL Chip Select Control 0 4 read-write 0x00000000 0x0000000F CS_OVERRIDE 0x00000034 16 Chip Select Override 0x00000000 CTL CS Override Control 0 2 read-write SPI1 0x40004400 SPI1_EVT 42 Event SPI2 0x40024000 SPI2_EVT 16 Event UART0 Unknown 0x40005000 UART0 0 0x00000100 registers UART_EVT 14 Event RX 0x00000000 16 Receive Buffer Register 0x00000000 RBR Receive Buffer Register 0 8 read-only TX 0x00000000 16 Transmit Holding Register RX 0x00000000 THR Transmit Holding Register 0 8 write-only 0x00000000 0x000000FF IEN 0x00000004 16 Interrupt Enable 0x00000000 ERBFI Receive Buffer Full Interrupt 0 1 read-write ETBEI Transmit Buffer Empty Interrupt 1 1 read-write ELSI Rx Status Interrupt 2 1 read-write EDSSI Modem Status Interrupt 3 1 read-write EDMAT DMA Requests in Transmit Mode 4 1 read-write EDMAR DMA Requests in Receive Mode 5 1 read-write IIR 0x00000008 16 Interrupt ID 0x00000001 NIRQ Interrupt Flag 0 1 read-only STAT Interrupt Status 1 3 read-only STAT_EDSSI Modem status interrupt (Read MSR register to clear) 0 STAT_ETBEI Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) 1 STAT_ERBFI Receive buffer full interrupt (Read Rx register to clear) 2 STAT_RLSI Receive line status interrupt (Read LSR register to clear) 3 STAT_RFTOI Receive FIFO time-out interrupt (Read Rx register to clear) 6 FEND FIFO Enabled 6 2 read-only LCR 0x0000000C 16 Line Control 0x00000000 WLS Word Length Select 0 2 read-write STOP Stop Bit 2 1 read-write PEN Parity Enable 3 1 read-write EPS Parity Select 4 1 read-write SP Stick Parity 5 1 read-write PAR_NOTFORCED Parity will not be forced based on Parity Select and Parity Enable bits. 0 PAR_FORCED Parity forced based on Parity Select and Parity Enable bits. 1 BRK Set Break 6 1 read-write MCR 0x00000010 16 Modem Control 0x00000000 DTR Data Terminal Ready 0 1 read-write RTS Request to Send 1 1 read-write OUT1 Output 1 2 1 read-write OUT2 Output 2 3 1 read-write LOOPBACK Loopback Mode 4 1 read-write LSR 0x00000014 16 Line Status 0x00000060 DR Data Ready 0 1 read-only OE Overrun Error 1 1 read-only PE Parity Error 2 1 read-only FE Framing Error 3 1 read-only BI Break Indicator 4 1 read-only THRE Transmit Register Empty 5 1 read-only TEMT Transmit and Shift Register Empty Status 6 1 read-only FIFOERR Rx FIFO Parity Error/Frame Error/Break Indication 7 1 read-only MSR 0x00000018 16 Modem Status 0x00000000 DCTS Delta CTS 0 1 read-only DDSR Delta DSR 1 1 read-only TERI Trailing Edge RI 2 1 read-only DDCD Delta DCD 3 1 read-only CTS Clear to Send 4 1 read-only DSR Data Set Ready 5 1 read-only RI Ring Indicator 6 1 read-only DCD Data Carrier Detect 7 1 read-only SCR 0x0000001C 16 Scratch Buffer 0x00000000 SCR Scratch 0 8 read-write 0x00000000 0x000000FF FCR 0x00000020 16 FIFO Control 0x00000000 FIFOEN FIFO Enable as to Work in 16550 Mode 0 1 read-write 0x00000000 0x00000001 RFCLR Clear Rx FIFO 1 1 write-only 0x00000000 0x00000001 TFCLR Clear Tx FIFO 2 1 write-only 0x00000000 0x00000001 FDMAMD FIFO DMA Mode 3 1 read-write MODE0 In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. 0 MODE1 in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. 1 RFTRIG Rx FIFO Trigger Level 6 2 read-write FBR 0x00000024 16 Fractional Baud Rate 0x00000000 DIVN Fractional Baud Rate N Divide Bits 0 to 2047 0 11 read-write 0x00000000 0x000007FF DIVM Fractional Baud Rate M Divide Bits 1 to 3 11 2 read-write 0x00000000 0x00000003 FBEN Fractional Baud Rate Generator Enable 15 1 read-write 0x00000000 0x00000001 DIV 0x00000028 16 Baud Rate Divider 0x00000000 DIV Baud Rate Divider 0 16 read-write 0x00000000 0x0000FFFF LCR2 0x0000002C 16 Second Line Control 0x00000002 OSR Over Sample Rate 0 2 read-write CTL 0x00000030 16 UART Control Register 0x00000100 FORCECLK Force UCLK on 1 1 read-write RXINV Invert Receiver Line 4 1 read-write NOTINV_RX Don't invert receiver line (idling high). 0 INV_RX Invert receiver line (idling low). 1 REV UART Revision ID 8 8 read-only RFC 0x00000034 16 RX FIFO Byte Count 0x00000000 RFC Current Rx FIFO Data Bytes 0 5 read-only TFC 0x00000038 16 TX FIFO Byte Count 0x00000000 TFC Current Tx FIFO Data Bytes 0 5 read-only RSC 0x0000003C 16 RS485 Half-duplex Control 0x00000000 OENP SOUT_EN Polarity 0 1 read-write OENSP SOUT_EN De-assert Before Full Stop Bit(s) 1 1 read-write DISRX Disable Rx When Transmitting 2 1 read-write 0x00000000 0x00000001 DISTX Hold off Tx When Receiving 3 1 read-write 0x00000000 0x00000001 ACR 0x00000040 16 Auto Baud Control 0x00000000 ABE Auto Baud Enable 0 1 read-write DIS_AUTOBAUD Disable auto baudrate 0 EN_AUTOBAUD Enable auto baudrate 1 DNIEN Enable Done Interrupt 1 1 read-write DIS_DONEINT Disable done interrupt 0 EN_DONEINT Enable done interrupt 1 TOIEN Enable Time-out Interrupt 2 1 read-write DIS_TIMEOUTINT Disable timeout interrupt 0 EN_TIMEOUTINT Enable timeout interrupt 1 SEC Starting Edge Count 4 3 read-write SEC_EDGE1 First edge 0 SEC_EDGE2 Second edge 1 SEC_EDGE3 Third edge 2 SEC_EDGE4 Fourth edge 3 SEC_EDGE5 Fifth edge 4 SEC_EDGE6 Sixth edge 5 SEC_EDGE7 Seventh edge 6 SEC_EDGE8 Eighth edge 7 EEC Ending Edge Count 8 4 read-write EEC_EDGE1 First edge 0 EEC_EDGE2 Second edge 1 EEC_EDGE3 Third edge 2 EEC_EDGE4 Fourth edge 3 EEC_EDGE5 Fifth edge 4 EEC_EDGE6 Sixth edge 5 EEC_EDGE7 Seventh edge 6 EEC_EDGE8 Eighth edge 7 EEC_EDGE9 Ninth edge 8 ASRL 0x00000044 16 Auto Baud Status (Low) 0x00000000 DONE Auto Baud Done Successfully 0 1 read-only BRKTO Timed Out Due to Long Time Break Condition 1 1 read-only NSETO Timed Out Due to No Valid Start Edge Found 2 1 read-only NEETO Timed Out Due to No Valid Ending Edge Found 3 1 read-only CNT CNT[11:0] Auto Baud Counter Value 4 12 read-only ASRH 0x00000048 16 Auto Baud Status (High) 0x00000000 CNT CNT[19:12] Auto Baud Counter Value 0 8 read-only BEEP0 Beeper Driver 0x40005C00 BEEP0 0 0x00000100 registers BEEP_EVT 45 Event CFG 0x00000000 16 Beeper Configuration 0x00000000 SEQREPEAT Beeper Sequence Repeat Value 0 8 read-write EN Beeper Enable 8 1 write-only ASTARTIRQ Tone A Start IRQ 10 1 read-write AENDIRQ Tone A End IRQ 11 1 read-write BSTARTIRQ Tone B Start IRQ 12 1 read-write BENDIRQ Tone B End IRQ 13 1 read-write SEQNEARENDIRQ Sequence 1 Cycle from End IRQ 14 1 read-write SEQATENDIRQ Sequence End IRQ 15 1 read-write STAT 0x00000004 16 Beeper Status 0x00000000 SEQREMAIN Remaining Tone-pair Iterations to Play in Sequence Mode 0 8 read-only BUSY Beeper is Busy 8 1 read-only ASTARTED Tone A Has Started 10 1 read-write 0x00000000 0x00000001 AENDED Tone A Has Ended 11 1 read-write 0x00000000 0x00000001 BSTARTED Tone B Has Started 12 1 read-write 0x00000000 0x00000001 BENDED Tone B Has Ended 13 1 read-write 0x00000000 0x00000001 SEQNEAREND Sequencer Last Tone-pair Has Started 14 1 read-write 0x00000000 0x00000001 SEQENDED Sequencer Has Ended 15 1 read-write 0x00000000 0x00000001 TONEA 0x00000008 16 Tone A Data 0x00000001 DUR Tone Duration 0 8 read-write FREQ Tone Frequency 8 7 read-write DIS Output Disable 15 1 read-write TONEB 0x0000000C 16 Tone B Data 0x00000001 DUR Tone Duration 0 8 read-write FREQ Tone Frequency 8 7 read-write DIS Output Disable 15 1 read-write ADC0 Unknown 0x40007000 ADC0 0 0x00000400 registers ADC0_EVT 46 Event CFG 0x00000000 16 ADC Configuration 0x00000000 PWRUP Powering up the ADC 0 1 read-write 0x00000000 0x00000001 VREFSEL Select Vref as 1.25V or 2.5V 1 1 read-write V_2p5 Vref = 2.5V 0 V_1p25 Vref = 1.25V 1 REFBUFEN Enable Internal Reference Buffer 2 1 read-write EXT_REF External reference is used 0 BUF_REF Reference buffer is enabled 1 EN Enable ADC Subsystem 4 1 read-write 0x00000000 0x00000001 STARTCAL Start a New Offset Calibration Cycle 5 1 read-write 0x00000000 0x00000001 RST Reset 6 1 read-write 0x00000000 0x00000001 SINKEN Enable Additional Sink Current Capability 7 1 read-write 0x00000000 0x00000001 TMPEN Power up Temperature Sensor 8 1 read-write 0x00000000 0x00000001 FAST_DISCH Fast Switchover of Vref from 2.5 to 1.25 9 1 read-write 0x00000000 0x00000001 PWRUP 0x00000004 16 ADC Power-up Time 0x0000020E WAIT Program This with 526/PCLKDIVCNT 0 10 read-write 0x00000000 0x000003FF CAL_WORD 0x00000008 16 Calibration Word 0x00000040 VALUE Offset Calibration Word 0 7 read-write 0x00000000 0x0000007F CNV_CFG 0x0000000C 16 ADC Conversion Configuration 0x00000000 SEL Selection of Channel(s) to Convert 0 8 read-write 0x00000000 0x000000FF BAT Battery Monitoring Enable 8 1 read-write 0x00000000 0x00000001 TMP Temperature Measurement 1 9 1 read-write 0x00000000 0x00000001 TMP2 Temperature Measurement 2 10 1 read-write 0x00000000 0x00000001 AUTOMODE Auto Mode Enable 12 1 read-write 0x00000000 0x00000001 DMAEN DMA Channel Enable 13 1 read-write 0x00000000 0x00000001 SINGLE Single Conversion Start 14 1 read-write 0x00000000 0x00000001 MULTI Multiple Conversions 15 1 read-write 0x00000000 0x00000001 CNV_TIME 0x00000010 16 ADC Conversion Time 0x00000000 SAMPTIME Sampling Time 0 8 read-write 0x00000000 0x000000FF DLY Delay Between Two Consecutive Conversions 8 8 read-write 0x00000000 0x000000FF AVG_CFG 0x00000014 16 Averaging Configuration 0x00004008 FACTOR Averaging Factor 0 8 read-write 0x00000000 0x000000FF OS Enable Oversampling 14 1 read-write 0x00000000 0x00000001 EN Enable Averaging on Channels Enabled in Enable Register 15 1 read-write 0x00000000 0x00000001 IRQ_EN 0x00000020 16 Interrupt Enable 0x00000000 CNVDONE Enable Conversion Done Interrupt 0 1 read-write 0x00000000 0x00000001 CALDONE Enable Interrupt for Calibration Done 10 1 read-write 0x00000000 0x00000001 OVF Enable Overflow Interrupt 11 1 read-write 0x00000000 0x00000001 ALERT Interrupt on Crossing Lower or Higher Limit Enable 12 1 read-write 0x00000000 0x00000001 RDY Set to Enable Interrupt When ADC is Ready to Convert 13 1 read-write 0x00000000 0x00000001 STAT 0x00000024 16 ADC Status 0x00000000 DONE0 Conversion Done on Channel 0 0 1 read-write 0x00000000 0x00000001 DONE1 Conversion Done on Channel 1 1 1 read-write 0x00000000 0x00000001 DONE2 Conversion Done on Channel 2 2 1 read-write 0x00000000 0x00000001 DONE3 Conversion Done on Channel 3 3 1 read-write 0x00000000 0x00000001 DONE4 Conversion Done on Channel 4 4 1 read-write 0x00000000 0x00000001 DONE5 Conversion Done on Channel 5 5 1 read-write 0x00000000 0x00000001 DONE6 Conversion Done on Channel 6 6 1 read-write 0x00000000 0x00000001 DONE7 Conversion Done on Channel 7 7 1 read-write 0x00000000 0x00000001 BATDONE Conversion Done - Battery Monitoring 8 1 read-write 0x00000000 0x00000001 TMPDONE Conversion Done for Temperature Sensing 9 1 read-write 0x00000000 0x00000001 TMP2DONE Conversion Done for Temperature Sensing 2 10 1 read-write 0x00000000 0x00000001 CALDONE Calibration Done 14 1 read-write 0x00000000 0x00000001 RDY ADC Ready to Start Converting 15 1 read-write 0x00000000 0x00000001 OVF 0x00000028 16 Overflow of Output Registers 0x00000000 CH0 Overflow in CH0_OUT 0 1 read-write 0x00000000 0x00000001 CH1 Overflow in CH1_OUT 1 1 read-write 0x00000000 0x00000001 CH2 Overflow in CH2_OUT 2 1 read-write 0x00000000 0x00000001 CH3 Overflow in CH3_OUT 3 1 read-write 0x00000000 0x00000001 CH4 Overflow in CH4_OUT 4 1 read-write 0x00000000 0x00000001 CH5 Overflow in CH5_OUT 5 1 read-write 0x00000000 0x00000001 CH6 Overflow in CH6_OUT 6 1 read-write 0x00000000 0x00000001 CH7 Overflow in CH7_OUT 7 1 read-write 0x00000000 0x00000001 BAT Overflow in BAT_OUT 8 1 read-write 0x00000000 0x00000001 TMP Overflow in TMP_OUT 9 1 read-write 0x00000000 0x00000001 TMP2 Overflow in TMP2_OUT 10 1 read-write 0x00000000 0x00000001 ALERT 0x0000002C 16 Alert Indication 0x00000000 HI0 Channel 0 High Alert Status 0 1 read-write 0x00000000 0x00000001 LO0 Channel 0 Low Alert Status 1 1 read-write 0x00000000 0x00000001 HI1 Channel 1 High Alert Status 2 1 read-write 0x00000000 0x00000001 LO1 Channel 1 Low Alert Status 3 1 read-write 0x00000000 0x00000001 HI2 Channel 2 High Alert Status 4 1 read-write 0x00000000 0x00000001 LO2 Channel 2 Low Alert Status 5 1 read-write 0x00000000 0x00000001 HI3 Channel 3 High Alert Status 6 1 read-write 0x00000000 0x00000001 LO3 Channel 3 Low Alert Status 7 1 read-write 0x00000000 0x00000001 CH0_OUT 0x00000030 16 Conversion Result Channel 0 0x00000000 RESULT Conversion Result of Channel 0 0 16 read-only CH1_OUT 0x00000034 16 Conversion Result Channel 1 0x00000000 RESULT Conversion Result of Channel 1 0 16 read-only CH2_OUT 0x00000038 16 Conversion Result Channel 2 0x00000000 RESULT Conversion Result of Channel 2 0 16 read-only CH3_OUT 0x0000003C 16 Conversion Result Channel 3 0x00000000 RESULT Conversion Result of Channel 3 0 16 read-only CH4_OUT 0x00000040 16 Conversion Result Channel 4 0x00000000 RESULT Conversion Result of Channel 4 0 16 read-only CH5_OUT 0x00000044 16 Conversion Result Channel 5 0x00000000 RESULT Conversion Result of Channel 5 0 16 read-only CH6_OUT 0x00000048 16 Conversion Result Channel 6 0x00000000 RESULT Conversion Result of Channel 6 0 16 read-only CH7_OUT 0x0000004C 16 Conversion Result Channel 7 0x00000000 RESULT Conversion Result of Channel 7 0 16 read-only BAT_OUT 0x00000050 16 Battery Monitoring Result 0x00000000 RESULT Conversion Result of Battery Monitoring 0 16 read-only TMP_OUT 0x00000054 16 Temperature Result 0x00000000 RESULT Conversion Result of Temperature Measurement 1 0 16 read-only TMP2_OUT 0x00000058 16 Temperature Result 2 0x00000000 RESULT Conversion Result of Temperature Measurement 2 0 16 read-only DMA_OUT 0x0000005C 16 DMA Output Register 0x00000000 RESULT Conversion Result for DMA 0 16 read-only LIM0_LO 0x00000060 16 Channel 0 Low Limit 0x00000000 VALUE Low Limit for Channel 0 0 12 read-write 0x00000000 0x00000FFF EN Enable Low Limit Comparison on Channel 0 15 1 read-write 0x00000000 0x00000001 LIM0_HI 0x00000064 16 Channel 0 High Limit 0x00000FFF VALUE High Limit for Channel 0 0 12 read-write 0x00000000 0x00000FFF EN Enable High Limit Comparison on Channel 0 15 1 read-write 0x00000000 0x00000001 HYS0 0x00000068 16 Channel 0 Hysteresis 0x00000000 VALUE Hysteresis Value for Channel 0 0 9 read-write 0x00000000 0x000001FF MONCYC Number of Conversion Cycles to Monitor Channel 0 12 3 read-write 0x00000000 0x00000007 EN Enable Hysteresis for Comparison on Channel 0 15 1 read-write 0x00000000 0x00000001 LIM1_LO 0x00000070 16 Channel 1 Low Limit 0x00000000 VALUE Low Limit for Channel 1 0 12 read-write 0x00000000 0x00000FFF EN Enable Low Limit Comparison on Channel 1 15 1 read-write 0x00000000 0x00000001 LIM1_HI 0x00000074 16 Channel 1 High Limit 0x00000FFF VALUE High Limit for Channel 1 0 12 read-write 0x00000000 0x00000FFF EN Enable High Limit Comparison on Channel 1 15 1 read-write 0x00000000 0x00000001 HYS1 0x00000078 16 Channel 1 Hysteresis 0x00000000 VALUE Hysteresis Value for Channel 1 0 9 read-write 0x00000000 0x000001FF MONCYC Number of Conversion Cycles to Monitor Channel 1 12 3 read-write 0x00000000 0x00000007 EN Enable Hysteresis for Comparison on Channel 1 15 1 read-write 0x00000000 0x00000001 LIM2_LO 0x00000080 16 Channel 2 Low Limit 0x00000000 VALUE Low Limit for Channel 2 0 12 read-write 0x00000000 0x00000FFF EN Enable Low Limit Comparison on Channel 2 15 1 read-write 0x00000000 0x00000001 LIM2_HI 0x00000084 16 Channel 2 High Limit 0x00000FFF VALUE High Limit for Channel 2 0 12 read-write 0x00000000 0x00000FFF EN Enable High Limit Comparison on Channel 15 1 read-write 0x00000000 0x00000001 HYS2 0x00000088 16 Channel 2 Hysteresis 0x00000000 VALUE Hysteresis Value for Channel 2 0 9 read-write 0x00000000 0x000001FF MONCYC Number of Conversion Cycles to Monitor Channel 2 12 3 read-write 0x00000000 0x00000007 EN Enable Hysteresis for Comparison on Channel 2 15 1 read-write 0x00000000 0x00000001 LIM3_LO 0x00000090 16 Channel 3 Low Limit 0x00000000 VALUE Low Limit for Channel 3 0 12 read-write 0x00000000 0x00000FFF EN Enable Low Limit Comparison on Channel 3 15 1 read-write 0x00000000 0x00000001 LIM3_HI 0x00000094 16 Channel 3 High Limit 0x00000FFF VALUE High Limit for Channel 3 0 12 read-write 0x00000000 0x00000FFF EN Enable High Limit Comparison on Channel 3 15 1 read-write 0x00000000 0x00000001 HYS3 0x00000098 16 Channel 3 Hysteresis 0x00000000 VALUE Hysteresis Value for Channel 3 0 9 read-write 0x00000000 0x000001FF MONCYC Number of Conversion Cycles to Monitor Channel 3 12 3 read-write 0x00000000 0x00000007 EN Enable Hysteresis for Comparison on Channel 3 15 1 read-write 0x00000000 0x00000001 CFG1 0x000000C0 16 Reference Buffer Low Power Mode 0x00000400 RBUFLP Enable Low Power Mode for Reference Buffer 0 1 read-write 0x00000000 0x00000001 DMA0 DMA 0x40010000 DMA0 0 0x00001000 registers DMA_CHAN_ERR 19 Channel Error DMA0_CH0_DONE 20 Channel 0 Done DMA0_CH1_DONE 21 Channel 1 Done DMA0_CH2_DONE 22 Channel 2 Done DMA0_CH3_DONE 23 Channel 3 Done DMA0_CH4_DONE 24 Channel 4 Done DMA0_CH5_DONE 25 Channel 5 Done DMA0_CH6_DONE 26 Channel 6 Done DMA0_CH7_DONE 27 Channel 7 Done DMA0_CH8_DONE 28 Channel 8 Done DMA0_CH9_DONE 29 Channel 9 Done DMA0_CH10_DONE 30 Channel 10 Done DMA0_CH11_DONE 31 Channel 11 Done DMA0_CH12_DONE 32 Channel 12 Done DMA0_CH13_DONE 33 Channel 13 Done DMA0_CH14_DONE 34 Channel 14 Done DMA0_CH15_DONE 35 Channel 15 Done DMA0_CH24_DONE 39 Channel 24 Done DMA0_CH16_DONE 56 Channel 16 Done DMA0_CH17_DONE 57 Channel 17 Done DMA0_CH18_DONE 58 Channel 18 Done DMA0_CH19_DONE 59 Channel 19 Done DMA0_CH20_DONE 60 Channel 20 Done DMA0_CH21_DONE 61 Channel 21 Done DMA0_CH22_DONE 62 Channel 22 Done DMA0_CH23_DONE 63 Channel 23 Done STAT 0x00000000 32 DMA Status 0x00180000 MEN Enable Status of the Controller 0 1 read-only CHANM1 Number of Available DMA Channels Minus 1 16 5 read-only CFG 0x00000004 32 DMA Configuration 0x00000000 MEN Controller Enable 0 1 write-only PDBPTR 0x00000008 32 DMA Channel Primary Control Database Pointer 0x00000000 ADDR Pointer to the Base Address of the Primary Data Structure 0 32 read-write 0x00000000 0xFFFFFFFF ADBPTR 0x0000000C 32 DMA Channel Alternate Control Database Pointer 0x00000200 ADDR Base Address of the Alternate Data Structure 0 32 read-only SWREQ 0x00000014 32 DMA Channel Software Request 0x00000000 CHAN Generate Software Request 0 25 write-only 0x00000000 0x01FFFFFF RMSK_SET 0x00000020 32 DMA Channel Request Mask Set 0x00000000 CHAN Mask Requests from DMA Channels 0 25 read-write 0x00000000 0x01FFFFFF RMSK_CLR 0x00000024 32 DMA Channel Request Mask Clear 0x00000000 CHAN Clear Request Mask Set Bits 0 25 write-only 0x00000000 0x01FFFFFF EN_SET 0x00000028 32 DMA Channel Enable Set 0x00000000 CHAN Enable DMA Channels 0 25 read-write 0x00000000 0x01FFFFFF EN_CLR 0x0000002C 32 DMA Channel Enable Clear 0x00000000 CHAN Disable DMA Channels 0 25 write-only 0x00000000 0x01FFFFFF ALT_SET 0x00000030 32 DMA Channel Primary Alternate Set 0x00000000 CHAN Control Structure Status / Select Alternate Structure 0 25 read-write 0x00000000 0x01FFFFFF ALT_CLR 0x00000034 32 DMA Channel Primary Alternate Clear 0x00000000 CHAN Select Primary Data Structure 0 25 write-only 0x00000000 0x01FFFFFF PRI_SET 0x00000038 32 DMA Channel Priority Set 0x00000000 CHAN Configure Channel for High Priority 0 25 write-only 0x00000000 0x01FFFFFF PRI_CLR 0x0000003C 32 DMA Channel Priority Clear 0x00000000 CHPRICLR Configure Channel for Default Priority Level 0 25 write-only 0x00000000 0x01FFFFFF ERRCHNL_CLR 0x00000048 32 DMA per Channel Error Clear 0x00000000 CHAN Per Channel Bus Error Status/Clear 0 25 read-write 0x00000000 0x01FFFFFF ERR_CLR 0x0000004C 32 DMA Bus Error Clear 0x00000000 CHAN Bus Error Status 0 25 read-write 0x00000000 0x01FFFFFF INVALIDDESC_CLR 0x00000050 32 DMA per Channel Invalid Descriptor Clear 0x00000000 CHAN Per Channel Invalid Descriptor Status/Clear 0 25 read-write 0x00000000 0x01FFFFFF BS_SET 0x00000800 32 DMA Channel Bytes Swap Enable Set 0x00000000 CHAN Byte Swap Status 0 25 read-write 0x00000000 0x01FFFFFF BS_CLR 0x00000804 32 DMA Channel Bytes Swap Enable Clear 0x00000000 CHAN Disable Byte Swap 0 25 write-only 0x00000000 0x01FFFFFF SRCADDR_SET 0x00000810 32 DMA Channel Source Address Decrement Enable Set 0x00000000 CHAN Source Address Decrement Status 0 25 read-write 0x00000000 0x01FFFFFF SRCADDR_CLR 0x00000814 32 DMA Channel Source Address Decrement Enable Clear 0x00000000 CHAN Disable Source Address Decrement 0 25 write-only 0x00000000 0x01FFFFFF DSTADDR_SET 0x00000818 32 DMA Channel Destination Address Decrement Enable Set 0x00000000 CHAN Destination Address Decrement Status 0 25 read-write 0x00000000 0x01FFFFFF DSTADDR_CLR 0x0000081C 32 DMA Channel Destination Address Decrement Enable Clear 0x00000000 CHAN Disable Destination Address Decrement 0 25 write-only 0x00000000 0x01FFFFFF REVID 0x00000FE0 32 DMA Controller Revision ID 0x00000002 VALUE DMA Controller Revision ID 0 8 read-only FLCC0 Flash Controller 0x40018000 FLCC0 0 0x00000100 registers STAT 0x00000000 32 Status 0x00000000 CMDBUSY Command Busy 0 1 read-only WRCLOSE WRITE Registers are Closed 1 1 read-only CMDCOMP Command Complete 2 1 read-only WRALCOMP Write Almost Complete 3 1 read-only CMDFAIL Provides Information on Command Failures 4 2 read-only SLEEPING Flash Array is in Low Power (Sleep) Mode 6 1 read-only ECCERRCMD ECC Errors Detected During User Issued SIGN Command 7 2 read-only ECCRDERR ECC IRQ Cause 9 2 read-only OVERLAP Overlapping Command 11 1 read-write 0x00000000 0x00000001 SIGNERR Signature Check Failure During Initialization 13 1 read-only INIT Flash Controller Initialization in Progress 14 1 read-only ECCINFOSIGN ECC Status of Flash Initialization 15 2 read-only ECCERRCNT ECC Correction Counter 17 3 read-only ECCICODE ICode AHB Bus Error ECC Status 25 2 read-only ECCDCODE DCode AHB Bus Error ECC Status 27 2 read-only CACHESRAMPERR SRAM Parity Errors in Cache Controller 29 1 read-only IEN 0x00000004 32 Interrupt Enable 0x00000060 CMDCMPLT Command Complete Interrupt Enable 0 1 read-write 0x00000000 0x00000001 WRALCMPLT Write Almost Complete Interrupt Enable 1 1 read-write 0x00000000 0x00000001 CMDFAIL Command Fail Interrupt Enable 2 1 read-write 0x00000000 0x00000001 ECC_ERROR Control 2-bit ECC Error Events 6 2 read-write NONE_err Do not generate a response to ECC events 0 BUS_ERR_err Generate Bus Errors in response to ECC events 1 IRQ_err Generate IRQs in response to ECC events 2 CMD 0x00000008 32 Command 0x00000000 VALUE Commands 0 4 read-write IDLE IDLE 0 ABORT ABORT 1 SLEEP Requests flash to enter Sleep mode 2 SIGN SIGN 3 WRITE WRITE 4 BLANK_CHECK Checks all of User Space; fails if any bits in user space are cleared 5 ERASEPAGE ERASEPAGE 6 MASSERASE MASSERASE 7 KH_ADDR 0x0000000C 32 Write Address 0x00000000 VALUE Key Hole Address 3 16 read-write 0x00000000 0x0000FFFF KH_DATA0 0x00000010 32 Write Lower Data 0xFFFFFFFF VALUE Lower 32 Bits of Key Hole Data 0 32 read-write 0x00000000 0xFFFFFFFF KH_DATA1 0x00000014 32 Write Upper Data 0xFFFFFFFF VALUE Upper Half of 64-bit Dualword Data to Be Written 0 32 read-write 0x00000000 0xFFFFFFFF PAGE_ADDR0 0x00000018 32 Lower Page Address 0x00000000 VALUE Lower Address Bits of the Page Address 10 9 read-write 0x00000000 0x000001FF PAGE_ADDR1 0x0000001C 32 Upper Page Address 0x00000000 VALUE Upper Address Bits of the Page Address 10 9 read-write 0x00000000 0x000001FF KEY 0x00000020 32 Key 0x00000000 VALUE Key Register 0 32 write-only WR_ABORT_ADDR 0x00000024 32 Write Abort Address 0x00000000 VALUE Address Targeted by an Ongoing Write Command 0 32 read-only WRPROT 0x00000028 32 Write Protection 0xFFFFFFFF WORD Write Protect 0 32 read-write 0x00000000 0xFFFFFFFF SIGNATURE 0x0000002C 32 Signature 0x00000000 VALUE Signature 0 32 read-only UCFG 0x00000030 32 User Configuration 0x00000000 KHDMAEN Key Hole DMA Enable 0 1 read-write 0x00000000 0x00000001 AUTOINCEN Auto Address Increment for Key Hole Access 1 1 read-write 0x00000000 0x00000001 TIME_PARAM0 0x00000034 32 Time Parameter 0 0xB8955950 DIVREFCLK Divide Reference Clock (by 2) 0 1 read-write 0x00000000 0x00000001 TNVS PROG/ERASE to NVSTR Setup Time 4 4 read-write 0x00000000 0x0000000F TPGS NVSTR to Program Setup Time 8 4 read-write 0x00000000 0x0000000F TPROG Program Time 12 4 read-write 0x00000000 0x0000000F TNVH NVSTR Hold Time 16 4 read-write 0x00000000 0x0000000F TRCV Recovery Time 20 4 read-write 0x00000000 0x0000000F TERASE Erase Time 24 4 read-write 0x00000000 0x0000000F TNVH1 NVSTR Hold Time During Mass Erase 28 4 read-write 0x00000000 0x0000000F TIME_PARAM1 0x00000038 32 Time Parameter 1 0x00000004 TWK Wakeup Time 0 4 read-write 0x00000000 0x0000000F ABORT_EN_LO 0x0000003C 32 IRQ Abort Enable (Lower Bits) 0x00000000 VALUE VALUE[31:0] Sys IRQ Abort Enable 0 32 read-write 0x00000000 0xFFFFFFFF ABORT_EN_HI 0x00000040 32 IRQ Abort Enable (Upper Bits) 0x00000000 VALUE VALUE[63:32] Sys IRQ Abort Enable 0 32 read-write 0x00000000 0xFFFFFFFF ECC_CFG 0x00000044 32 ECC Configuration 0x00000002 EN ECC Enable 0 1 read-write 0x00000000 0x00000001 INFOEN Info Space ECC Enable Bit 1 1 read-write 0x00000000 0x00000001 PTR ECC Start Page Pointer 8 24 read-write 0x00000000 0x00FFFFFF ECC_ADDR 0x00000048 32 ECC Status (Address) 0x00000000 VALUE ECC Error Address 0 19 read-only POR_SEC 0x00000050 32 Flash Security 0x00000000 SECURE Prevent Read/Write Access to User Space (Sticky When Set) 0 1 read-write 0x00000000 0x00000001 VOL_CFG 0x00000054 32 Volatile Flash Configuration 0x00000001 INFO_REMAP Alias the Info Space to the Base Address of User Space 0 1 read-write 0x00000000 0x00000001 FLCC0_CACHE Cache Controller 0x40018058 FLCC0_CACHE 0 0x00000100 registers STAT 0x00000000 32 Cache Status 0x00000000 ICEN I-Cache Enabled 0 1 read-only SETUP 0x00000004 32 Cache Setup 0x00000000 ICEN I-Cache Enable 0 1 read-write 0x00000000 0x00000001 KEY 0x00000008 32 Cache Key 0x00000000 VALUE Cache Key Register 0 32 write-only 0x00000000 0xFFFFFFFF GPIO0 Unknown 0x40020000 GPIO0 0 0x00004000 registers CFG 0x00000000 32 Port Configuration 0x00000000 PIN00 Pin 0 Configuration Bits 0 2 read-write 0x00000000 0x00000003 PIN01 Pin 1 Configuration Bits 2 2 read-write 0x00000000 0x00000003 PIN02 Pin 2 Configuration Bits 4 2 read-write 0x00000000 0x00000003 PIN03 Pin 3 Configuration Bits 6 2 read-write 0x00000000 0x00000003 PIN04 Pin 4 Configuration Bits 8 2 read-write 0x00000000 0x00000003 PIN05 Pin 5 Configuration Bits 10 2 read-write 0x00000000 0x00000003 PIN06 Pin 6 Configuration Bits 12 2 read-write 0x00000000 0x00000003 PIN07 Pin 7 Configuration Bits 14 2 read-write 0x00000000 0x00000003 PIN08 Pin 8 Configuration Bits 16 2 read-write 0x00000000 0x00000003 PIN09 Pin 9 Configuration Bits 18 2 read-write 0x00000000 0x00000003 PIN10 Pin 10 Configuration Bits 20 2 read-write 0x00000000 0x00000003 PIN11 Pin 11 Configuration Bits 22 2 read-write 0x00000000 0x00000003 PIN12 Pin 12 Configuration Bits 24 2 read-write 0x00000000 0x00000003 PIN13 Pin 13 Configuration Bits 26 2 read-write 0x00000000 0x00000003 PIN14 Pin 14 Configuration Bits 28 2 read-write 0x00000000 0x00000003 PIN15 Pin 15 Configuration Bits 30 2 read-write 0x00000000 0x00000003 OEN 0x00000004 16 Port Output Enable 0x00000000 VALUE Pin Output Drive Enable 0 16 read-write 0x00000000 0x0000FFFF PE 0x00000008 16 Port Output Pull-up/Pull-down Enable 0x000000C0 VALUE Pin Pull Enable 0 16 read-write 0x00000000 0x0000FFFF IEN 0x0000000C 16 Port Input Path Enable 0x00000000 VALUE Input Path Enable 0 16 read-write 0x00000000 0x0000FFFF IN 0x00000010 16 Port Registered Data Input 0x00000000 VALUE Registered Data Input 0 16 read-only OUT 0x00000014 16 Port Data Output 0x00000000 VALUE Data Out 0 16 read-write 0x00000000 0x0000FFFF SET 0x00000018 16 Port Data Out Set 0x00000000 VALUE Set the Output High for the Pin 0 16 write-only 0x00000000 0x0000FFFF CLR 0x0000001C 16 Port Data Out Clear 0x00000000 VALUE Set the Output Low for the Port Pin 0 16 write-only 0x00000000 0x0000FFFF TGL 0x00000020 16 Port Pin Toggle 0x00000000 VALUE Toggle the Output of the Port Pin 0 16 write-only 0x00000000 0x0000FFFF POL 0x00000024 16 Port Interrupt Polarity 0x00000000 VALUE Interrupt polarity 0 16 read-write 0x00000000 0x0000FFFF IENA 0x00000028 16 Port Interrupt A Enable 0x00000000 VALUE Interrupt A enable 0 16 read-write 0x00000000 0x0000FFFF IENB 0x0000002C 16 Port Interrupt B Enable 0x00000000 VALUE Interrupt B enable 0 16 read-write 0x00000000 0x0000FFFF INT 0x00000030 16 Port Interrupt Status 0x00000000 VALUE Interrupt Status 0 16 read-write 0x00000000 0x0000FFFF DS 0x00000034 16 Port Drive Strength Select 0x00000000 PIN00 Drive Strength Pin 00 0 1 read-write SINGLE_PIN00 Single Drive Strength 0 DOUBLE_PIN00 Double Drive Strength 1 PIN01 Drive Strength Pin 01 1 1 read-write SINGLE_PIN01 Single Drive Strength 0 DOUBLE_PIN01 Double Drive Strength 1 PIN02 Drive Strength Pin 02 2 1 read-write SINGLE_PIN02 Single Drive Strength 0 DOUBLE_PIN02 Double Drive Strength 1 PIN03 Drive Strength Pin 03 3 1 read-write SINGLE_PIN03 Single Drive Strength 0 DOUBLE_PIN03 Double Drive Strength 1 PIN04 Drive Strength Pin 04 4 1 read-write SINGLE_PIN04 Single Drive Strength 0 DOUBLE_PIN04 Double Drive Strength 1 PIN05 Drive Strength Pin 05 5 1 read-write SINGLE_PIN05 Single Drive Strength 0 DOUBLE_PIN05 Double Drive Strength 1 PIN06 Drive Strength Pin 06 6 1 read-write SINGLE_PIN06 Single Drive Strength 0 DOUBLE_PIN06 Double Drive Strength 1 PIN07 Drive Strength Pin 07 7 1 read-write SINGLE_PIN07 Single Drive Strength 0 DOUBLE_PIN07 Double Drive Strength 1 PIN08 Drive Strength Pin 08 8 1 read-write SINGLE_PIN08 Single Drive Strength 0 DOUBLE_PIN08 Double Drive Strength 1 PIN09 Drive Strength Pin 09 9 1 read-write SINGLE_PIN09 Single Drive Strength 0 DOUBLE_PIN09 Double Drive Strength 1 PIN10 Drive Strength Pin 10 10 1 read-write SINGLE_PIN10 Single Drive Strength 0 DOUBLE_PIN10 Double Drive Strength 1 PIN11 Drive Strength Pin 11 11 1 read-write SINGLE_PIN11 Single Drive Strength 0 DOUBLE_PIN11 Double Drive Strength 1 PIN12 Drive Strength Pin 12 12 1 read-write SINGLE_PIN12 Single Drive Strength 0 DOUBLE_PIN12 Double Drive Strength 1 PIN13 Drive Strength Pin 13 13 1 read-write SINGLE_PIN13 Single Drive Strength 0 DOUBLE_PIN13 Double Drive Strength 1 PIN14 Drive Strength Pin 14 14 1 read-write SINGLE_PIN14 Single Drive Strength 0 DOUBLE_PIN14 Double Drive Strength 1 PIN15 Drive Strength Pin 15 15 1 read-write SINGLE_PIN15 Single Drive Strength 0 DOUBLE_PIN15 Double Drive Strength 1 GPIO1 0x40020040 GPIO2 0x40020080 SPORT0 Serial Port 0x40038000 SPORT0 0 0x00000100 registers SPORT_A_EVT 36 Channel A Event SPORT_B_EVT 37 Channel B Event CTL_A 0x00000000 32 Half SPORT 'A' Control 0x00000000 SPEN Serial Port Enable 0 1 read-write CTL_DIS Disable 0 CTL_EN Enable 1 FSMUXSEL Frame Sync Multiplexer Select 1 1 read-write CTL_FS_MUX_DIS Disable frame sync multiplexing 0 CTL_FS_MUX_EN Enable frame sync multiplexing 1 CKMUXSEL Clock Multiplexer Select 2 1 read-write CTL_CLK_MUX_DIS Disable serial clock multiplexing 0 CTL_CLK_MUX_EN Enable serial clock multiplexing 1 LSBF Least-Significant Bit First 3 1 read-write CTL_MSB_FIRST MSB first sent/received 0 CTL_LSB_FIRST LSB first sent/received 1 SLEN Serial Word Length 4 5 read-write 0x00000000 0x0000001F ICLK Internal Clock 10 1 read-write CTL_EXTERNAL_CLK External clock 0 CTL_INTERNAL_CLK Internal clock 1 OPMODE Operation Mode 11 1 read-write CTL_SERIAL DSP standard 0 CTL_TIMER_EN_MODE Timer_enable mode 1 CKRE Clock Rising Edge 12 1 read-write CTL_CLK_FALL_EDGE Clock falling edge 0 CTL_CLK_RISE_EDGE Clock rising edge 1 FSR Frame Sync Required 13 1 read-write CTL_FS_NOT_REQ No frame sync required 0 CTL_FS_REQ Frame sync required 1 IFS Internal Frame Sync 14 1 read-write CTL_EXTERNAL_FS External frame sync 0 CTL_INTERNAL_FS Internal frame sync 1 DIFS Data-Independent Frame Sync 15 1 read-write CTL_DATA_DEP_FS Data-dependent frame sync 0 CTL_DATA_INDP_FS Data-independent frame sync 1 LFS Active-Low Frame Sync 16 1 read-write CTL_FS_LO Active high frame sync 0 CTL_FS_HI Active low frame sync 1 LAFS Late Frame Sync 17 1 read-write CTL_EARLY_FS Early frame sync 0 CTL_LATE_FS Late frame sync 1 PACK Packing Enable 18 2 read-write CTL_PACK_DIS Disable 0 CTL_PACK_8BIT 8-bit packing enable 1 CTL_PACK_16BIT 16-bit packing enable 2 CTL_PACK_RSV Reserved 3 FSERRMODE Frame Sync Error Operation 20 1 read-write GCLKEN Gated Clock Enable 21 1 read-write CTL_GCLK_DIS Disable 0 CTL_GCLK_EN Enable 1 SPTRAN Serial Port Transfer Direction 25 1 read-write CTL_RX Receive 0 CTL_TX Transmit 1 DMAEN DMA Enable 26 1 read-write DIV_A 0x00000004 32 Half SPORT 'A' Divisor 0x00000000 CLKDIV Clock Divisor 0 16 read-write 0x00000000 0x0000FFFF FSDIV Frame Sync Divisor 16 8 read-write 0x00000000 0x000000FF IEN_A 0x00000008 32 Half SPORT A's Interrupt Enable 0x00000000 TF Transfer Finish Interrupt Enable 0 1 read-write CTL_TXFIN_DIS Transfer finish Interrupt is disabled 0 CTL_TXFIN_EN Transfer Finish Interrupt is Enabled 1 DERRMSK Data Error (Interrupt) Mask 1 1 read-write FSERRMSK Frame Sync Error (Interrupt) Mask 2 1 read-write DATA Data Request Interrupt to the Core 3 1 read-write SYSDATERR Data Error for System Writes or Reads 4 1 read-write STAT_A 0x0000000C 32 Half SPORT A's Status 0x00000000 TFI Transmit Finish Interrupt Status 0 1 read-only DERR Data Error Status 1 1 read-only FSERR Frame Sync Error Status 2 1 read-only DATA Data Buffer Status 3 1 read-only SYSDATERR System Data Error Status 4 1 read-only DXS Data Transfer Buffer Status 8 2 read-only CTL_EMPTY Empty 0 CTL_RSV Reserved 1 CTL_PART_FULL Partially full 2 CTL_FULL Full 3 NUMTRAN_A 0x00000010 32 Half SPORT A Number of Transfers 0x00000000 VALUE Number of Transfers (Half SPORT A) 0 12 read-write 0x00000000 0x00000FFF CNVT_A 0x00000014 32 Half SPORT 'A' CNV Width 0x00000000 WID SPT_CNVT Signal Width: Half SPORT a 0 4 read-write 0x00000000 0x0000000F POL Polarity of the SPT_CNVT Signal 8 1 read-write CNVT2FS SPT_CNVT to FS Duration: Half SPORT a 16 8 read-write 0x00000000 0x000000FF TX_A 0x00000020 32 Half SPORT 'A' Tx Buffer 0x00000000 VALUE Transmit Buffer 0 32 write-only 0x00000000 0xFFFFFFFF RX_A 0x00000028 32 Half SPORT 'A' Rx Buffer 0x00000000 VALUE Receive Buffer 0 32 read-only CTL_B 0x00000040 32 Half SPORT 'B' Control 0x00000000 SPEN Serial Port Enable 0 1 read-write LSBF Least-Significant Bit First 3 1 read-write SLEN Serial Word Length 4 5 read-write 0x00000000 0x0000001F ICLK Internal Clock 10 1 read-write OPMODE Operation Mode 11 1 read-write CKRE Clock Rising Edge 12 1 read-write FSR Frame Sync Required 13 1 read-write IFS Internal Frame Sync 14 1 read-write DIFS Data-Independent Frame Sync 15 1 read-write LFS Active-Low Frame Sync 16 1 read-write LAFS Late Frame Sync 17 1 read-write PACK Packing Enable 18 2 read-write CTL_PACK_DIS Disable 0 CTL_PACK_8BIT 8-bit packing enable 1 CTL_PACK_16BIT 16-bit packing enable 2 CTL_PACK_RSV Reserved 3 FSERRMODE Frame Sync Error Operation 20 1 read-write GCLKEN Gated Clock Enable 21 1 read-write SPTRAN Serial Port Transfer Direction 25 1 read-write DMAEN DMA Enable 26 1 read-write DIV_B 0x00000044 32 Half SPORT 'B' Divisor 0x00000000 CLKDIV Clock Divisor 0 16 read-write 0x00000000 0x0000FFFF FSDIV Frame Sync Divisor 16 8 read-write 0x00000000 0x000000FF IEN_B 0x00000048 32 Half SPORT B's Interrupt Enable 0x00000000 TF Transmit Finish Interrupt Enable 0 1 read-write CTL_TXFIN_DIS Transfer Finish Interrupt is disabled 0 CTL_TXFIN_EN Transfer Finish Interrupt is Enabled 1 DERRMSK Data Error (Interrupt) Mask 1 1 read-write FSERRMSK Frame Sync Error (Interrupt) Mask 2 1 read-write DATA Data Request Interrupt to the Core 3 1 read-write SYSDATERR Data Error for System Writes or Reads 4 1 read-write STAT_B 0x0000004C 32 Half SPORT B's Status 0x00000000 TFI Transmit Finish Interrupt Status 0 1 read-only DERR Data Error Status 1 1 read-only FSERR Frame Sync Error Status 2 1 read-only DATA Data Buffer Status 3 1 read-only SYSDATERR System Data Error Status 4 1 read-only DXS Data Transfer Buffer Status 8 2 read-only CTL_EMPTY Empty 0 CTL_RSV Reserved 1 CTL_PART_FULL Partially full 2 CTL_FULL Full 3 NUMTRAN_B 0x00000050 32 Half SPORT B Number of Transfers 0x00000000 VALUE Number of Transfers (Half SPORT A) 0 12 read-write 0x00000000 0x00000FFF CNVT_B 0x00000054 32 Half SPORT 'B' CNV Width 0x00000000 WID SPT_CNVT Signal Width: Half SPORT B 0 4 read-write 0x00000000 0x0000000F POL Polarity of the SPT_CNVT Signal 8 1 read-write CNVT2FS SPT_CNVT to FS Duration: Half SPORT B 16 8 read-write 0x00000000 0x000000FF TX_B 0x00000060 32 Half SPORT 'B' Tx Buffer 0x00000000 VALUE Transmit Buffer 0 32 write-only 0x00000000 0xFFFFFFFF RX_B 0x00000068 32 Half SPORT 'B' Rx Buffer 0x00000000 VALUE Receive Buffer 0 32 read-only CRC0 CRC Accelerator 0x40040000 CRC0 0 0x00000100 registers CTL 0x00000000 32 CRC Control 0x10000000 EN CRC Peripheral Enable 0 1 read-write CRC_DIS CRC peripheral is disabled 0 CRC_EN CRC peripheral is enabled 1 LSBFIRST LSB First Calculation Order 1 1 read-write MSB_FIRST MSB First CRC calculation is done 0 LSB_FIRST LSB First CRC calculation is done 1 BITMIRR Bit Mirroring 2 1 read-write BITMIRR_DIS Bit Mirroring is disabled 0 BITMIRR_EN Bit Mirroring is enabled 1 BYTMIRR Byte Mirroring 3 1 read-write BYTEMIR_DIS Byte Mirroring is disabled 0 BYTEMIR_EN Byte Mirroring is enabled 1 W16SWP Word16 Swap 4 1 read-write W16SP_DIS Word16 Swap disabled 0 W16SP_EN Word16 Swap enabled 1 RevID Revision ID 28 4 read-only IPDATA 0x00000004 32 Input Data Word 0x00000000 VALUE Data Input 0 32 write-only 0x00000000 0xFFFFFFFF RESULT 0x00000008 32 CRC Result 0x00000000 VALUE CRC Residue 0 32 read-write 0x00000000 0xFFFFFFFF POLY 0x0000000C 32 Programmable CRC Polynomial 0x04C11DB7 VALUE CRC Reduction Polynomial 0 32 read-write 0x00000000 0xFFFFFFFF 8 1 IPBITS[%s] 0x00000010 8 Input Data Bits 0x00000000 DATA_BITS Input Data Bits 0 8 write-only 0x00000000 0x000000FF IPBYTE 0x00000010 8 Input Data Byte IPBITS0 0x00000000 DATA_BYTE Input Data Byte 0 8 write-only 0x00000000 0x000000FF RNG0 Random Number Generator 0x40040400 RNG0 0 0x00000100 registers RNG0_EVT 44 Event CTL 0x00000000 16 RNG Control Register 0x00000000 EN RNG Enable 0 1 read-write DISABLE Disable the RNG 0 ENABLE Enable the RNG 1 SINGLE Generate a Single Number 3 1 read-write WORD Buffer Word 0 SINGLE Single Byte 1 LEN 0x00000004 16 RNG Sample Length Register 0x00003400 RELOAD Reload Value for the Sample Counter 0 12 read-write 0x00000000 0x00000FFF PRESCALE Prescaler for the Sample Counter 12 4 read-write 0x00000000 0x0000000F STAT 0x00000008 16 RNG Status Register 0x00000000 RNRDY Random Number Ready 0 1 read-write STUCK Sampled Data Stuck High or Low 1 1 read-write 0x00000000 0x00000001 DATA 0x0000000C 32 RNG Data Register 0x00000000 VALUE Value of the CRC Accumulator 0 8 read-only BUFF Buffer for RNG Data 8 24 read-only OSCCNT 0x00000010 32 Oscillator Count 0x00000000 VALUE Oscillator Count 0 28 read-only 4 1 OSCDIFF[%s] 0x00000014 8 Oscillator Difference 0x00000000 DELTA Oscillator Count Difference 0 8 read-only CRYPT0 Register Map for the Crypto Block 0x40044000 CRYPT0 0 0x00000200 registers CRYPT_EVT 38 Event CFG 0x00000000 32 Configuration Register 0x10000000 BLKEN Enable Bit for Crypto Block 0 1 read-write Enable Enable Crypto Block 0 Disable Disable Crypto Block 1 ENCR Encrypt or Decrypt 1 1 read-write INDMAEN Enable DMA Channel Request for Input Buffer 2 1 read-write DMA_DISABLE_INBUF Disable DMA Requesting for Input Buffer 0 DMA_ENABLE_INBUF Enable DMA Requesting for Input Buffer 1 OUTDMAEN Enable DMA Channel Request for Output Buffer 3 1 read-write DMA_DISABLE_OUTBUF Disable DMA Requesting for Output Buffer 0 DMA_ENABLE_OUTBUF Enable DMA Requesting for Output Buffer 1 INFLUSH Input Buffer Flush 4 1 write-only 0x00000000 0x00000001 OUTFLUSH Output Buffer Flush 5 1 write-only 0x00000000 0x00000001 AES_BYTESWAP Byte Swap 32 Bit AES Input Data 6 1 read-write 0x00000000 0x00000001 AESKEYLEN Select Key Length for AES Cipher 8 2 read-write AESKEYLEN128 Uses 128-bit long key 0 AESKEYLEN256 Uses 256-bit long key 2 ECBEN Enable ECB Mode Operation 16 1 read-write 0x00000000 0x00000001 CTREN Enable CTR Mode Operation 17 1 read-write 0x00000000 0x00000001 CBCEN Enable CBC Mode Operation 18 1 read-write 0x00000000 0x00000001 CCMEN Enable CCM/CCM* Mode Operation 19 1 read-write 0x00000000 0x00000001 CMACEN Enable CMAC Mode Operation 20 1 read-write 0x00000000 0x00000001 SHA256EN Enable SHA-256 Operation 25 1 read-write 0x00000000 0x00000001 SHAINIT Restarts SHA Computation 26 1 read-write 0x00000000 0x00000001 RevID Rev ID for Crypto 28 4 read-only DATALEN 0x00000004 32 Payload Data Length 0x00000000 VALUE Length of Payload Data 0 20 read-write 0x00000000 0x000FFFFF PREFIXLEN 0x00000008 32 Authentication Data Length 0x00000000 VALUE Length of Associated Data 0 16 read-write 0x00000000 0x0000FFFF INTEN 0x0000000C 32 Interrupt Enable Register 0x00000000 INRDYEN Enable Input Ready Interrupt 0 1 read-write 0x00000000 0x00000001 OUTRDYEN Enables the Output Ready Interrupt 1 1 read-write 0x00000000 0x00000001 INOVREN Enable Input Overflow Interrupt 2 1 read-write 0x00000000 0x00000001 SHADONEN Enable SHA_Done Interrupt 5 1 read-write 0x00000000 0x00000001 STAT 0x00000010 32 Status Register 0x00000001 INRDY Input Buffer Status 0 1 read-only OUTRDY Output Data Ready 1 1 read-only INOVR Overflow in the Input Buffer 2 1 read-write 0x00000000 0x00000001 SHADONE SHA Computation Complete 5 1 read-write 0x00000000 0x00000001 SHABUSY SHA Busy. in Computation 6 1 read-only INWORDS Number of Words in the Input Buffer 7 3 read-only OUTWORDS Number of Words in the Output Buffer 10 3 read-only INBUF 0x00000014 32 Input Buffer 0x00000000 VALUE Input Buffer 0 32 write-only 0x00000000 0xFFFFFFFF OUTBUF 0x00000018 32 Output Buffer 0x00000000 VALUE Output Buffer 0 32 read-only NONCE0 0x0000001C 32 Nonce Bits [31:0] 0x00000000 VALUE Word 0: Nonce Bits [31:0] 0 32 read-write 0x00000000 0xFFFFFFFF NONCE1 0x00000020 32 Nonce Bits [63:32] 0x00000000 VALUE Word 1: Nonce Bits [63:32] 0 32 read-write 0x00000000 0xFFFFFFFF NONCE2 0x00000024 32 Nonce Bits [95:64] 0x00000000 VALUE Word 2: Nonce Bits [95:64] 0 32 read-write 0x00000000 0xFFFFFFFF NONCE3 0x00000028 32 Nonce Bits [127:96] 0x00000000 VALUE Word 3: Nonce Bits [127:96] 0 32 read-write 0x00000000 0xFFFFFFFF AESKEY0 0x0000002C 32 AES Key Bits [31:0] 0x00000000 VALUE Key: Bytes [3:0] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY1 0x00000030 32 AES Key Bits [63:32] 0x00000000 VALUE Key: Bytes [7:4] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY2 0x00000034 32 AES Key Bits [95:64] 0x00000000 VALUE Key: Bytes [11:8] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY3 0x00000038 32 AES Key Bits [127:96] 0x00000000 VALUE Key: Bytes [15:12] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY4 0x0000003C 32 AES Key Bits [159:128] 0x00000000 VALUE Key: Bytes [19:16] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY5 0x00000040 32 AES Key Bits [191:160] 0x00000000 VALUE Key: Bytes [23:20] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY6 0x00000044 32 AES Key Bits [223:192] 0x00000000 VALUE Key: Bytes [27:24] 0 32 write-only 0x00000000 0xFFFFFFFF AESKEY7 0x00000048 32 AES Key Bits [255:224] 0x00000000 VALUE Key: Bytes [31:28] 0 32 write-only 0x00000000 0xFFFFFFFF CNTRINIT 0x0000004C 32 Counter Initialization Vector 0x00000000 VALUE Counter Initialization Value 0 20 read-write 0x00000000 0x000FFFFF SHAH0 0x00000050 32 SHA Bits [31:0] 0x6A09E667 SHAHASH0 Word 0: SHA Hash 0 32 read-only SHAH1 0x00000054 32 SHA Bits [63:32] 0xBB67AE85 SHAHASH1 Word 1: SHA Hash 0 32 read-only SHAH2 0x00000058 32 SHA Bits [95:64] 0x3C6EF372 SHAHASH2 Word 2: SHA Hash 0 32 read-only SHAH3 0x0000005C 32 SHA Bits [127:96] 0xA54FF53A SHAHASH3 Word 3: SHA Hash 0 32 read-only SHAH4 0x00000060 32 SHA Bits [159:128] 0x510E527F SHAHASH4 Word 4: SHA Hash 0 32 read-only SHAH5 0x00000064 32 SHA Bits [191:160] 0x9B05688C SHAHASH5 Word 5: SHA Hash 0 32 read-only SHAH6 0x00000068 32 SHA Bits [223:192] 0x1F83D9AB SHAHASH6 Word 6: SHA Hash 0 32 read-only SHAH7 0x0000006C 32 SHA Bits [255:224] 0x5BE0CD19 SHAHASH7 Word 7: SHA Hash 0 32 read-only SHA_LAST_WORD 0x00000070 32 SHA Last Word and Valid Bits Information 0x00000000 O_Last_Word Last SHA Input Word 0 1 read-write 0x00000000 0x00000001 O_Bits_Valid Bits Valid in SHA Last Word Input 1 5 read-write 0x00000000 0x0000001F CCM_NUM_VALID_BYTES 0x00000074 32 NUM_VALID_BYTES 0x00000000 NUM_VALID_BYTES Number of Valid Bytes in CCM Last Data 0 4 read-write 0x00000000 0x0000000F PMG0 Power Management 0x4004C000 PMG0 0 0x00004000 registers PMG0_VREG_OVR 6 Voltage Regulator (VREG) Overvoltage PMG0_BATT_RANGE 7 Battery Voltage (VBAT) Out of Range IEN 0x00000000 32 Power Supply Monitor Interrupt Enable 0x00000000 VBAT Enable Interrupt for VBAT 0 1 read-write 0x00000000 0x00000001 VREGUNDR Enable Interrupt When VREG Undervoltage: Below 1V 1 1 read-write 0x00000000 0x00000001 VREGOVR Enable Interrupt When VREG Overvoltage: Above 1.32V 2 1 read-write 0x00000000 0x00000001 RANGEBAT Battery Monitor Range 8 2 read-write region1 Configure to generate interrupt if VBAT > 2.75 V 0 region2 Configure to generate interrupt if VBAT between 2.75 V - 1.6 V 1 region3 Configure to generate interrupt if VBAT between 2.3 V - 1.6 V 2 NA N/A 3 IENBAT Interrupt Enable for VBAT Range 10 1 read-write 0x00000000 0x00000001 PSM_STAT 0x00000004 32 Power Supply Monitor Status 0x00000000 VBATUNDR Status Bit Indicating an Alarm That Battery is Below 1.8V 0 1 read-write 0x00000000 0x00000001 VREGUNDR Status Bit for Alarm Indicating VREG is Below 1V 1 1 read-write 0x00000000 0x00000001 VREGOVR Status Bit for Alarm Indicating Overvoltage for VREG 2 1 read-write 0x00000000 0x00000001 WICENACK WIC Enable Acknowledge from Cortex 7 1 read-only RANGE1 VBAT Range1 (> 2.75v) 8 1 read-write RANGE2 VBAT Range2 (2.75v - 2.3v) 9 1 read-write RANGE3 VBAT Range3 (2.3v - 1.6v) 10 1 read-write RORANGE1 VBAT Range1 (> 2.75v) 13 1 read-only batstat1 VBAT not in the range specified 0 batstat0 VBAT in the range specified 1 RORANGE2 VBAT Range2 (2.75v - 2.3v) 14 1 read-only RORANGE3 VBAT Range3 (2.3v - 1.6v) 15 1 read-only PWRMOD 0x00000008 32 Power Mode Register 0x00000000 MODE Power Mode Bits 0 2 read-write FLEXI Flexi Mode 0 HIBERNATE Hibernate Mode 2 SHUTDOWN Shutdown Mode 3 MONVBATN Monitor VBAT During Hibernate Mode. Monitors VBAT by Default 3 1 read-write VBAT_MONEN VBAT monitor enabled in PMG block. 0 VBAT_MONDIS VBAT monitor disabled in PMG block. 1 PWRKEY 0x0000000C 32 Key Protection for PMG_PWRMOD and PMG_SRAMRET 0x00000000 VALUE Power Control Key Register 0 16 write-only 0x00000000 0x0000FFFF SHDN_STAT 0x00000010 32 Shutdown Status Register 0x00000000 EXTINT0 Wakeup by Interrupt from External Interrupt 0 0 1 read-only EXTINT1 Wakeup by Interrupt from External Interrupt 1 1 1 read-only EXTINT2 Wakeup by Interrupt from External Interrupt 2 2 1 read-only RTC Wakeup by Interrupt from RTC 3 1 read-only SRAMRET 0x00000014 32 Control for Retention SRAM in Hibernate Mode 0x00000000 BNK1EN Enable Retention Bank 1 (8kB) 0 1 read-write 0x00000000 0x00000001 BNK2EN Enable Retention Bank 2 (16kB) 1 1 read-write 0x00000000 0x00000001 RST_STAT 0x00000040 32 Reset Status 0x00000000 POR Power-on-Reset 0 1 read-write 0x00000000 0x00000001 EXTRST External Reset 1 1 read-write 0x00000000 0x00000001 WDRST Watchdog Time-out Reset 2 1 read-write 0x00000000 0x00000001 SWRST Software Reset 3 1 read-write 0x00000000 0x00000001 PORSRC Power-on-Reset Source 4 2 read-only FAILSAFE_HV POR triggered because VBAT drops below Fail Safe 0 RST_VBAT POR trigger because VBAT supply (VBAT < 1.7 V) 1 RST_VREG POR triggered because VDD supply (VDD < 1.08 V) 2 FAILSAFE_LV POR triggered because VREG drops below Fail Safe 3 CTL1 0x00000044 32 HP Buck Control 0x00A00000 HPBUCKEN Enable HP Buck 0 1 read-write 0x00000000 0x00000001 XINT0 External interrupt configuration 0x4004C080 XINT0 0 0x00004000 registers XINT_EVT0 1 External Wakeup Interrupt n XINT_EVT1 2 External Wakeup Interrupt n XINT_EVT2 3 External Wakeup Interrupt n XINT_EVT3 4 External Wakeup Interrupt n CFG0 0x00000000 32 External Interrupt Configuration 0x00200000 IRQ0MDE External Interrupt 0 Mode Registers 0 3 read-write IRQ0EN External Interrupt 0 Enable Bit 3 1 read-write IRQ1MDE External Interrupt 1 Mode Registers 4 3 read-write IRQ1EN External Interrupt 1 Enable Bit 7 1 read-write IRQ2MDE External Interrupt 2 Mode Registers 8 3 read-write IRQ2EN External Interrupt 2 Enable Bit 11 1 read-write IRQ3MDE External Interrupt 3 Mode Registers 12 3 read-write IRQ3EN External Interrupt 3 Enable Bit 15 1 read-write UART_RX_EN External Interrupt Enable Bit 20 1 read-write UART_RX_MDE External Interrupt Using UART_RX Wakeup Mode Registers 21 3 read-write EXT_STAT 0x00000004 32 External Wakeup Interrupt Status 0x00000000 STAT_EXTINT0 Interrupt Status Bit for External Interrupt 0 0 1 read-only STAT_EXTINT1 Interrupt Status Bit for External Interrupt 1 1 1 read-only STAT_EXTINT2 Interrupt Status Bit for External Interrupt 2 2 1 read-only STAT_EXTINT3 Interrupt Status Bit for External Interrupt 3 3 1 read-only STAT_UART_RXWKUP Interrupt Status Bit for UART RX Wakeup Interrupt 5 1 read-only CLR 0x00000010 32 External Interrupt Clear 0x00000000 IRQ0 External Interrupt 0 0 1 read-write 0x00000000 0x00000001 IRQ1 External Interrupt 1 1 1 read-write 0x00000000 0x00000001 IRQ2 External Interrupt 2 2 1 read-write 0x00000000 0x00000001 IRQ3 External Interrupt 3 3 1 read-write 0x00000000 0x00000001 UART_RX_CLR External Interrupt Clear for UART_RX Wakeup Interrupt 5 1 read-write 0x00000000 0x00000001 NMICLR 0x00000014 32 Non-Maskable Interrupt Clear 0x00000000 CLR NMI Clear 0 1 read-write 0x00000000 0x00000001 CLKG0_OSC Clocking 0x4004C100 CLKG0_OSC 0 0x00004000 registers CLKG_XTAL_OSC_EVT 41 Crystal Oscillator Event CLKG_PLL_EVT 43 PLL Event KEY 0x0000000C 32 Key Protection for CLKG_OSC_CTL 0x00000000 VALUE Oscillator K 0 16 write-only 0x00000000 0x0000FFFF CTL 0x00000010 32 Oscillator Control 0x00000002 LFCLKMUX 32kHz Clock Select Mux 0 1 read-write HFOSCEN High Frequency Internal Oscillator Enable 1 1 read-write LFXTALEN Low Frequency Crystal Oscillator Enable 2 1 read-write HFXTALEN High Frequency Crystal Oscillator Enable 3 1 read-write LFXTAL_BYPASS Low Frequency Crystal Oscillator Bypass 4 1 read-write LFXTAL_MON_EN LFXTAL Clock Monitor and Clock Fail Interrupt Enable 5 1 read-write LFOSCOK Status of LFOSC Oscillator 8 1 read-only HFOSCOK Status of HFOSC 9 1 read-only LFXTALOK Status of LFXTAL Oscillator 10 1 read-only HFXTALOK Status of HFXTAL Oscillator 11 1 read-only LFXTAL_MON_FAIL_STAT LFXTAL Not Stable 31 1 read-write LFXTAL_RUNNING LFXTAL is running fine 0 LFXTAL_NOTRUNNING LFXTAL is not running 1 PMG0_TST Power Management 0x4004C200 PMG0_TST 0 0x00004000 registers SRAM_CTL 0x00000060 32 Control for SRAM Parity and Instruction SRAM 0x80000000 BNK0EN Enable Initialization of SRAM Bank 0 0 1 read-write 0x00000000 0x00000001 BNK1EN Enable Initialization of SRAM Bank 1 1 1 read-write 0x00000000 0x00000001 BNK2EN Enable Initialization of SRAM Bank 2 2 1 read-write 0x00000000 0x00000001 BNK3EN Enable Initialization of SRAM Bank 3 3 1 read-write 0x00000000 0x00000001 BNK4EN Enable Initialization of SRAM Bank 4 4 1 read-write 0x00000000 0x00000001 BNK5EN Enable Initialization of SRAM Bank 5 5 1 read-write 0x00000000 0x00000001 STARTINIT Write 1 to Trigger Initialization 13 1 read-write 0x00000000 0x00000001 AUTOINIT Automatic Initialization on Wakeup from Hibernate Mode 14 1 read-write 0x00000000 0x00000001 ABTINIT Abort Current Initialization. Self-cleared 15 1 read-write 0x00000000 0x00000001 PENBNK0 Enable Parity Check SRAM Bank 0 16 1 read-write 0x00000000 0x00000001 PENBNK1 Enable Parity Check SRAM Bank 1 17 1 read-write 0x00000000 0x00000001 PENBNK2 Enable Parity Check SRAM Bank 2 18 1 read-write 0x00000000 0x00000001 PENBNK3 Enable Parity Check SRAM Bank 3 19 1 read-write 0x00000000 0x00000001 PENBNK4 Enable Parity Check SRAM Bank 4 20 1 read-write 0x00000000 0x00000001 PENBNK5 Enable Parity Check SRAM Bank 5 21 1 read-write 0x00000000 0x00000001 INSTREN Enables Instruction SRAM 31 1 read-write 0x00000000 0x00000001 SRAM_INITSTAT 0x00000064 32 Initialization Status Register 0x00000000 BNK0 Initialization Done of SRAM Bank 0 0 1 read-only BNK1 Initialization Done of SRAM Bank 1 1 1 read-only BNK2 Initialization Done of SRAM Bank 2 2 1 read-only BNK3 Initialization Done of SRAM Bank 3 3 1 read-only BNK4 Initialization Done of SRAM Bank 4 4 1 read-only BNK5 Initialization Done of SRAM Bank 5 5 1 read-only CLR_LATCH_GPIOS 0x00000068 16 Clear GPIO After Shutdown Mode 0x00000000 VALUE Clear GPIOs Latches 0 16 write-only 0x00000000 0x0000FFFF SCRPAD_IMG 0x0000006C 32 Scratch Pad Image 0x00000000 DATA Scratch Image 0 32 read-write 0x00000000 0xFFFFFFFF SCRPAD_3V_RD 0x00000070 32 Scratch Pad Saved in Battery Domain 0x00000000 DATA Reading the Scratch Pad Stored in Shutdown Mode 0 32 read-only CLKG0_CLK Clocking 0x4004C300 CLKG0_CLK 0 0x00004000 registers CTL0 0x00000000 32 Miscellaneous Clock Settings 0x00000078 CLKMUX Clock Mux Select 0 2 read-write CLKOUT GPIO Clock Out Select (for Debug) 3 4 read-write RCLKMUX Flash Reference Clock and HP Buck Source Mux 8 2 read-write SPLLIPSEL SPLL Source Select Mux 11 1 read-write LFXTALIE Low Frequency Crystal Interrupt Enable 14 1 read-write HFXTALIE High Frequency Crystal Interrupt Enable 15 1 read-write CTL1 0x00000004 32 Clock Dividers 0x00100404 HCLKDIVCNT HCLK Divide Count 0 6 read-write 0x00000000 0x0000003F PCLKDIVCNT PCLK Divide Count 8 6 read-write 0x00000000 0x0000003F ACLKDIVCNT ACLK Divide Count 16 8 read-write 0x00000000 0x000000FF CTL3 0x0000000C 32 System PLL 0x0000691A SPLLNSEL System PLL N Multiplier 0 5 read-write 0x00000000 0x0000001F SPLLDIV2 System PLL Division by 2 8 1 read-write SPLLEN System PLL Enable 9 1 read-write SPLLIE System PLL Interrupt Enable 10 1 read-write SPLLMSEL System PLL M Divider 11 4 read-write 0x00000000 0x0000000F SPLLMUL2 System PLL Multiply by 2 16 1 read-write CTL5 0x00000014 32 User Clock Gating Control 0x0000001F GPTCLK0OFF Timer 0 User Control 0 1 read-write GPTCLK1OFF Timer 1 User Control 1 1 read-write GPTCLK2OFF Timer 2 User Control 2 1 read-write UCLKI2COFF I2C Clock User Control 3 1 read-write GPIOCLKOFF GPIO Clock Control 4 1 read-write PERCLKOFF Disables All Clocks Connected to All Peripherals 5 1 read-write PERIPH_CLK_ACT Clocks to all peripherals are active 0 PERIPH_CLK_OFF Clocks to all peripherals are gated off 1 STAT0 0x00000018 32 Clocking Status 0x00000000 SPLL System PLL Status 0 1 read-only SPLLLK System PLL Lock 1 1 read-write SPLLUNLK System PLL Unlock 2 1 read-write LFXTAL LF Crystal Status 8 1 read-only LFXTALOK LF Crystal Stable 9 1 read-write LFXTALNOK LF Crystal Not Stable 10 1 read-write HFXTAL HF Crystal Status 12 1 read-only HFXTALOK HF Crystal Stable 13 1 read-write HFXTALNOK HF Crystal Not Stable 14 1 read-write BUSM0 Bus matrix 0x4004C800 BUSM0 0 0x00004000 registers ARBIT0 0x00000000 32 Arbitration Priority Configuration for FLASH and SRAM0 0x00240024 FLSH_DCODE Flash priority for DCODE 0 2 read-write 0x00000000 0x00000003 FLSH_SBUS Flash priority for SBUS 2 2 read-write 0x00000000 0x00000003 FLSH_DMA0 Flash priority for DMA0 4 2 read-write 0x00000000 0x00000003 SRAM0_DCODE SRAM0 priority for Dcode 16 2 read-write 0x00000000 0x00000003 SRAM0_SBUS SRAM0 priority for SBUS 18 2 read-write 0x00000000 0x00000003 SRAM0_DMA0 SRAM0 priority for DMA0 20 2 read-write 0x00000000 0x00000003 ARBIT1 0x00000004 32 Arbitration Priority Configuration for SRAM1 and SIP 0x00240024 SRAM1_DCODE SRAM1 priority for Dcode 0 2 read-write 0x00000000 0x00000003 SRAM1_SBUS SRAM1 priority for SBUS 2 2 read-write 0x00000000 0x00000003 SRAM1_DMA0 SRAM1 priority for DMA0 4 2 read-write 0x00000000 0x00000003 SIP_DCODE SIP priority for DCODE 16 2 read-write 0x00000000 0x00000003 SIP_SBUS SIP priority for SBUS 18 2 read-write 0x00000000 0x00000003 SIP_DMA0 SIP priority for DMA0 20 2 read-write 0x00000000 0x00000003 ARBIT2 0x00000008 32 Arbitration Priority Configuration for APB32 and APB16 0x00240024 APB32_DCODE APB32 priority for DCODE 0 2 read-write 0x00000000 0x00000003 APB32_SBUS APB32 priority for SBUS 2 2 read-write 0x00000000 0x00000003 APB32_DMA0 APB32 priority for DMA0 4 2 read-write 0x00000000 0x00000003 APB16_DCODE APB16 priority for DCODE 16 2 read-write 0x00000000 0x00000003 APB16_SBUS APB16 priority for SBUS 18 2 read-write 0x00000000 0x00000003 APB16_DMA0 APB16 priority for DMA0 20 2 read-write 0x00000000 0x00000003 ARBIT3 0x0000000C 32 Arbitration Priority Configuration for APB16 priority for core and for DMA1 0x00010002 APB16_CORE APB16 priority for CORE 0 1 read-write 0x00000000 0x00000001 APB16_DMA1 APB16 priority for DMA1 1 1 read-write 0x00000000 0x00000001 APB16_4DMA_CORE APB16 for dma priority for CORE 16 1 read-write 0x00000000 0x00000001 APB16_4DMA_DMA1 APB16 for dma priority for DMA1 17 1 read-write 0x00000000 0x00000001 NVIC0 Cortex-M3 Interrupt Controller 0xE000E000 NVIC0 0 0x00001000 registers INTNUM 0x00000004 32 Interrupt Control Type 0x00000000 VALUE Interrupt Control Type 0 32 read-write 0x00000000 0xFFFFFFFF STKSTA 0x00000010 32 Systick Control and Status 0x00000000 VALUE Systick Control and Status 0 32 read-write 0x00000000 0xFFFFFFFF STKLD 0x00000014 32 Systick Reload Value 0x00000000 VALUE Systick Reload Value 0 32 read-write 0x00000000 0xFFFFFFFF STKVAL 0x00000018 32 Systick Current Value 0x00000000 VALUE Systick Current Value 0 32 read-write 0x00000000 0xFFFFFFFF STKCAL 0x0000001C 32 Systick Calibration Value 0x00000000 VALUE Systick Calibration Value 0 32 read-write 0x00000000 0xFFFFFFFF INTSETE0 0x00000100 32 IRQ0..31 Set_Enable 0x00000000 VALUE IRQ0..31 Set_Enable 0 32 read-write 0x00000000 0xFFFFFFFF INTSETE1 0x00000104 32 IRQ32..63 Set_Enable 0x00000000 VALUE IRQ32..63 Set_Enable 0 32 read-write 0x00000000 0xFFFFFFFF INTCLRE0 0x00000180 32 IRQ0..31 Clear_Enable 0x00000000 VALUE IRQ0..31 Clear_Enable 0 32 read-write 0x00000000 0xFFFFFFFF INTCLRE1 0x00000184 32 IRQ32..63 Clear_Enable 0x00000000 VALUE IRQ32..63 Clear_Enable 0 32 read-write 0x00000000 0xFFFFFFFF INTSETP0 0x00000200 32 IRQ0..31 Set_Pending 0x00000000 VALUE IRQ0..31 Set_Pending 0 32 read-write 0x00000000 0xFFFFFFFF INTSETP1 0x00000204 32 IRQ32..63 Set_Pending 0x00000000 VALUE IRQ32..63 Set_Pending 0 32 read-write 0x00000000 0xFFFFFFFF INTCLRP0 0x00000280 32 IRQ0..31 Clear_Pending 0x00000000 VALUE IRQ0..31 Clear_Pending 0 32 read-write 0x00000000 0xFFFFFFFF INTCLRP1 0x00000284 32 IRQ32..63 Clear_Pending 0x00000000 VALUE IRQ32..63 Clear_Pending 0 32 read-write 0x00000000 0xFFFFFFFF INTACT0 0x00000300 32 IRQ0..31 Active Bit 0x00000000 VALUE IRQ0..31 Active Bit 0 32 read-write 0x00000000 0xFFFFFFFF INTACT1 0x00000304 32 IRQ32..63 Active Bit 0x00000000 VALUE IRQ32..63 Active Bit 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI0 0x00000400 32 IRQ0..3 Priority 0x00000000 VALUE IRQ0..3 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI1 0x00000404 32 IRQ4..7 Priority 0x00000000 VALUE IRQ4..7 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI2 0x00000408 32 IRQ8..11 Priority 0x00000000 VALUE IRQ8..11 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI3 0x0000040C 32 IRQ12..15 Priority 0x00000000 VALUE IRQ12..15 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI4 0x00000410 32 IRQ16..19 Priority 0x00000000 VALUE IRQ16..19 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI5 0x00000414 32 IRQ20..23 Priority 0x00000000 VALUE IRQ20..23 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI6 0x00000418 32 IRQ24..27 Priority 0x00000000 VALUE IRQ24..27 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI7 0x0000041C 32 IRQ28..31 Priority 0x00000000 VALUE IRQ28..31 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI8 0x00000420 32 IRQ32..35 Priority 0x00000000 VALUE IRQ32..35 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI9 0x00000424 32 IRQ36..39 Priority 0x00000000 VALUE IRQ36..39 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTPRI10 0x00000428 32 IRQ40..43 Priority 0x00000000 VALUE IRQ40..43 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTCPID 0x00000D00 32 CPUID Base 0x00000000 VALUE CPUID Base 0 32 read-write 0x00000000 0xFFFFFFFF INTSTA 0x00000D04 32 Interrupt Control State 0x00000000 VALUE Interrupt Control State 0 32 read-write 0x00000000 0xFFFFFFFF INTVEC 0x00000D08 32 Vector Table Offset 0x00000000 VALUE Vector Table Offset 0 32 read-write 0x00000000 0xFFFFFFFF INTAIRC 0x00000D0C 32 Application Interrupt/Reset Control 0x00000000 VALUE Application Interrupt/Reset Control 0 32 read-write 0x00000000 0xFFFFFFFF INTCON0 0x00000D10 16 System Control 0x00000000 SLEEPONEXIT Sleeps the core on exit from an ISR 1 1 read-write SLEEPDEEP deep sleep flag for HIBERNATE mode 2 1 read-write INTCON1 0x00000D14 32 Configuration Control 0x00000000 VALUE Configuration Control 0 32 read-write 0x00000000 0xFFFFFFFF INTSHPRIO0 0x00000D18 32 System Handlers 4-7 Priority 0x00000000 VALUE System Handlers 4-7 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTSHPRIO1 0x00000D1C 32 System Handlers 8-11 Priority 0x00000000 VALUE System Handlers 8-11 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTSHPRIO3 0x00000D20 32 System Handlers 12-15 Priority 0x00000000 VALUE System Handlers 12-15 Priority 0 32 read-write 0x00000000 0xFFFFFFFF INTSHCSR 0x00000D24 32 System Handler Control and State 0x00000000 VALUE System Handler Control and State 0 32 read-write 0x00000000 0xFFFFFFFF INTCFSR 0x00000D28 32 Configurable Fault Status 0x00000000 VALUE Configurable Fault Status 0 32 read-write 0x00000000 0xFFFFFFFF INTHFSR 0x00000D2C 32 Hard Fault Status 0x00000000 VALUE Hard Fault Status 0 32 read-write 0x00000000 0xFFFFFFFF INTDFSR 0x00000D30 32 Debug Fault Status 0x00000000 VALUE Debug Fault Status 0 32 read-write 0x00000000 0xFFFFFFFF INTMMAR 0x00000D34 32 Mem Manage Address 0x00000000 VALUE Mem Manage Address 0 32 read-write 0x00000000 0xFFFFFFFF INTBFAR 0x00000D38 32 Bus Fault Address 0x00000000 VALUE Bus Fault Address 0 32 read-write 0x00000000 0xFFFFFFFF INTAFSR 0x00000D3C 32 Auxiliary Fault Status 0x00000000 VALUE Auxiliary Fault Status 0 32 read-write 0x00000000 0xFFFFFFFF INTPFR0 0x00000D40 32 Processor Feature Register 0 0x00000000 VALUE Processor Feature Register 0 0 32 read-write 0x00000000 0xFFFFFFFF INTPFR1 0x00000D44 32 Processor Feature Register 1 0x00000000 VALUE Processor Feature Register 1 0 32 read-write 0x00000000 0xFFFFFFFF INTDFR0 0x00000D48 32 Debug Feature Register 0 0x00000000 VALUE Debug Feature Register 0 0 32 read-write 0x00000000 0xFFFFFFFF INTAFR0 0x00000D4C 32 Auxiliary Feature Register 0 0x00000000 VALUE Auxiliary Feature Register 0 0 32 read-write 0x00000000 0xFFFFFFFF INTMMFR0 0x00000D50 32 Memory Model Feature Register 0 0x00000000 VALUE Memory Model Feature Register 0 0 32 read-write 0x00000000 0xFFFFFFFF INTMMFR1 0x00000D54 32 Memory Model Feature Register 1 0x00000000 VALUE Memory Model Feature Register 1 0 32 read-write 0x00000000 0xFFFFFFFF INTMMFR2 0x00000D58 32 Memory Model Feature Register 2 0x00000000 VALUE Memory Model Feature Register 2 0 32 read-write 0x00000000 0xFFFFFFFF INTMMFR3 0x00000D5C 32 Memory Model Feature Register 3 0x00000000 VALUE Memory Model Feature Register 3 0 32 read-write 0x00000000 0xFFFFFFFF INTISAR0 0x00000D60 32 ISA Feature Register 0 0x00000000 VALUE ISA Feature Register 0 0 32 read-write 0x00000000 0xFFFFFFFF INTISAR1 0x00000D64 32 ISA Feature Register 1 0x00000000 VALUE ISA Feature Register 1 0 32 read-write 0x00000000 0xFFFFFFFF INTISAR2 0x00000D68 32 ISA Feature Register 2 0x00000000 VALUE ISA Feature Register 2 0 32 read-write 0x00000000 0xFFFFFFFF INTISAR3 0x00000D6C 32 ISA Feature Register 3 0x00000000 VALUE ISA Feature Register 3 0 32 read-write 0x00000000 0xFFFFFFFF INTISAR4 0x00000D70 32 ISA Feature Register 4 0x00000000 VALUE ISA Feature Register 4 0 32 read-write 0x00000000 0xFFFFFFFF INTTRGI 0x00000F00 32 Software Trigger Interrupt Register 0x00000000 VALUE Software Trigger Interrupt Register 0 32 read-write 0x00000000 0xFFFFFFFF INTPID4 0x00000FD0 32 Peripheral Identification Register 4 0x00000000 VALUE Peripheral Identification Register 4 0 32 read-write 0x00000000 0xFFFFFFFF INTPID5 0x00000FD4 32 Peripheral Identification Register 5 0x00000000 VALUE Peripheral Identification Register 5 0 32 read-write 0x00000000 0xFFFFFFFF INTPID6 0x00000FD8 32 Peripheral Identification Register 6 0x00000000 VALUE Peripheral Identification Register 6 0 32 read-write 0x00000000 0xFFFFFFFF INTPID7 0x00000FDC 32 Peripheral Identification Register 7 0x00000000 VALUE Peripheral Identification Register 7 0 32 read-write 0x00000000 0xFFFFFFFF INTPID0 0x00000FE0 32 Peripheral Identification Bits7:0 0x00000000 VALUE Peripheral Identification Bits7:0 0 32 read-write 0x00000000 0xFFFFFFFF INTPID1 0x00000FE4 32 Peripheral Identification Bits15:8 0x00000000 VALUE Peripheral Identification Bits15:8 0 32 read-write 0x00000000 0xFFFFFFFF INTPID2 0x00000FE8 32 Peripheral Identification Bits16:23 0x00000000 VALUE Peripheral Identification Bits16:23 0 32 read-write 0x00000000 0xFFFFFFFF INTPID3 0x00000FEC 32 Peripheral Identification Bits24:31 0x00000000 VALUE Peripheral Identification Bits24:31 0 32 read-write 0x00000000 0xFFFFFFFF INTCID0 0x00000FF0 32 Component Identification Bits7:0 0x00000000 VALUE Component Identification Bits7:0 0 32 read-write 0x00000000 0xFFFFFFFF INTCID1 0x00000FF4 32 Component Identification Bits15:8 0x00000000 VALUE Component Identification Bits15:8 0 32 read-write 0x00000000 0xFFFFFFFF INTCID2 0x00000FF8 32 Component Identification Bits16:23 0x00000000 VALUE Component Identification Bits16:23 0 32 read-write 0x00000000 0xFFFFFFFF INTCID3 0x00000FFC 32 Component Identification Bits24:31 0x00000000 VALUE Component Identification Bits24:31 0 32 read-write 0x00000000 0xFFFFFFFF