SKEAZN642 1.6 SKEAZN642 Freescale Microcontroller 8 32 FTMRH_FlashConfig Flash configuration field NV_ 0x400 0 0x10 registers BACKKEY0 Backdoor Comparison Key 0 0 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1 0x1 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2 0x2 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY3 Backdoor Comparison Key 3 0x3 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4 0x4 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5 0x5 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6 0x6 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7 0x7 8 read-only 0xFF 0xFF KEY Backdoor Comparison Key. 0 8 read-only EEPROT Non-volatile E-Flash Protection Register 0xC 8 read-only 0x87 0xFF DPS no description available 0 3 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only DPOPEN no description available 7 1 read-only FPROT Non-volatile P-Flash Protection Register 0xD 8 read-only 0xFF 0xFF FPLS no description available 0 2 read-only FPLDIS no description available 2 1 read-only FPHS no description available 3 2 read-only FPHDIS no description available 5 1 read-only RESERVED no description available 6 1 read-only FPOPEN no description available 7 1 read-only FSEC Non-volatile Flash Security Register 0xE 8 read-only 0xFF 0xFF SEC Flash Security 0 2 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only KEYEN Backdoor Key Security Enable 6 2 read-only FOPT Non-volatile Flash Option Register 0xF 8 read-only 0xFF 0xFF RESERVED no description available 0 1 read-only RESERVED no description available 1 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only FTMRH Flash Memory FTMRH_ 0x40020000 0 0xD registers INT_FTMRH 5 FCLKDIV Flash Clock Divider Register 0 8 read-write 0 0xFF FDIV Clock Divider Bits 0 6 read-write FDIVLCK Clock Divider Locked 6 1 read-write 0 FDIV field is open for writing. #0 1 FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode. #1 FDIVLD Clock Divider Loaded 7 1 read-only 0 FCLKDIV register has not been written since the last reset. #0 1 FCLKDIV register has been written since the last reset. #1 FSEC Flash Security Register 0x1 8 read-only 0 0 SEC Flash Security Bits 0 2 read-only 00 Secured #00 01 Secured #01 10 Unsecured #10 11 Secured #11 RESERVED no description available 2 4 read-only KEYEN Backdoor Key Security Enable Bits 6 2 read-only 00 Disabled #00 01 Disabled #01 10 Enabled #10 11 Disabled #11 FCCOBIX Flash CCOB Index Register 0x2 8 read-write 0 0xFF CCOBIX Common Command Register Index 0 3 read-write RESERVED no description available 3 5 read-only FCNFG Flash Configuration Register 0x4 8 read-write 0 0xFF FSFD Force Single Bit Fault Detect 0 1 read-write 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected. #0 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt will be generated as long as FERCNFG[SFDIE] is set. #1 FDFD Force Double Bit Fault Detect 1 1 read-write 0 Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected. #0 1 Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as FERCNFG[DFDIE] is set. #1 RESERVED no description available 2 2 read-only IGNSF Ignore Single Bit Fault 4 1 read-write 0 All single-bit faults detected during array reads are reported. #0 1 Single-bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated. #1 RESERVED no description available 5 2 read-only CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt is disabled. #0 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set. #1 FERCNFG Flash Error Configuration Register 0x5 8 read-write 0 0xFF SFDIE Single Bit Fault Detect Interrupt Enable 0 1 read-write 0 SFDIF interrupt is disabled whenever the SFDIF flag is set. #0 1 An interrupt will be requested whenever the SFDIF flag is set. #1 DFDIE Double Bit Fault Detect Interrupt Enable 1 1 read-write 0 DFDIF interrupt is disabled. #0 1 An interrupt will be requested whenever the DFDIF flag is set. #1 RESERVED no description available 2 6 read-only FSTAT Flash Status Register 0x6 8 read-write 0x80 0xFF MGSTAT Memory Controller Command Completion Status Flag 0 2 read-only RESERVED no description available 2 1 read-only MGBUSY Memory Controller Busy Flag 3 1 read-only 0 Memory controller is idle. #0 1 Memory controller is busy executing a flash command (CCIF = 0). #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation is detected. #0 1 Protection violation is detected. #1 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error is detected. #0 1 Access error is detected. #1 RESERVED no description available 6 1 read-only CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command is in progress. #0 1 Flash command has completed. #1 FERSTAT Flash Error Status Register 0x7 8 read-write 0 0xFF SFDIF Single Bit Fault Detect Interrupt Flag 0 1 read-write 0 No single bit fault detected. #0 1 Single bit fault detected and corrected or a flash array read operation returning invalid data was attempted while command running. #1 DFDIF Double Bit Fault Detect Interrupt Flag 1 1 read-write 0 No double bit fault detected. #0 1 Double bit fault detected or a flash array read operation returning invalid data was attempted while command running. #1 RESERVED no description available 2 6 read-only FPROT Flash Protection Register 0x8 8 read-write 0 0 FPLS Flash Protection Lower Address Size 0 2 read-write FPLDIS Flash Protection Lower Address Range Disable 2 1 read-write 0 Protection/Unprotection enabled. #0 1 Protection/Unprotection disabled. #1 FPHS Flash Protection Higher Address Size 3 2 read-write FPHDIS Flash Protection Higher Address Range Disable 5 1 read-write 0 Protection/Unprotection enabled. #0 1 Protection/Unprotection disabled. #1 RNV6 Reserved Nonvolatile Bit 6 1 read-only FPOPEN Flash Protection Operation Enable 7 1 read-write 0 When FPOPEN is clear, the FPHDIS and FPLDIS fields define unprotected address ranges as specified by the corresponding FPHS and FPLS fields. #0 1 When FPOPEN is set, the FPHDIS and FPLDIS fields enable protection for the address range specified by the corresponding FPHS and FPLS fields. #1 EEPROT EEPROM Protection Register 0x9 8 read-write 0 0 DPS EEPROM Protection Size 0 3 read-write RESERVED no description available 3 4 read-only DPOPEN EEPROM Protection Control 7 1 read-write 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits. #0 1 Disables EEPROM memory protection from program and erase. #1 FCCOBHI Flash Common Command Object Register:High 0xA 8 read-write 0 0xFF CCOB Common Command Object Bit 15:8 0 8 read-write FCCOBLO Flash Common Command Object Register: Low 0xB 8 read-write 0 0xFF CCOB Common Command Object Bit 7:0 0 8 read-write FOPT Flash Option Register 0xC 8 read-only 0 0 NV Nonvolatile Bits 0 8 read-only IRQ Interrupt IRQ_ 0x40031000 0 0x1 registers INT_IRQ 7 SC Interrupt Pin Request Status and Control Register 0 8 read-write 0 0xFF IRQMOD IRQ Detection Mode 0 1 read-write 0 IRQ event is detected only on falling/rising edges. #0 1 IRQ event is detected on falling/rising edges and low/high levels. #1 IRQIE IRQ Interrupt Enable 1 1 read-write 0 Interrupt request when IRQF set is disabled (use polling). #0 1 Interrupt requested whenever IRQF = 1. #1 IRQACK IRQ Acknowledge 2 1 write-only IRQF IRQ Flag 3 1 read-only 0 No IRQ request #0 1 IRQ event is detected. #1 IRQPE IRQ Pin Enable 4 1 read-write 0 IRQ pin function is disabled. #0 1 IRQ pin function is enabled. #1 IRQEDG Interrupt Request (IRQ) Edge Select 5 1 read-write 0 IRQ is falling-edge or falling-edge/low-level sensitive. #0 1 IRQ is rising-edge or rising-edge/high-level sensitive. #1 IRQPDD Interrupt Request (IRQ) Pull Device Disable 6 1 read-write 0 IRQ pull device enabled if IRQPE = 1. #0 1 IRQ pull device disabled if IRQPE = 1. #1 RESERVED no description available 7 1 read-only CRC Cyclic Redundancy Check CRC_ 0x40032000 0 0xC registers DATALL CRC_DATALL register. CRC 0 8 read-write 0xFF 0xFF DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATA CRC Data register CRC 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write DATAL CRC_DATAL register. CRC 0 16 read-write 0xFFFF 0xFFFF DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALU CRC_DATALU register. 0x1 8 read-write 0xFF 0xFF DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write 0xFF 0xFF DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write 0xFFFF 0xFFFF DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write 0xFF 0xFF DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write 0xFF 0xFF GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write 0xFFFF 0xFFFF GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write 0xFF 0xFF GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write 0xFFFF 0xFFFF GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write 0xFF 0xFF GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write 0xFF 0xFF GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 24 read-only TCRC no description available 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 RESERVED no description available 27 1 read-only TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 CTRLHU CRC_CTRLHU register. 0xB 8 read-write 0 0xFF TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 RESERVED no description available 3 1 read-only TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 PIT Periodic Interrupt Timer PIT_ 0x40037000 0 0x120 registers INT_PIT_CH0 22 INT_PIT_CH1 23 MCR PIT Module Control Register 0 32 read-write 0x6 0xFFFFFFFF FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 29 read-only 2 0x10 0,1 LDVAL%s Timer Load Value Register 0x100 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write 2 0x10 0,1 CVAL%s Current Timer Value Register 0x104 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only 2 0x10 0,1 TCTRL%s Timer Control Register 0x108 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 RESERVED no description available 3 29 read-only 2 0x10 0,1 TFLG%s Timer Flag Register 0x10C 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 RESERVED no description available 1 31 read-only FTM0 FlexTimer Module FTM FTM0_ 0x40038000 0 0x1C registers INT_FTM0 17 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 1 read-only RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only FTM1 FlexTimer Module FTM FTM1_ 0x40039000 0 0x1C registers INT_FTM1 18 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 2 0x8 0,1 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 1 read-only RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 2 0x8 0,1 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only FTM2 FlexTimer Module FTM FTM2_ 0x4003A000 0 0x9C registers INT_FTM2 19 SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 RESERVED no description available 8 24 read-only CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write 6 0x8 0,1,2,3,4,5 C%sSC Channel (n) Status And Control 0xC 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 1 read-only RESERVED no description available 1 1 read-only ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only 6 0x8 0,1,2,3,4,5 C%sV Channel (n) Value 0x10 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 RESERVED no description available 8 24 read-only SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 RESERVED no description available 8 24 read-only OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 15 1 read-only COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 23 1 read-only COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 31 1 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 RESERVED no description available 8 24 read-write POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 RESERVED no description available 4 1 read-only FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 RESERVED no description available 8 24 read-only FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only BDMMODE Debug Mode 6 2 read-write RESERVED no description available 8 1 read-only GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 RESERVED no description available 11 21 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 RESERVED no description available 1 1 read-only CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 3 1 read-only INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 6 1 read-only SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 13 3 read-only HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 RESERVED no description available 21 11 read-only INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 RESERVED no description available 8 1 read-only LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 10 22 read-only ADC Analog-to-digital converter ADC_ 0x4003B000 0 0x1C registers INT_ADC0 15 SC1 Status and Control Register 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input Channel Select 0 5 read-write 10110 Temperature Sensor #10110 10111 Bandgap #10111 11101 VREFH #11101 11110 VREFL #11110 11111 Module disabled Reset FIFO in FIFO mode. #11111 ADCO Continuous Conversion Enable 5 1 read-write 0 One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggered. #0 1 Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. #1 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 RESERVED no description available 8 24 read-only SC2 Status and Control Register 2 0x4 32 read-write 0x8 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair (VREFH/VREFL). #00 01 Analog supply pin pair (VDDA/VSSA). #01 10 Reserved. #10 11 Reserved - Selects default voltage reference (VREFH/VREFL) pin pair. #11 FFULL Result FIFO full 2 1 read-only 0 Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO. #0 1 Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action. #1 FEMPTY Result FIFO empty 3 1 read-only 0 Indicates that ADC result FIFO have at least one valid new data. #0 1 Indicates that ADC result FIFO have no valid new data. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Compare triggers when input is less than compare level. #0 1 Compare triggers when input is greater than or equal to compare level. #1 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 RESERVED no description available 8 24 read-only SC3 Status and Control Register 3 0x8 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2 #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 MODE Conversion Mode Selection 2 2 read-write 00 8-bit conversion (N = 8) #00 01 10-bit conversion (N = 10) #01 10 12-bit conversion (N = 12) #10 11 Reserved #11 ADLSMP Long Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 ADIV Clock Divide Select 5 2 read-write 00 Divide ration = 1, and clock rate = Input clock. #00 01 Divide ration = 2, and clock rate = Input clock * 2. #01 10 Divide ration = 3, and clock rate = Input clock * 4. #10 11 Divide ration = 4, and clock rate = Input clock * 8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 High speed configuration. #0 1 Low power configuration:The power is reduced at the expense of maximum clock speed. #1 RESERVED no description available 8 24 read-only SC4 Status and Control Register 4 0xC 32 read-write 0 0xFFFFFFFF AFDEP no description available 0 3 read-write 000 FIFO is disabled. #000 001 2-level FIFO is enabled. #001 010 3-level FIFO is enabled.. #010 011 4-level FIFO is enabled. #011 100 5-level FIFO is enabled. #100 101 6-level FIFO is enabled. #101 110 7-level FIFO is enabled. #110 111 8-level FIFO is enabled. #111 RESERVED no description available 3 2 read-only ACFSEL no description available 5 1 read-write 0 OR all of compare trigger. #0 1 AND all of compare trigger. #1 ASCANE FIFO Scan Mode Enable 6 1 read-write 0 FIFO scan mode disabled. #0 1 FIFO scan mode enabled. #1 RESERVED no description available 7 25 read-only R Conversion Result Register 0x10 32 read-only 0 0xFFFFFFFF ADR Conversion Result 0 12 read-only RESERVED no description available 12 20 read-only CV Compare Value Register 0x14 32 read-write 0 0xFFFFFFFF CV Conversion Result[11:0] 0 12 read-write RESERVED no description available 12 20 read-only APCTL1 Pin Control 1 Register 0x18 32 read-write 0 0xFFFFFFFF ADPC ADC Pin Control 0 16 read-write 0 ADx pin I/O control enabled. #0 1 ADx pin I/O control disabled. #1 RESERVED no description available 16 16 read-only RTC Real-time counter RTC_ 0x4003D000 0 0xC registers INT_RTC 20 SC RTC Status and Control Register 0 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 4 read-only RTCO Real-Time Counter Output 4 1 read-write 0 Real-time counter output disabled. #0 1 Real-time counter output enabled. #1 RESERVED no description available 5 1 read-only RTIE Real-Time Interrupt Enable 6 1 read-write 0 Real-time interrupt requests are disabled. Use software polling. #0 1 Real-time interrupt requests are enabled. #1 RTIF Real-Time Interrupt Flag 7 1 read-write 0 RTC counter has not reached the value in the RTC modulo register. #0 1 RTC counter has reached the value in the RTC modulo register. #1 RTCPS Real-Time Clock Prescaler Select 8 3 read-write 000 Off #000 001 If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128. #001 010 If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256. #010 011 If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512. #011 100 If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024. #100 101 If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048. #101 110 If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100. #110 111 If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000. #111 RESERVED no description available 11 3 read-only RTCLKS Real-Time Clock Source Select 14 2 read-write 00 External clock source. #00 01 Real-time clock source is 1 kHz (LPOCLK). #01 10 Internal reference clock (ICSIRCLK). #10 11 Bus clock. #11 RESERVED no description available 16 16 read-only MOD RTC Modulo Register 0x4 32 read-write 0 0xFFFFFFFF MOD RTC Modulo 0 16 read-write RESERVED no description available 16 16 read-only CNT RTC Counter Register 0x8 32 read-only 0 0xFFFFFFFF CNT RTC Count 0 16 read-only RESERVED no description available 16 16 read-only SIM System Integration Module SIM_ 0x40048000 0 0x1C registers SRSID System Reset Status and ID Register 0 32 read-only 0x2000002 0xFFFFFFFF RESERVED no description available 0 1 read-only LVD Low Voltage Detect 1 1 read-only 0 Reset is not caused by LVD trip or POR. #0 1 Reset is caused by LVD trip or POR. #1 LOC Internal Clock Source Module Reset 2 1 read-only 0 Reset is not caused by the ICS module. #0 1 Reset is caused by the ICS module. #1 RESERVED no description available 3 2 read-only WDOG Watchdog (WDOG) 5 1 read-only 0 Reset is not caused by WDOG timeout. #0 1 Reset is caused by WDOG timeout. #1 PIN External Reset Pin 6 1 read-only 0 Reset is not caused by external reset pin. #0 1 Reset came from external reset pin. #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR. #0 1 POR caused reset. #1 RESERVED no description available 8 1 read-only LOCKUP Core Lockup 9 1 read-only 0 Reset is not caused by core LOCKUP event. #0 1 Reset is caused by core LOCKUP event. #1 SW Software 10 1 read-only 0 Reset is not caused by software setting of SYSRESETREQ bit. #0 1 Reset caused by software setting of SYSRESETREQ bit #1 MDMAP MDM-AP System Reset Request 11 1 read-only 0 Reset is not caused by host debugger system setting of the System Reset Request bit. #0 1 Reset is caused by host debugger system setting of the System Reset Request bit. #1 RESERVED no description available 12 1 read-only SACKERR Stop Mode Acknowledge Error Reset 13 1 read-only 0 Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode. #0 1 Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode. #1 RESERVED no description available 14 2 read-only PINID Device Pin ID 16 4 read-only 0000 8-pin #0000 0001 16-pin #0001 0010 20-pin #0010 0011 24-pin #0011 0100 32-pin #0100 0101 44-pin #0101 0110 48-pin #0110 0111 64-pin #0111 1000 80-pin #1000 1010 100-pin #1010 RevID Device Revision Number 20 4 read-only SUBFAMID Kinetis sub-family ID 24 4 read-only 0010 KEx2 sub-family #0010 FAMID Kinetis family ID 28 4 read-only 0000 KE0x family. #0000 SOPT System Options Register 0x4 32 read-write 0xE 0xFFFFFFFF RESERVED no description available 0 1 read-only NMIE NMI Pin Enable 1 1 read-write 0 PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as PTB4, FTM2_CH4, SPI0_MISO, or ACMP1_IN2. #0 1 PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as NMI. #1 RSTPE RESET Pin Enable 2 1 read-write 0 PTA5/IRQ/FTM0_CLK/RESET pin functions as PTA5, IRQ, or FTM0_CLK. #0 1 PTA5/IRQ/FTM0_CLK/RESET pin functions as RESET. #1 SWDE Single Wire Debug Port Pin Enable 3 1 read-write 0 PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/RTCO/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, RTCO, FTM1_CH0, or ACMP0_IN2 function. #0 1 PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/RTCO/FTM1CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function. #1 RESERVED no description available 4 4 read-only ADHWT ADC Hardware Trigger Source 8 2 read-write 00 RTC overflow as the ADC hardware trigger #00 01 PIT overflow as the ADC hardware trigger #01 10 FTM2 init trigger with 8-bit programmable delay #10 11 FTM2 match trigger with 8-bit programmable delay #11 RTCC Real-Time Counter Capture 10 1 read-write 0 RTC overflow is not connected to FTM1 input channel 1. #0 1 RTC overflow is connected to FTM1 input channel 1. #1 ACIC Analog Comparator to Input Capture Enable 11 1 read-write 0 ACMP0 output is not connected to FTM1 input channel 0. #0 1 ACMP0 output is connected to FTM1 input channel 0. #1 RXDCE UART0_RX Capture Select 12 1 read-write 0 UART0_RX input signal is connected to the UART0 module only. #0 1 UART0_RX input signal is connected to the UART0 module and FTM0 channel 1. #1 RXDFE UART0_RX Filter Select 13 1 read-write 0 UART0_RX input signal is connected to UART0 module directly. #0 1 UART0_RX input signal is filtered by ACMP, then injected to UART0. #1 FTMSYNC FTM2 Synchronization Select 14 1 write-only 0 No synchronization triggered. #0 1 Generates a PWM synchronization trigger to the FTM2 modules. #1 TXDME UART0_TX Modulation Select 15 1 read-write 0 UART0_TX output is connected to pinout directly. #0 1 UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout. #1 BUSREF BUS Clock Output select 16 3 read-write 000 Bus #000 001 Bus divided by 2 #001 010 Bus divided by 4 #010 011 Bus divided by 8 #011 100 Bus divided by 16 #100 101 Bus divided by 32 #101 110 Bus divided by 64 #110 111 Bus divided by 128 #111 CLKOE Bus Clock Output Enable 19 1 read-write 0 Bus clock output is disabled on PTH2. #0 1 Bus clock output is enabled on PTH2. #1 RESERVED no description available 20 3 read-only DLYACT FTM2 Trigger Delay Active 23 1 read-only 0 The delay is inactive. #0 1 The delay is active. #1 DELAY FTM2 Trigger Delay 24 8 read-write PINSEL Pin Selection Register 0x8 32 read-write 0 0xFFFFFFFF RESERVED no description available 0 4 read-only RTCPS RTCO Pin Select 4 1 read-write 0 RTCO is mapped on PTC4. #0 1 RTCO is mapped on PTC5. #1 I2C0PS I2C0 Port Pin Select 5 1 read-write 0 I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. #0 1 I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. #1 SPI0PS SPI0 Pin Select 6 1 read-write 0 SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTB2, PTB3, PTB4, and PTB5. #0 1 SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTE0, PTE1, PTE2, and PTE3. #1 UART0PS UART0 Pin Select 7 1 read-write 0 UART0_RX and UART0_TX are mapped on PTB0 and PTB1. #0 1 UART0_RX and UART0_TX are mapped on PTA2 and PTA3. #1 FTM0PS0 FTM0[0] Port Pin Select 8 1 read-write 0 FTM0[0] channels are mapped on PTA0. #0 1 FTM0[0] channels are mapped on PTB2. #1 FTM0PS1 FTM0[1] Port Pin Select 9 1 read-write 0 FTM0[1] channels are mapped on PTA1. #0 1 FTM0[1] channels are mapped on PTB3. #1 FTM1PS0 FTM1[0] Port Pin Select 10 1 read-write 0 FTM1[0] channels are mapped on PTC4. #0 1 FTM1[0] channels are mapped on PTH2. #1 FTM1PS1 FTM1[1] Port Pin Select 11 1 read-write 0 FTM1[1] channels are mapped on PTC5. #0 1 FTM1[1] channels are mapped on PTE7. #1 FTM2PS0 FTM2[0] Port Pin Select 12 1 read-write 0 FTM2[0] channels are mapped on PTC0. #0 1 FTM2[0] channels are mapped on PTH0. #1 FTM2PS1 FTM2[1] Port Pin Select 13 1 read-write 0 FTM2[1] channels are mapped on PTC1. #0 1 FTM2[1] channels are mapped on PTH1. #1 FTM2PS2 FTM2[2] Port Pin Select 14 1 read-write 0 FTM2[2] channels are mapped on PTC2. #0 1 FTM2[2] channels are mapped on PTD0. #1 FTM2PS3 FTM2[3] Port Pin Select 15 1 read-write 0 FTM2[3] channels are mapped on PTC3. #0 1 FTM2[3] channels are mapped on PTD1. #1 RESERVED no description available 16 16 read-only SCGC System Clock Gating Control Register 0xC 32 read-write 0x3000 0xFFFFFFFF RTC RTC Clock Gate Control 0 1 read-write 0 Bus clock to the RTC module is disabled. #0 1 Bus clock to the RTC module is enabled. #1 PIT PIT Clock Gate Control 1 1 read-write 0 Bus clock to the PIT module is disabled. #0 1 Bus clock to the PIT module is enabled. #1 RESERVED no description available 2 3 read-only FTM0 FTM0 Clock Gate Control 5 1 read-write 0 Bus clock to the FTM0 module is disabled. #0 1 Bus clock to the FTM0 module is enabled. #1 FTM1 FTM1 Clock Gate Control 6 1 read-write 0 Bus clock to the FTM1 module is disabled. #0 1 Bus clock to the FTM1 module is enabled. #1 FTM2 FTM2 Clock Gate Control 7 1 read-write 0 Bus clock to the FTM2 module is disabled. #0 1 Bus clock to the FTM2 module is enabled. #1 RESERVED no description available 8 2 read-only CRC CRC Clock Gate Control 10 1 read-write 0 Bus clock to the CRC module is disabled. #0 1 Bus clock to the CRC module is enabled. #1 RESERVED no description available 11 1 read-only FLASH Flash Clock Gate Control 12 1 read-write 0 Bus clock to the flash module is disabled. #0 1 Bus clock to the flash module is enabled. #1 SWD SWD (single wire debugger) Clock Gate Control 13 1 read-write 0 Bus clock to the SWD module is disabled. #0 1 Bus clock to the SWD module is enabled. #1 RESERVED no description available 14 3 read-only I2C I2C Clock Gate Control 17 1 read-write 0 Bus clock to the IIC module is disabled. #0 1 Bus clock to the IIC module is enabled. #1 SPI0 SPI0 Clock Gate Control 18 1 read-write 0 Bus clock to the SPI0 module is disabled. #0 1 Bus clock to the SPI0 module is enabled. #1 SPI1 SPI1 Clock Gate Control 19 1 read-write 0 Bus clock to the SPI1 module is disabled. #0 1 Bus clock to the SPI1 module is enabled. #1 UART0 UART0 Clock Gate Control 20 1 read-write 0 Bus clock to the UART0 module is disabled. #0 1 Bus clock to the UART0 module is enabled. #1 UART1 UART1 Clock Gate Control 21 1 read-write 0 Bus clock to the UART1 module is disabled. #0 1 Bus clock to the UART1 module is enabled. #1 UART2 UART2 Clock Gate Control 22 1 read-write 0 Bus clock to the UART2 module is disabled. #0 1 Bus clock to the UART2 module is enabled. #1 RESERVED no description available 23 1 read-only KBI0 KBI0 Clock Gate Control 24 1 read-write 0 Bus clock to the KBI0 module is disabled. #0 1 Bus clock to the KBI0 module is enabled. #1 KBI1 KBI1 Clock Gate Control 25 1 read-write 0 Bus clock to the KBI1 module is disabled. #0 1 Bus clock to the KBI1 module is enabled. #1 RESERVED no description available 26 1 read-only IRQ IRQ Clock Gate Control 27 1 read-write 0 Bus clock to the IRQ module is disabled. #0 1 Bus clock to the IRQ module is enabled. #1 RESERVED no description available 28 1 read-only ADC ADC Clock Gate Control 29 1 read-write 0 Bus clock to the ADC module is disabled. #0 1 Bus clock to the ADC module is enabled. #1 ACMP0 ACMP0 Clock Gate Control 30 1 read-write 0 Bus clock to the ACMP0 module is disabled. #0 1 Bus clock to the ACMP0 module is enabled. #1 ACMP1 ACMP1 Clock Gate Control 31 1 read-write 0 Bus clock to the ACMP1 module is disabled. #0 1 Bus clock to the ACMP1 module is enabled. #1 UUIDL Universally Unique Identifier Low Register 0x10 32 read-only 0 0 ID Universally Unique Identifier 0 32 read-only UUIDH Universally Unique Identifier High Register 0x14 32 read-only 0 0 ID Universally Unique Identifier 0 32 read-only BUSDIV BUS Clock Divider Register 0x18 32 read-write 0 0xFFFFFFFF BUSDIV BUS Clock Divider 0 1 read-write 0 Bus clock is same as ICSOUTCLK. #0 1 Bus clock is ICSOUTCLK divided by 2. #1 RESERVED no description available 1 31 read-only PORT Port control and interrupts PORT_ 0x40049000 0 0x10 registers IOFLT Port Filter Register 0 32 read-write 0xC00000 0xFFFFFFFF FLTA Filter Selection for Input from PTA 0 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTB Filter Selection for Input from PTB 2 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTC Filter Selection for Input from PTC 4 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTD Filter Selection for Input from PTD 6 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTE Filter Selection for Input from PTD 8 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTF Filter Selection for Input from PTF 10 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTG Filter Selection for Input from PTG 12 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTH Filter Selection for Input from PTH 14 2 read-write 00 BUSCLK #00 01 FLTDIV1 #01 10 FLTDIV2 #10 11 FLTDIV3 #11 FLTRST Filter Selection for Input from RESET/IRQ 16 2 read-write 00 No filter. #00 01 Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. #01 10 Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. #10 11 FLTDIV3 #11 FLTKBI0 Filter selection for Input from KBI0 18 2 read-write 00 No filter. #00 01 Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. #01 10 Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. #10 11 FLTDIV3 #11 FLTKBI1 Filter Selection for Input from KBI1 20 2 read-write 00 No filter #00 01 Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. #01 10 Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. #10 11 FLTDIV3 #11 FLTNMI Filter Selection for Input from NMI 22 2 read-write 00 No filter. #00 01 Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. #01 10 Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. #10 11 FLTDIV3 #11 FLTDIV1 Filter Division Set 1 24 2 read-write 00 BUSCLK/2 #00 01 BUSCLK/4 #01 10 BUSCLK/8 #10 11 BUSCLK/16 #11 FLTDIV2 Filter Division Set 2 26 3 read-write 000 BUSCLK/32 #000 001 BUSCLK/64 #001 010 BUSCLK/128 #010 011 BUSCLK/256 #011 100 BUSCLK/512 #100 101 BUSCLK/1024 #101 110 BUSCLK/2048 #110 111 BUSCLK/4096 #111 FLTDIV3 Filter Division Set 3 29 3 read-write 000 LPOCLK #000 001 LPOCLK/2 #001 010 LPOCLK/4 #010 011 LPOCLK/8 #011 100 LPOCLK/16 #100 101 LPOCLK/32 #101 110 LPOCLK/64 #110 111 LPOCLK/128 #111 PUEL Port Pullup Enable Low Register 0x4 32 read-write 0x100000 0xFFFFFFFF PTAPE0 Pull Enable for Port A Bit 0 0 1 read-write 0 Pullup is disabled for port A bit 0. #0 1 Pullup is enabled for port A bit 0. #1 PTAPE1 Pull Enable for Port A Bit 1 1 1 read-write 0 Pullup is disabled for port A bit 1. #0 1 Pullup is enabled for port A bit 1. #1 PTAPE2 Pull Enable for Port A Bit 2 2 1 read-write 0 Pullup is disabled for port A bit 2. #0 1 Pullup is enabled for port A bit 2. #1 PTAPE3 Pull Enable for Port A Bit 3 3 1 read-write 0 Pullup is disabled for port A bit 3. #0 1 Pullup is enabled for port A bit 3. #1 PTAPE4 Pull Enable for Port A Bit 4 4 1 read-write 0 Pullup is disabled for port A bit 4. #0 1 Pullup is enabled for port A bit 4. #1 PTAPE5 Pull Enable for Port A Bit 5 5 1 read-write 0 Pullup is disabled for port A bit 5. #0 1 Pullup is enabled for port A bit 5. #1 PTAPE6 Pull Enable for Port A Bit 6 6 1 read-write 0 Pullup is disabled for port A bit 6. #0 1 Pullup is enabled for port A bit 6. #1 PTAPE7 Pull Enable for Port A Bit 7 7 1 read-write 0 Pullup is disabled for port A bit 7. #0 1 Pullup is enabled for port A bit 7. #1 PTBPE0 Pull Enable for Port B Bit 0 8 1 read-write 0 Pullup is disabled for port B bit 0. #0 1 Pullup is enabled for port B bit 0. #1 PTBPE1 Pull Enable for Port B Bit 1 9 1 read-write 0 Pullup is disabled for port B bit 1. #0 1 Pullup is enabled for port B bit 1. #1 PTBPE2 Pull Enable for Port B Bit 2 10 1 read-write 0 Pullup is disabled for port B bit 2. #0 1 Pullup is enabled for port B bit 2. #1 PTBPE3 Pull Enable for Port B Bit 3 11 1 read-write 0 Pullup is disabled for port B bit 3. #0 1 Pullup is enabled for port B bit 3. #1 PTBPE4 Pull Enable for Port B Bit 4 12 1 read-write 0 Pullup is disabled for port B bit 4. #0 1 Pullup is enabled for port B bit 4. #1 PTBPE5 Pull Enable for Port B Bit 5 13 1 read-write 0 Pullup is disabled for port B bit 5. #0 1 Pullup is enabled for port B bit 5. #1 PTBPE6 Pull Enable for Port B Bit 6 14 1 read-write 0 Pullup is disabled for port B bit 6. #0 1 Pullup is enabled for port B bit 6. #1 PTBPE7 Pull Enable for Port B Bit 7 15 1 read-write 0 Pullup is disabled for port B bit 7. #0 1 Pullup is enabled for port B bit 7. #1 PTCPE0 Pull Enable for Port C Bit 0 16 1 read-write 0 Pullup is disabled for port C bit 0. #0 1 Pullup is enabled for port C bit 0. #1 PTCPE1 Pull Enable for Port C Bit 1 17 1 read-write 0 Pullup is disabled for port C bit 1. #0 1 Pullup is enabled for port C bit 1. #1 PTCPE2 Pull Enable for Port C Bit 2 18 1 read-write 0 Pullup is disabled for port C bit 2. #0 1 Pullup is enabled for port C bit 2. #1 PTCPE3 Pull Enable for Port C Bit 3 19 1 read-write 0 Pullup is disabled for port C bit 3. #0 1 Pullup is enabled for port C bit 3. #1 PTCPE4 Pull Enable for Port C Bit 4 20 1 read-write 0 Pullup is disabled for port C bit 4. #0 1 Pullup is enabled for port C bit 4. #1 PTCPE5 Pull Enable for Port C Bit 5 21 1 read-write 0 Pullup is disabled for port C bit 5. #0 1 Pullup is enabled for port C bit 5. #1 PTCPE6 Pull Enable for Port C Bit 6 22 1 read-write 0 Pullup is disabled for port C bit 6. #0 1 Pullup is enabled for port C bit 6. #1 PTCPE7 Pull Enable for Port C Bit 7 23 1 read-write 0 Pullup is disabled for port C bit 7. #0 1 Pullup is enabled for port C bit 7. #1 PTDPE0 Pull Enable for Port D Bit 0 24 1 read-write 0 Pullup is disabled for port D bit 0. #0 1 Pullup is enabled for port D bit 0. #1 PTDPE1 Pull Enable for Port D Bit 1 25 1 read-write 0 Pullup is disabled for port D bit 1. #0 1 Pullup is enabled for port D bit 1. #1 PTDPE2 Pull Enable for Port D Bit 2 26 1 read-write 0 Pullup is disabled for port D bit 2. #0 1 Pullup is enabled for port D bit 2. #1 PTDPE3 Pull Enable for Port D Bit 3 27 1 read-write 0 Pullup is disabled for port D bit 3. #0 1 Pullup is enabled for port D bit 3. #1 PTDPE4 Pull Enable for Port D Bit 4 28 1 read-write 0 Pullup is disabled for port D bit 4. #0 1 Pullup is enabled for port D bit 4. #1 PTDPE5 Pull Enable for Port D Bit 5 29 1 read-write 0 Pullup is disabled for port D bit 5. #0 1 Pullup is enabled for port D bit 5. #1 PTDPE6 Pull Enable for Port D Bit 6 30 1 read-write 0 Pullup is disabled for port D bit 6. #0 1 Pullup is enabled for port D bit 6. #1 PTDPE7 Pull Enable for Port D Bit 7 31 1 read-write 0 Pullup is disabled for port D bit 7. #0 1 Pullup is enabled for port D bit 7. #1 PUEH Port Pullup Enable High Register 0x8 32 read-write 0 0xFFFFFFFF PTEPE0 Pull Enable for Port E Bit 0 0 1 read-write 0 Pullup is disabled for port E bit 0. #0 1 Pullup is enabled for port E bit 0. #1 PTEPE1 Pull Enable for Port E Bit 1 1 1 read-write 0 Pullup is disabled for port E bit 1. #0 1 Pullup is enabled for port E bit 1. #1 PTEPE2 Pull Enable for Port E Bit 2 2 1 read-write 0 Pullup is disabled for port E bit 2. #0 1 Pullup is enabled for port E bit 2. #1 PTEPE3 Pull Enable for Port E Bit 3 3 1 read-write 0 Pullup is disabled for port E bit 3. #0 1 Pullup is enabled for port E bit 3. #1 PTEPE4 Pull Enable for Port E Bit 4 4 1 read-write 0 Pullup is disabled for port E bit 4. #0 1 Pullup is enabled for port E bit 4. #1 PTEPE5 Pull Enable for Port E Bit 5 5 1 read-write 0 Pullup is disabled for port E bit 5. #0 1 Pullup is enabled for port E bit 5. #1 PTEPE6 Pull Enable for Port E Bit 6 6 1 read-write 0 Pullup is disabled for port E bit 6. #0 1 Pullup is enabled for port E bit 6. #1 PTEPE7 Pull Enable for Port E Bit 7 7 1 read-write 0 Pullup is disabled for port E bit 7. #0 1 Pullup is enabled for port E bit 7. #1 PTFPE0 Pull Enable for Port F Bit 0 8 1 read-write 0 Pullup is disabled for port F bit 0. #0 1 Pullup is enabled for port F bit 0. #1 PTFPE1 Pull Enable for Port F Bit 1 9 1 read-write 0 Pullup is disabled for port F bit 1. #0 1 Pullup is enabled for port F bit 1. #1 PTFPE2 Pull Enable for Port F Bit 2 10 1 read-write 0 Pullup is disabled for port F bit 2. #0 1 Pullup is enabled for port F bit 2. #1 PTFPE3 Pull Enable for Port F Bit 3 11 1 read-write 0 Pullup is disabled for port F bit 3. #0 1 Pullup is enabled for port F bit 3. #1 PTFPE4 Pull Enable for Port F Bit 4 12 1 read-write 0 Pullup is disabled for port F bit 4. #0 1 Pullup is enabled for port F bit 4. #1 PTFPE5 Pull Enable for Port F Bit 5 13 1 read-write 0 Pullup is disabled for port F bit 5. #0 1 Pullup is enabled for port F bit 5. #1 PTFPE6 Pull Enable for Port F Bit 6 14 1 read-write 0 Pullup is disabled for port F bit 6. #0 1 Pullup is enabled for port F bit 6. #1 PTFPE7 Pull Enable for Port F Bit 7 15 1 read-write 0 Pullup is disabled for port F bit 7. #0 1 Pullup is enabled for port F bit 7. #1 PTGPE0 Pull Enable for Port G Bit 0 16 1 read-write 0 Pullup is disabled for port G bit 0. #0 1 Pullup is enabled for port G bit 0. #1 PTGPE1 Pull Enable for Port G Bit 1 17 1 read-write 0 Pullup is disabled for port G bit 1. #0 1 Pullup is enabled for port G bit 1. #1 PTGPE2 Pull Enable for Port G Bit 2 18 1 read-write 0 Pullup is disabled for port G bit 2. #0 1 Pullup is enabled for port G bit 2. #1 PTGPE3 Pull Enable for Port G Bit 3 19 1 read-write 0 Pullup is disabled for port G bit 3. #0 1 Pullup is enabled for port G bit 3. #1 RESERVED no description available 20 4 read-only PTHPE0 Pull Enable for Port H Bit 0 24 1 read-write 0 Pullup is disabled for port H bit 0. #0 1 Pullup is enabled for port H bit 0. #1 PTHPE1 Pull Enable for Port H Bit 1 25 1 read-write 0 Pullup is disabled for port H bit 1. #0 1 Pullup is enabled for port H bit 1. #1 PTHPE2 Pull Enable for Port H Bit 2 26 1 read-write 0 Pullup is disabled for port H bit 2. #0 1 Pullup is enabled for port H bit 2. #1 RESERVED no description available 27 3 read-only PTHPE6 Pull Enable for Port H Bit 6 30 1 read-write 0 Pullup is disabled for port H bit 6. #0 1 Pullup is enabled for port H bit 6. #1 PTHPE7 Pull Enable for Port H Bit 7 31 1 read-write 0 Pullup is disabled for port H bit 7. #0 1 Pullup is enabled for port H bit 7. #1 HDRVE Port High Drive Enable Register 0xC 32 read-write 0 0xFFFFFFFF PTB4 High Current Drive Capability of PTB4 0 1 read-write 0 PTB4 is disabled to offer high current drive capability. #0 1 PTB4 is enabled to offer high current drive capability. #1 PTB5 High Current Drive Capability of PTB5 1 1 read-write 0 PTB5 is disabled to offer high current drive capability. #0 1 PTB5 is enabled to offer high current drive capability. #1 PTD0 High Current Drive Capability of PTD0 2 1 read-write 0 PTD0 is disabled to offer high current drive capability. #0 1 PTD0 is enabled to offer high current drive capability. #1 PTD1 High Current Drive Capability of PTD1 3 1 read-write 0 PTD1 is disabled to offer high current drive capability. #0 1 PTD1 is enable to offer high current drive capability. #1 PTE0 High Current Drive Capability of PTE0 4 1 read-write 0 PTE0 is disabled to offer high current drive capability. #0 1 PTE0 is enable to offer high current drive capability. #1 PTE1 High Current Drive Capability of PTE1 5 1 read-write 0 PTE1 is disabled to offer high current drive capability. #0 1 PTE1 is enabled to offer high current drive capability. #1 PTH0 High Current Drive Capability of PTH0 6 1 read-write 0 PTH0 is disabled to offer high current drive capability. #0 1 PTH0 is enabled to offer high current drive capability. #1 PTH1 High Current Drive Capability of PTH1 7 1 read-write 0 PTH1 is disabled to offer high current drive capability. #0 1 PTH1 is enabled to offer high current drive capability. #1 RESERVED no description available 8 24 read-only WDOG Watchdog timer WDOG_ 0x40052000 0 0x8 registers INT_Watchdog 28 CS1 Watchdog Control and Status Register 1 0 8 read-write 0x80 0xFF STOP Stop Enable 0 1 read-write 0 Watchdog disabled in chip stop mode. #0 1 Watchdog enabled in chip stop mode. #1 WAIT Wait Enable 1 1 read-write 0 Watchdog disabled in chip wait mode. #0 1 Watchdog enabled in chip wait mode. #1 DBG Debug Enable 2 1 read-write 0 Watchdog disabled in chip debug mode. #0 1 Watchdog enabled in chip debug mode. #1 TST Watchdog Test 3 2 read-write 00 Watchdog test mode disabled. #00 01 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. #01 10 Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL. #10 11 Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH. #11 UPDATE Allow updates 5 1 read-write 0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. #0 1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. #1 INT Watchdog Interrupt 6 1 read-write 0 Watchdog interrupts are disabled. Watchdog resets are not delayed. #0 1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks. #1 EN Watchdog Enable 7 1 read-write 0 Watchdog disabled. #0 1 Watchdog enabled. #1 CS2 Watchdog Control and Status Register 2 0x1 8 read-write 0x1 0xFF CLK Watchdog Clock 0 2 read-write 00 Bus clock. #00 01 1 kHz internal low-power oscillator (LPOCLK). #01 10 32 kHz internal oscillator (ICSIRCLK). #10 11 External clock source. #11 RESERVED no description available 2 2 read-only PRES Watchdog Prescalar 4 1 read-write 0 256 prescalar disabled. #0 1 256 prescalar enabled. #1 RESERVED no description available 5 1 read-only FLG Watchdog Interrupt Flag 6 1 read-write 0 No interrupt occurred. #0 1 An interrupt occurred. #1 WIN Watchdog Window 7 1 read-write 0 Window mode disabled. #0 1 Window mode enabled. #1 CNT WDOG_CNT register. WDOG 0x2 16 read-write 0 0xFFFF CNT Watchdog Counter Value 0 16 read-write CNTH Watchdog Counter Register: High WDOG 0x2 8 read-only 0 0xFF CNTHIGH High byte of the Watchdog Counter 0 8 read-only CNTL Watchdog Counter Register: Low 0x3 8 read-only 0 0xFF CNTLOW Low byte of the Watchdog Counter 0 8 read-only TOVALH Watchdog Timeout Value Register: High WDOG 0x4 8 read-write 0 0xFF TOVALHIGH High byte of the timeout value 0 8 read-write TOVAL WDOG_TOVAL register. WDOG 0x4 16 read-write 0 0xFFFF TOVAL Watchdog Timeout Value 0 16 read-write TOVALL Watchdog Timeout Value Register: Low 0x5 8 read-write 0x4 0xFF TOVALLOW Low byte of the timeout value 0 8 read-write WINH Watchdog Window Register: High WDOG 0x6 8 read-write 0 0xFF WINHIGH High byte of Watchdog Window 0 8 read-write WIN WDOG_WIN register. WDOG 0x6 16 read-write 0 0xFFFF WIN Watchdog Window Value 0 16 read-write WINL Watchdog Window Register: Low 0x7 8 read-write 0 0xFF WINLOW Low byte of Watchdog Window 0 8 read-write ICS Clock management ICS_ 0x40064000 0 0x5 registers INT_ICS 27 C1 ICS Control Register 1 0 8 read-write 0x4 0xFF IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop. #1 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 ICSIRCLK is inactive. #0 1 ICSIRCLK is active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 Internal reference clock is selected. #1 RDIV Reference Divider 3 3 read-write CLKS Clock Source Select 6 2 read-write 00 Output of FLL is selected. #00 01 Internal reference clock is selected. #01 10 External reference clock is selected. #10 11 Reserved, defaults to 00. #11 C2 ICS Control Register 2 0x1 8 read-write 0x20 0xFF RESERVED no description available 0 4 read-only LP Low Power Select 4 1 read-write 0 FLL is not disabled in bypass mode. #0 1 FLL is disabled in bypass modes unless debug is active. #1 BDIV Bus Frequency Divider 5 3 read-write 000 Encoding 0-Divides the selected clock by 1. #000 001 Encoding 1-Divides the selected clock by 2 (reset default). #001 010 Encoding 2-Divides the selected clock by 4. #010 011 Encoding 3-Divides the selected clock by 8. #011 100 Encoding 4-Divides the selected clock by 16. #100 101 Encoding 5-Divides the selected clock by 32. #101 110 Encoding 6-Divides the selected clock by 64. #110 111 Encoding 7-Divides the selected clock by 128. #111 C3 ICS Control Register 3 0x2 8 read-write 0 0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 ICS Control Register 4 0x3 8 read-write 0 0xFE SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write RESERVED no description available 1 4 read-only CME Clock Monitor Enable 5 1 read-write 0 Clock monitor is disabled. #0 1 Generates a reset request on loss of external clock. #1 RESERVED no description available 6 1 read-only LOLIE Loss of Lock Interrupt 7 1 read-write 0 No request on loss of lock. #0 1 Generates an interrupt request on loss of lock. #1 S ICS Status Register 0x4 8 read-write 0x10 0xFF RESERVED no description available 0 2 read-only CLKST Clock Mode Status 2 2 read-only 00 Output of FLL is selected. #00 01 FLL Bypassed, internal reference clock is selected. #01 10 FLL Bypassed, external reference clock is selected. #10 11 Reserved. #11 IREFST Internal Reference Status 4 1 read-only 0 Source of reference clock is external clock. #0 1 Source of reference clock is internal clock. #1 RESERVED no description available 5 1 read-only LOCK Lock Status 6 1 read-only 0 FLL is currently unlocked. #0 1 FLL is currently locked. #1 LOLS Loss of Lock Status 7 1 read-write oneToClear 0 FLL has not lost lock since LOLS was last cleared. #0 1 FLL has lost lock since LOLS was last cleared. #1 OSC Oscillator OSC_ 0x40065000 0 0x1 registers CR OSC Control Register 0 8 read-write 0 0xFF OSCINIT OSC Initialization 0 1 read-only 0 Oscillator initialization is not complete. #0 1 Oscillator initialization is completed. #1 HGO High Gain Oscillator Select 1 1 read-write 0 Low-power mode #0 1 High-gain mode #1 RANGE Frequency Range Select 2 1 read-write 0 Low frequency range of 32 kHz. #0 1 High frequency range of 4-20 MHz. #1 RESERVED no description available 3 1 read-only OSCOS OSC Output Select 4 1 read-write 0 External clock source from EXTAL pin is selected. #0 1 Oscillator clock source is selected. #1 OSCSTEN OSC Enable in Stop mode 5 1 read-write 0 OSC clock is disabled in Stop mode. #0 1 OSC clock stays enabled in Stop mode. #1 RESERVED no description available 6 1 read-only OSCEN OSC Enable 7 1 read-write 0 OSC module is disabled. #0 1 OSC module is enabled. #1 I2C0 Inter-Integrated Circuit I2C0_ 0x40066000 0 0xC registers INT_I2C0 8 A1 I2C Address Register 1 0 8 read-write 0 0xFF RESERVED no description available 0 1 read-only AD Address 1 7 read-write F I2C Frequency Divider register 0x1 8 read-write 0 0xFF ICR ClockRate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 11 Reserved #11 C1 I2C Control Register 1 0x2 8 read-write 0 0xFF RESERVED no description available 0 1 read-only WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 RSTA Repeat START 2 1 write-only TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 S I2C Status register 0x3 8 read-write 0x80 0xFF RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 D I2C Data I/O register 0x4 8 read-write 0 0xFF DATA Data 0 8 read-write C2 I2C Control Register 2 0x5 8 read-write 0 0xFF AD Slave Address 0 3 read-write RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 RESERVED no description available 5 1 read-only ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write 0 0xFF FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 RA I2C Range Address register 0x7 8 read-write 0 0xFF RESERVED no description available 0 1 read-only RAD Range Slave Address 1 7 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write 0 0xFF SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 A2 I2C Address Register 2 0x9 8 read-write 0xC2 0xFF RESERVED no description available 0 1 read-only SAD SMBus Address 1 7 read-write SLTH I2C SCL Low Timeout Register High 0xA 8 read-write 0 0xFF SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write 0 0xFF SSLT no description available 0 8 read-write UART0 Universal Asynchronous Receiver/Transmitter (UART) UART UART0_ 0x4006A000 0 0x8 registers INT_UART0 12 BDH UART Baud Rate Register: High 0 8 read-write 0 0xFF SBR Baud Rate Modulo Divisor. 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 One stop bit. #0 1 Two stop bit. #1 RXEDGIE RxD Input Active Edge Interrupt Enable (for RXEDGIF) 6 1 read-write 0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable (for LBKDIF) 7 1 read-write 0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. #1 BDL UART Baud Rate Register: Low 0x1 8 read-write 0x4 0xFF SBR Baud Rate Modulo Divisor 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (lsb first) + stop. #0 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. #0 1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU. #0 1 UART clocks freeze while CPU is in wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RxD and TxD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal UART receiver operation. #0 1 UART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable for IDLE 4 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable for RDRF 5 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for TC 6 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable for TDRE 7 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected. #0 1 Noise detected in the received character in UART_D. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun. #0 1 Receive overrun (new UART data lost). #1 IDLE Idle Line Flag 4 1 read-only 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 Receive data register empty. #0 1 Receive data register full. #1 TC Transmission Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 Transmit data register (buffer) full. #0 1 Transmit data register (buffer) empty. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break detection is disabled. #0 1 Break detection is enabled (Break character is detected at length 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1)). #1 BRK13 Break Character Generation Length 2 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). #1 RWUID Receive Wake Up Idle Detect 3 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 RESERVED no description available 5 1 read-only RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupts disabled; use polling). #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupts disabled; use polling). #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 3 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 4 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TxD Pin Direction in Single-Wire Mode 5 1 read-write 0 TxD pin is an input in single-wire mode. #0 1 TxD pin is an output in single-wire mode. #1 T8 Ninth Data Bit for Transmitter 6 1 read-write R8 Ninth Data Bit for Receiver 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF R0T0 no description available 0 1 read-write R1T1 no description available 1 1 read-write R2T2 no description available 2 1 read-write R3T3 no description available 3 1 read-write R4T4 no description available 4 1 read-write R5T5 no description available 5 1 read-write R6T6 no description available 6 1 read-write R7T7 no description available 7 1 read-write UART1 Universal Asynchronous Receiver/Transmitter (UART) UART UART1_ 0x4006B000 0 0x8 registers INT_UART1 13 BDH UART Baud Rate Register: High 0 8 read-write 0 0xFF SBR Baud Rate Modulo Divisor. 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 One stop bit. #0 1 Two stop bit. #1 RXEDGIE RxD Input Active Edge Interrupt Enable (for RXEDGIF) 6 1 read-write 0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable (for LBKDIF) 7 1 read-write 0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. #1 BDL UART Baud Rate Register: Low 0x1 8 read-write 0x4 0xFF SBR Baud Rate Modulo Divisor 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (lsb first) + stop. #0 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. #0 1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU. #0 1 UART clocks freeze while CPU is in wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RxD and TxD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal UART receiver operation. #0 1 UART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable for IDLE 4 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable for RDRF 5 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for TC 6 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable for TDRE 7 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected. #0 1 Noise detected in the received character in UART_D. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun. #0 1 Receive overrun (new UART data lost). #1 IDLE Idle Line Flag 4 1 read-only 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 Receive data register empty. #0 1 Receive data register full. #1 TC Transmission Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 Transmit data register (buffer) full. #0 1 Transmit data register (buffer) empty. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break detection is disabled. #0 1 Break detection is enabled (Break character is detected at length 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1)). #1 BRK13 Break Character Generation Length 2 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). #1 RWUID Receive Wake Up Idle Detect 3 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 RESERVED no description available 5 1 read-only RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupts disabled; use polling). #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupts disabled; use polling). #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 3 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 4 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TxD Pin Direction in Single-Wire Mode 5 1 read-write 0 TxD pin is an input in single-wire mode. #0 1 TxD pin is an output in single-wire mode. #1 T8 Ninth Data Bit for Transmitter 6 1 read-write R8 Ninth Data Bit for Receiver 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF R0T0 no description available 0 1 read-write R1T1 no description available 1 1 read-write R2T2 no description available 2 1 read-write R3T3 no description available 3 1 read-write R4T4 no description available 4 1 read-write R5T5 no description available 5 1 read-write R6T6 no description available 6 1 read-write R7T7 no description available 7 1 read-write UART2 Universal Asynchronous Receiver/Transmitter (UART) UART UART2_ 0x4006C000 0 0x8 registers INT_UART2 14 BDH UART Baud Rate Register: High 0 8 read-write 0 0xFF SBR Baud Rate Modulo Divisor. 0 5 read-write SBNS Stop Bit Number Select 5 1 read-write 0 One stop bit. #0 1 Two stop bit. #1 RXEDGIE RxD Input Active Edge Interrupt Enable (for RXEDGIF) 6 1 read-write 0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. #1 LBKDIE LIN Break Detect Interrupt Enable (for LBKDIF) 7 1 read-write 0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. #1 BDL UART Baud Rate Register: Low 0x1 8 read-write 0x4 0xFF SBR Baud Rate Modulo Divisor 0 8 read-write C1 UART Control Register 1 0x2 8 read-write 0 0xFF PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (lsb first) + stop. #0 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. #0 1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU. #0 1 UART clocks freeze while CPU is in wait mode. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - RxD and TxD use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. #1 C2 UART Control Register 2 0x3 8 read-write 0 0xFF SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal UART receiver operation. #0 1 UART receiver in standby waiting for wakeup condition. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 ILIE Idle Line Interrupt Enable for IDLE 4 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 RIE Receiver Interrupt Enable for RDRF 5 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 TCIE Transmission Complete Interrupt Enable for TC 6 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TIE Transmit Interrupt Enable for TDRE 7 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 S1 UART Status Register 1 0x4 8 read-only 0xC0 0xFF PF Parity Error Flag 0 1 read-only 0 No parity error. #0 1 Parity error. #1 FE Framing Error Flag 1 1 read-only 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 NF Noise Flag 2 1 read-only 0 No noise detected. #0 1 Noise detected in the received character in UART_D. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun. #0 1 Receive overrun (new UART data lost). #1 IDLE Idle Line Flag 4 1 read-only 0 No idle line detected. #0 1 Idle line was detected. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 Receive data register empty. #0 1 Receive data register full. #1 TC Transmission Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 Transmit data register (buffer) full. #0 1 Transmit data register (buffer) empty. #1 S2 UART Status Register 2 0x5 8 read-write 0 0xFF RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break detection is disabled. #0 1 Break detection is enabled (Break character is detected at length 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1)). #1 BRK13 Break Character Generation Length 2 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). #1 RWUID Receive Wake Up Idle Detect 3 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 RESERVED no description available 5 1 read-only RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 C3 UART Control Register 3 0x6 8 read-write 0 0xFF PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupts disabled; use polling). #0 1 Hardware interrupt requested when FE is set. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupts disabled; use polling). #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 3 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 TXINV Transmit Data Inversion 4 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 TXDIR TxD Pin Direction in Single-Wire Mode 5 1 read-write 0 TxD pin is an input in single-wire mode. #0 1 TxD pin is an output in single-wire mode. #1 T8 Ninth Data Bit for Transmitter 6 1 read-write R8 Ninth Data Bit for Receiver 7 1 read-only D UART Data Register 0x7 8 read-write 0 0xFF R0T0 no description available 0 1 read-write R1T1 no description available 1 1 read-write R2T2 no description available 2 1 read-write R3T3 no description available 3 1 read-write R4T4 no description available 4 1 read-write R5T5 no description available 5 1 read-write R6T6 no description available 6 1 read-write R7T7 no description available 7 1 read-write ACMP0 Analog comparator ACMP ACMP0_ 0x40073000 0 0x4 registers INT_ACMP0 16 CS ACMP Control and Status Register 0 8 read-write 0 0xFF ACMOD ACMP MOD 0 2 read-write 00 ACMP interrupt on output falling edge. #00 01 ACMP interrupt on output rising edge. #01 10 ACMP interrupt on output falling edge. #10 11 ACMP interrupt on output falling or rising edge. #11 ACOPE ACMP Output Pin Enable 2 1 read-write 0 ACMP output cannot be placed onto external pin. #0 1 ACMP output can be placed onto external pin. #1 ACO ACMP Output 3 1 read-only ACIE ACMP Interrupt Enable 4 1 read-write 0 Disable the ACMP Interrupt. #0 1 Enable the ACMP Interrupt. #1 ACF ACMP Interrupt Flag Bit 5 1 read-write HYST Analog Comparator Hysterisis Selection 6 1 read-write 0 20 mV. #0 1 30 mV. #1 ACE Analog Comparator Enable 7 1 read-write 0 The ACMP is disabled. #0 1 The ACMP is enabled. #1 C0 ACMP Control Register 0 0x1 8 read-write 0 0xFF ACNSEL ACMP Negative Input Select 0 2 read-write 00 External reference 0 #00 01 External reference 1 #01 10 External reference 2 #10 11 DAC output #11 RESERVED no description available 2 2 read-only ACPSEL ACMP Positive Input Select 4 2 read-write 00 External reference 0 #00 01 External reference 1 #01 10 External reference 2 #10 11 DAC output #11 RESERVED no description available 6 2 read-only C1 ACMP Control Register 1 0x2 8 read-write 0 0xFF DACVAL DAC Output Level Selection 0 6 read-write DACREF DAC Reference Select 6 1 read-write 0 The DAC selects Bandgap as the reference. #0 1 The DAC selects VDDA as the reference. #1 DACEN DAC Enable 7 1 read-write 0 The DAC is disabled. #0 1 The DAC is enabled. #1 C2 ACMP Control Register 2 0x3 8 read-write 0 0xFF ACIPE ACMP Input Pin Enable 0 3 read-write 0 The corresponding external analog input is not allowed. #0 1 The corresponding external analog input is allowed. #1 RESERVED no description available 3 5 read-only ACMP1 Analog comparator ACMP ACMP1_ 0x40074000 0 0x4 registers INT_ACMP1 21 CS ACMP Control and Status Register 0 8 read-write 0 0xFF ACMOD ACMP MOD 0 2 read-write 00 ACMP interrupt on output falling edge. #00 01 ACMP interrupt on output rising edge. #01 10 ACMP interrupt on output falling edge. #10 11 ACMP interrupt on output falling or rising edge. #11 ACOPE ACMP Output Pin Enable 2 1 read-write 0 ACMP output cannot be placed onto external pin. #0 1 ACMP output can be placed onto external pin. #1 ACO ACMP Output 3 1 read-only ACIE ACMP Interrupt Enable 4 1 read-write 0 Disable the ACMP Interrupt. #0 1 Enable the ACMP Interrupt. #1 ACF ACMP Interrupt Flag Bit 5 1 read-write HYST Analog Comparator Hysterisis Selection 6 1 read-write 0 20 mV. #0 1 30 mV. #1 ACE Analog Comparator Enable 7 1 read-write 0 The ACMP is disabled. #0 1 The ACMP is enabled. #1 C0 ACMP Control Register 0 0x1 8 read-write 0 0xFF ACNSEL ACMP Negative Input Select 0 2 read-write 00 External reference 0 #00 01 External reference 1 #01 10 External reference 2 #10 11 DAC output #11 RESERVED no description available 2 2 read-only ACPSEL ACMP Positive Input Select 4 2 read-write 00 External reference 0 #00 01 External reference 1 #01 10 External reference 2 #10 11 DAC output #11 RESERVED no description available 6 2 read-only C1 ACMP Control Register 1 0x2 8 read-write 0 0xFF DACVAL DAC Output Level Selection 0 6 read-write DACREF DAC Reference Select 6 1 read-write 0 The DAC selects Bandgap as the reference. #0 1 The DAC selects VDDA as the reference. #1 DACEN DAC Enable 7 1 read-write 0 The DAC is disabled. #0 1 The DAC is enabled. #1 C2 ACMP Control Register 2 0x3 8 read-write 0 0xFF ACIPE ACMP Input Pin Enable 0 3 read-write 0 The corresponding external analog input is not allowed. #0 1 The corresponding external analog input is allowed. #1 RESERVED no description available 3 5 read-only SPI0 Serial Peripheral Interface SPI SPI0_ 0x40076000 0 0x8 registers INT_SPI0 10 C1 SPI Control Register 1 0 8 read-write 0x4 0xFF LSBFE LSB First (shifter direction) 0 1 read-write 0 SPI serial data transfers start with the most significant bit. #0 1 SPI serial data transfers start with the least significant bit. #1 SSOE Slave Select Output Enable 1 1 read-write 0 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. #0 1 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. #1 CPHA Clock Phase 2 1 read-write 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer. #0 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer. #1 CPOL Clock Polarity 3 1 read-write 0 Active-high SPI clock (idles low) #0 1 Active-low SPI clock (idles high) #1 MSTR Master/Slave Mode Select 4 1 read-write 0 SPI module configured as a slave SPI device #0 1 SPI module configured as a master SPI device #1 SPTIE SPI Transmit Interrupt Enable 5 1 read-write 0 Interrupts from SPTEF inhibited (use polling) #0 1 When SPTEF is 1, hardware interrupt requested #1 SPE SPI System Enable 6 1 read-write 0 SPI system inactive #0 1 SPI system enabled #1 SPIE SPI Interrupt Enable: for SPRF and MODF 7 1 read-write 0 Interrupts from SPRF and MODF are inhibited-use polling #0 1 Request a hardware interrupt when SPRF or MODF is 1 #1 C2 SPI Control Register 2 0x1 8 read-write 0 0xFF SPC0 SPI Pin Control 0 0 1 read-write 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. #0 1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. #1 SPISWAI SPI Stop in Wait Mode 1 1 read-write 0 SPI clocks continue to operate in Wait mode. #0 1 SPI clocks stop when the MCU enters Wait mode. #1 RESERVED no description available 2 1 read-only BIDIROE Bidirectional Mode Output Enable 3 1 read-write 0 Output driver disabled so SPI data I/O pin acts as an input #0 1 SPI I/O pin enabled as an output #1 MODFEN Master Mode-Fault Function Enable 4 1 read-write 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI #0 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output #1 RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only SPMIE SPI Match Interrupt Enable 7 1 read-write 0 Interrupts from SPMF inhibited (use polling) #0 1 When SPMF is 1, requests a hardware interrupt #1 BR SPI Baud Rate Register 0x2 8 read-write 0 0xFF SPR SPI Baud Rate Divisor 0 4 read-write 0000 Baud rate divisor is 2. #0000 0001 Baud rate divisor is 4. #0001 0010 Baud rate divisor is 8. #0010 0011 Baud rate divisor is 16. #0011 0100 Baud rate divisor is 32. #0100 0101 Baud rate divisor is 64. #0101 0110 Baud rate divisor is 128. #0110 0111 Baud rate divisor is 256. #0111 1000 Baud rate divisor is 512. #1000 SPPR SPI Baud Rate Prescale Divisor 4 3 read-write 000 Baud rate prescaler divisor is 1. #000 001 Baud rate prescaler divisor is 2. #001 010 Baud rate prescaler divisor is 3. #010 011 Baud rate prescaler divisor is 4. #011 100 Baud rate prescaler divisor is 5. #100 101 Baud rate prescaler divisor is 6. #101 110 Baud rate prescaler divisor is 7. #110 111 Baud rate prescaler divisor is 8. #111 RESERVED no description available 7 1 read-only S SPI Status Register 0x3 8 read-only 0x20 0xFF RESERVED no description available 0 4 read-only MODF Master Mode Fault Flag 4 1 read-only 0 No mode fault error #0 1 Mode fault error detected #1 SPTEF SPI Transmit Buffer Empty Flag 5 1 read-only 0 SPI transmit buffer not empty #0 1 SPI transmit buffer empty #1 SPMF SPI Match Flag 6 1 read-only 0 Value in the receive data buffer does not match the value in the M register #0 1 Value in the receive data buffer matches the value in the M register #1 SPRF SPI Read Buffer Full Flag 7 1 read-only 0 No data available in the receive data buffer #0 1 Data available in the receive data buffer #1 D SPI Data Register 0x5 8 read-write 0 0xFF Bits Data (low byte) 0 8 read-write M SPI Match Register 0x7 8 read-write 0 0xFF Bits Hardware compare value (low byte) 0 8 read-write SPI1 Serial Peripheral Interface SPI SPI1_ 0x40077000 0 0x8 registers INT_SPI1 11 C1 SPI Control Register 1 0 8 read-write 0x4 0xFF LSBFE LSB First (shifter direction) 0 1 read-write 0 SPI serial data transfers start with the most significant bit. #0 1 SPI serial data transfers start with the least significant bit. #1 SSOE Slave Select Output Enable 1 1 read-write 0 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. #0 1 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. #1 CPHA Clock Phase 2 1 read-write 0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer. #0 1 First edge on SPSCK occurs at the start of the first cycle of a data transfer. #1 CPOL Clock Polarity 3 1 read-write 0 Active-high SPI clock (idles low) #0 1 Active-low SPI clock (idles high) #1 MSTR Master/Slave Mode Select 4 1 read-write 0 SPI module configured as a slave SPI device #0 1 SPI module configured as a master SPI device #1 SPTIE SPI Transmit Interrupt Enable 5 1 read-write 0 Interrupts from SPTEF inhibited (use polling) #0 1 When SPTEF is 1, hardware interrupt requested #1 SPE SPI System Enable 6 1 read-write 0 SPI system inactive #0 1 SPI system enabled #1 SPIE SPI Interrupt Enable: for SPRF and MODF 7 1 read-write 0 Interrupts from SPRF and MODF are inhibited-use polling #0 1 Request a hardware interrupt when SPRF or MODF is 1 #1 C2 SPI Control Register 2 0x1 8 read-write 0 0xFF SPC0 SPI Pin Control 0 0 1 read-write 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. #0 1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. #1 SPISWAI SPI Stop in Wait Mode 1 1 read-write 0 SPI clocks continue to operate in Wait mode. #0 1 SPI clocks stop when the MCU enters Wait mode. #1 RESERVED no description available 2 1 read-only BIDIROE Bidirectional Mode Output Enable 3 1 read-write 0 Output driver disabled so SPI data I/O pin acts as an input #0 1 SPI I/O pin enabled as an output #1 MODFEN Master Mode-Fault Function Enable 4 1 read-write 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI #0 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output #1 RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only SPMIE SPI Match Interrupt Enable 7 1 read-write 0 Interrupts from SPMF inhibited (use polling) #0 1 When SPMF is 1, requests a hardware interrupt #1 BR SPI Baud Rate Register 0x2 8 read-write 0 0xFF SPR SPI Baud Rate Divisor 0 4 read-write 0000 Baud rate divisor is 2. #0000 0001 Baud rate divisor is 4. #0001 0010 Baud rate divisor is 8. #0010 0011 Baud rate divisor is 16. #0011 0100 Baud rate divisor is 32. #0100 0101 Baud rate divisor is 64. #0101 0110 Baud rate divisor is 128. #0110 0111 Baud rate divisor is 256. #0111 1000 Baud rate divisor is 512. #1000 SPPR SPI Baud Rate Prescale Divisor 4 3 read-write 000 Baud rate prescaler divisor is 1. #000 001 Baud rate prescaler divisor is 2. #001 010 Baud rate prescaler divisor is 3. #010 011 Baud rate prescaler divisor is 4. #011 100 Baud rate prescaler divisor is 5. #100 101 Baud rate prescaler divisor is 6. #101 110 Baud rate prescaler divisor is 7. #110 111 Baud rate prescaler divisor is 8. #111 RESERVED no description available 7 1 read-only S SPI Status Register 0x3 8 read-only 0x20 0xFF RESERVED no description available 0 4 read-only MODF Master Mode Fault Flag 4 1 read-only 0 No mode fault error #0 1 Mode fault error detected #1 SPTEF SPI Transmit Buffer Empty Flag 5 1 read-only 0 SPI transmit buffer not empty #0 1 SPI transmit buffer empty #1 SPMF SPI Match Flag 6 1 read-only 0 Value in the receive data buffer does not match the value in the M register #0 1 Value in the receive data buffer matches the value in the M register #1 SPRF SPI Read Buffer Full Flag 7 1 read-only 0 No data available in the receive data buffer #0 1 Data available in the receive data buffer #1 D SPI Data Register 0x5 8 read-write 0 0xFF Bits Data (low byte) 0 8 read-write M SPI Match Register 0x7 8 read-write 0 0xFF Bits Hardware compare value (low byte) 0 8 read-write KBI0 Keyboard interrupts KBI KBI0_ 0x40079000 0 0x3 registers INT_KBI0 24 SC KBI Status and Control Register 0 8 read-write 0 0xFF KBMOD KBI Detection Mode 0 1 read-write 0 Keyboard detects edges only. #0 1 Keyboard detects both edges and levels. #1 KBIE KBI Interrupt Enable 1 1 read-write 0 KBI interrupt not enabled. #0 1 KBI interrupt enabled. #1 KBACK KBI Acknowledge 2 1 write-only KBF KBI Interrupt Flag 3 1 read-only 0 KBI interrupt request not detected. #0 1 KBI interrupt request detected. #1 RESERVED no description available 4 4 read-only PE KBIx Pin Enable Register 0x1 8 read-write 0 0xFF KBIPE KBI Pin Enables 0 8 read-write 0 Pin is not enabled as KBI interrupt. #0 1 Pin is enabled as KBI interrupt. #1 ES KBIx Edge Select Register 0x2 8 read-write 0 0xFF KBEDG KBI Edge Selects 0 8 read-write 0 Falling edge/low level. #0 1 Rising edge/high level. #1 KBI1 Keyboard interrupts KBI KBI1_ 0x4007A000 0 0x3 registers INT_KBI1 25 SC KBI Status and Control Register 0 8 read-write 0 0xFF KBMOD KBI Detection Mode 0 1 read-write 0 Keyboard detects edges only. #0 1 Keyboard detects both edges and levels. #1 KBIE KBI Interrupt Enable 1 1 read-write 0 KBI interrupt not enabled. #0 1 KBI interrupt enabled. #1 KBACK KBI Acknowledge 2 1 write-only KBF KBI Interrupt Flag 3 1 read-only 0 KBI interrupt request not detected. #0 1 KBI interrupt request detected. #1 RESERVED no description available 4 4 read-only PE KBIx Pin Enable Register 0x1 8 read-write 0 0xFF KBIPE KBI Pin Enables 0 8 read-write 0 Pin is not enabled as KBI interrupt. #0 1 Pin is enabled as KBI interrupt. #1 ES KBIx Edge Select Register 0x2 8 read-write 0 0xFF KBEDG KBI Edge Selects 0 8 read-write 0 Falling edge/low level. #0 1 Rising edge/high level. #1 PMC Power management PMC_ 0x4007D000 0 0x2 registers INT_LVD_LVW 6 SPMSC1 System Power Management Status and Control 1 Register 0 8 read-write 0x1C 0xFF BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer is disabled. #0 1 Bandgap buffer is enabled. #1 RESERVED no description available 1 1 write-only LVDE Low-Voltage Detect Enable 2 1 read-write 0 LVD logic is disabled. #0 1 LVD logic is enabled. #1 LVDSE Low-Voltage Detect Stop Enable 3 1 read-write 0 Low-voltage detect is disabled during Stop mode. #0 1 Low-voltage detect is enabled during Stop mode. #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVD events do not generate hardware resets. #0 1 Forces an MCU reset when an enabled low-voltage detect event occurs. #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt is disabled (use polling). #0 1 Requests a hardware interrupt when LVWF = 1. #1 LVWACK Low-Voltage Warning Acknowledge 6 1 read-write oneToClear LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning is not present. #0 1 Low-voltage warning is present or was present. #1 SPMSC2 System Power Management Status and Control 2 Register 0x1 8 read-write 0 0xFF RESERVED no description available 0 4 read-only LVWV Low-Voltage Warning Voltage Select 4 2 read-write 00 Low trip point is selected (VLVW = VLVW1). #00 01 Middle 1 trip point is selected (VLVW = VLVW2). #01 10 Middle 2 trip point is selected (VLVW = VLVW3). #10 11 High trip point is selected (VLVW = VLVW4). #11 LVDV Low-Voltage Detect Voltage Select 6 1 read-write 0 Low trip point is selected (VLVD = VLVDL). #0 1 High trip point is selected (VLVD = VLVDH). #1 RESERVED no description available 7 1 read-only GPIOA General Purpose Input/Output GPIO GPIOA_ 0x400FF000 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PIDR Port Input Disable Register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF PID Port Input Disable 0 32 read-write 0 Pin is configured for General Purpose Input, provided the pin is configured for any digital function. #0 1 Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero. #1 GPIOB General Purpose Input/Output GPIO GPIOB_ 0x400FF040 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PIDR Port Input Disable Register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF PID Port Input Disable 0 32 read-write 0 Pin is configured for General Purpose Input, provided the pin is configured for any digital function. #0 1 Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero. #1 ROM System ROM ROM_ 0xF0002000 0 0x1000 registers ENTRY Entry 0 32 read-only 0 0 ENTRY ENTRY 0 32 read-only TABLEMARK End of Table Marker Register 0x4 32 read-only 0 0xFFFFFFFF MARK no description available 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only 0x1 0xFFFFFFFF SYSACCESS no description available 0 32 read-only 8 0x4 4,5,6,7,0,1,2,3 PERIPHID%s Peripheral ID Register 0xFD0 32 read-only 0 0 PERIPHID no description available 0 32 read-only 4 0x4 0,1,2,3 COMPID%s Component ID Register 0xFF0 32 read-only 0 0 COMPID Component ID 0 32 read-only MCM Core Platform Miscellaneous Control Module MCM_ 0xF0003000 0x8 0x8 registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 RESERVED no description available 8 8 read-only PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x1 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 RESERVED no description available 8 8 read-only PLACR Platform Control Register 0xC 32 read-write 0x800 0xFFFFFFFF RESERVED no description available 0 10 read-only CFCC Clear Flash Controller Cache 10 1 write-only DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 RESERVED no description available 17 15 read-only FGPIOA General Purpose Input/Output FGPIO FGPIOA_ 0xF8000000 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PIDR Port Input Disable Register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF PID Port Input Disable 0 32 read-write 0 Pin is configured for General Purpose Input, provided the pin is configured for any digital function. #0 1 Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero. #1 FGPIOB General Purpose Input/Output FGPIO FGPIOB_ 0xF8000040 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only 0 0xFFFFFFFF PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PCOR Port Clear Output Register 0x8 32 write-only 0 0xFFFFFFFF PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTOR Port Toggle Output Register 0xC 32 write-only 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PIDR Port Input Disable Register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF PID Port Input Disable 0 32 read-write 0 Pin is configured for General Purpose Input, provided the pin is configured for any digital function. #0 1 Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero. #1