#![doc = "Peripheral access API for AIR001XX_DFP microcontrollers (generated using svd2rust v0.29.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.29.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] #![deny(no_mangle_generic_items)] #![deny(non_shorthand_field_patterns)] #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] #![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] #![deny(unused_parens)] #![deny(while_true)] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![no_std] use core::marker::PhantomData; use core::ops::Deref; #[doc = r"Number available in the NVIC for configuring priority"] pub const NVIC_PRIO_BITS: u8 = 4; #[cfg(feature = "rt")] pub use self::Interrupt as interrupt; pub use cortex_m::peripheral::Peripherals as CorePeripherals; pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; #[cfg(feature = "rt")] pub use cortex_m_rt::interrupt; #[allow(unused_imports)] use generic::*; #[doc = "Common register and bit access and modify traits"] pub mod generic; #[cfg(feature = "rt")] extern "C" { fn WWDG(); fn PVD(); fn RTC(); fn FLASH(); fn RCC(); fn EXTI0_1(); fn EXTI2_3(); fn EXTI4_15(); fn DMA_CHANNEL1(); fn DMA_CHANNEL2_3(); fn ADC_COMP(); fn TIM1_BRK_UP_TRG_COM(); fn TIM1_CC(); fn TIM3(); fn TIM14(); fn TIM16(); fn TIM17(); fn I2C1(); fn SPI1(); fn SPI2(); fn USART1(); fn USART2(); fn LED(); } #[doc(hidden)] pub union Vector { _handler: unsafe extern "C" fn(), _reserved: u32, } #[cfg(feature = "rt")] #[doc(hidden)] #[link_section = ".vector_table.interrupts"] #[no_mangle] pub static __INTERRUPTS: [Vector; 31] = [ Vector { _handler: WWDG }, Vector { _handler: PVD }, Vector { _handler: RTC }, Vector { _handler: FLASH }, Vector { _handler: RCC }, Vector { _handler: EXTI0_1 }, Vector { _handler: EXTI2_3 }, Vector { _handler: EXTI4_15 }, Vector { _reserved: 0 }, Vector { _handler: DMA_CHANNEL1, }, Vector { _handler: DMA_CHANNEL2_3, }, Vector { _reserved: 0 }, Vector { _handler: ADC_COMP }, Vector { _handler: TIM1_BRK_UP_TRG_COM, }, Vector { _handler: TIM1_CC }, Vector { _reserved: 0 }, Vector { _handler: TIM3 }, Vector { _reserved: 0 }, Vector { _reserved: 0 }, Vector { _handler: TIM14 }, Vector { _reserved: 0 }, Vector { _handler: TIM16 }, Vector { _handler: TIM17 }, Vector { _handler: I2C1 }, Vector { _reserved: 0 }, Vector { _handler: SPI1 }, Vector { _handler: SPI2 }, Vector { _handler: USART1 }, Vector { _handler: USART2 }, Vector { _reserved: 0 }, Vector { _handler: LED }, ]; #[doc = r"Enumeration of all the interrupts."] #[derive(Copy, Clone, Debug, PartialEq, Eq)] #[repr(u16)] pub enum Interrupt { #[doc = "0 - Window WatchDog Interrupt"] WWDG = 0, #[doc = "1 - PVD Interrupt through EXTI Lines 16"] PVD = 1, #[doc = "2 - RTC Interrupt through EXTI Lines 19"] RTC = 2, #[doc = "3 - FLASH global Interrupt"] FLASH = 3, #[doc = "4 - RCC global Interrupt"] RCC = 4, #[doc = "5 - EXTI Line 0 and 1 Interrupt"] EXTI0_1 = 5, #[doc = "6 - EXTI Line 2 and 3 Interrupt"] EXTI2_3 = 6, #[doc = "7 - EXTI Line 4 to 15 Interrupt"] EXTI4_15 = 7, #[doc = "9 - DMA Channel 1 Interrupt"] DMA_CHANNEL1 = 9, #[doc = "10 - DMA Channel 2 and Channel 3 Interrupt"] DMA_CHANNEL2_3 = 10, #[doc = "12 - ADC and COMP Interrupt through EXTI Lines 17 and 18"] ADC_COMP = 12, #[doc = "13 - TIM1 Break, Update, Trigger and Commutation Interrupt"] TIM1_BRK_UP_TRG_COM = 13, #[doc = "14 - TIM1 Capture Compare Interrupt"] TIM1_CC = 14, #[doc = "16 - TIM3 global Interrupt"] TIM3 = 16, #[doc = "19 - TIM14 global Interrupt"] TIM14 = 19, #[doc = "21 - TIM16 global Interrupt"] TIM16 = 21, #[doc = "22 - TIM17 global Interrupt"] TIM17 = 22, #[doc = "23 - I2C1 global Interrupt"] I2C1 = 23, #[doc = "25 - SPI1 global Interrupt"] SPI1 = 25, #[doc = "26 - SPI2 global Interrupt"] SPI2 = 26, #[doc = "27 - USART1 global Interrupt"] USART1 = 27, #[doc = "28 - USART2 global Interrupt"] USART2 = 28, #[doc = "30 - LED global Interrupt"] LED = 30, } unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { #[inline(always)] fn number(self) -> u16 { self as u16 } } #[doc = "Analog to Digital Converter"] pub struct ADC { _marker: PhantomData<*const ()>, } unsafe impl Send for ADC {} impl ADC { #[doc = r"Pointer to the register block"] pub const PTR: *const adc::RegisterBlock = 0x4001_2400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const adc::RegisterBlock { Self::PTR } } impl Deref for ADC { type Target = adc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for ADC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("ADC").finish() } } #[doc = "Analog to Digital Converter"] pub mod adc { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - ADC interrupt and status register"] pub isr: ISR, #[doc = "0x04 - ADC interrupt enable register"] pub ier: IER, #[doc = "0x08 - ADC control register"] pub cr: CR, #[doc = "0x0c - ADC configuration register 1"] pub cfgr1: CFGR1, #[doc = "0x10 - ADC configuration register 2"] pub cfgr2: CFGR2, #[doc = "0x14 - ADC sampling time register"] pub smpr: SMPR, _reserved6: [u8; 0x08], #[doc = "0x20 - ADC analog watchdog 1 threshold register"] pub tr: TR, _reserved7: [u8; 0x04], #[doc = "0x28 - ADC group regular sequencer register"] pub chselr: CHSELR, _reserved8: [u8; 0x14], #[doc = "0x40 - ADC group regular data register"] pub dr: DR, #[doc = "0x44 - ADC calibration configuration and status register"] pub ccsr: CCSR, #[doc = "0x48 - ADC calibration result register 1"] pub calrr1: CALRR1, #[doc = "0x4c - ADC calibration result register 2"] pub calrr2: CALRR2, #[doc = "0x50 - ADC calibration factor input register 1"] pub calfir1: CALFIR1, #[doc = "0x54 - ADC calibration factor input register 2"] pub calfir2: CALFIR2, _reserved14: [u8; 0x02b0], #[doc = "0x308 - ADC common configuration register"] pub ccr: CCR, } #[doc = "ISR (rw) register accessor: an alias for `Reg`"] pub type ISR = crate::Reg; #[doc = "ADC interrupt and status register"] pub mod isr { #[doc = "Register `ISR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ISR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EOSMP` reader - ADC group regular end of sampling flag"] pub type EOSMP_R = crate::BitReader; #[doc = "Field `EOSMP` writer - ADC group regular end of sampling flag"] pub type EOSMP_W<'a, const O: u8> = crate::BitWriter<'a, ISR_SPEC, O>; #[doc = "Field `EOC` reader - ADC group regular end of unitary conversion flag"] pub type EOC_R = crate::BitReader; #[doc = "Field `EOC` writer - ADC group regular end of unitary conversion flag"] pub type EOC_W<'a, const O: u8> = crate::BitWriter<'a, ISR_SPEC, O>; #[doc = "Field `EOSEQ` reader - ADC group regular end of sequence conversions flag"] pub type EOSEQ_R = crate::BitReader; #[doc = "Field `EOSEQ` writer - ADC group regular end of sequence conversions flag"] pub type EOSEQ_W<'a, const O: u8> = crate::BitWriter<'a, ISR_SPEC, O>; #[doc = "Field `OVR` reader - ADC group regular overrun flag"] pub type OVR_R = crate::BitReader; #[doc = "Field `OVR` writer - ADC group regular overrun flag"] pub type OVR_W<'a, const O: u8> = crate::BitWriter<'a, ISR_SPEC, O>; #[doc = "Field `AWD` reader - ADC analog watchdog flag"] pub type AWD_R = crate::BitReader; #[doc = "Field `AWD` writer - ADC analog watchdog flag"] pub type AWD_W<'a, const O: u8> = crate::BitWriter<'a, ISR_SPEC, O>; impl R { #[doc = "Bit 1 - ADC group regular end of sampling flag"] #[inline(always)] pub fn eosmp(&self) -> EOSMP_R { EOSMP_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - ADC group regular end of unitary conversion flag"] #[inline(always)] pub fn eoc(&self) -> EOC_R { EOC_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - ADC group regular end of sequence conversions flag"] #[inline(always)] pub fn eoseq(&self) -> EOSEQ_R { EOSEQ_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - ADC group regular overrun flag"] #[inline(always)] pub fn ovr(&self) -> OVR_R { OVR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 7 - ADC analog watchdog flag"] #[inline(always)] pub fn awd(&self) -> AWD_R { AWD_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 1 - ADC group regular end of sampling flag"] #[inline(always)] #[must_use] pub fn eosmp(&mut self) -> EOSMP_W<1> { EOSMP_W::new(self) } #[doc = "Bit 2 - ADC group regular end of unitary conversion flag"] #[inline(always)] #[must_use] pub fn eoc(&mut self) -> EOC_W<2> { EOC_W::new(self) } #[doc = "Bit 3 - ADC group regular end of sequence conversions flag"] #[inline(always)] #[must_use] pub fn eoseq(&mut self) -> EOSEQ_W<3> { EOSEQ_W::new(self) } #[doc = "Bit 4 - ADC group regular overrun flag"] #[inline(always)] #[must_use] pub fn ovr(&mut self) -> OVR_W<4> { OVR_W::new(self) } #[doc = "Bit 7 - ADC analog watchdog flag"] #[inline(always)] #[must_use] pub fn awd(&mut self) -> AWD_W<7> { AWD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC interrupt and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [isr::R](R) reader structure"] impl crate::Readable for ISR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [isr::W](W) writer structure"] impl crate::Writable for ISR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IER (rw) register accessor: an alias for `Reg`"] pub type IER = crate::Reg; #[doc = "ADC interrupt enable register"] pub mod ier { #[doc = "Register `IER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EOSMPIE` reader - ADC group regular end of sampling interrupt"] pub type EOSMPIE_R = crate::BitReader; #[doc = "Field `EOSMPIE` writer - ADC group regular end of sampling interrupt"] pub type EOSMPIE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; #[doc = "Field `EOCIE` reader - ADC group regular end of unitary conversion interrupt"] pub type EOCIE_R = crate::BitReader; #[doc = "Field `EOCIE` writer - ADC group regular end of unitary conversion interrupt"] pub type EOCIE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; #[doc = "Field `EOSEQIE` reader - ADC group regular end of sequence conversions interrupt"] pub type EOSEQIE_R = crate::BitReader; #[doc = "Field `EOSEQIE` writer - ADC group regular end of sequence conversions interrupt"] pub type EOSEQIE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; #[doc = "Field `OVRIE` reader - ADC group regular overrun interrupt"] pub type OVRIE_R = crate::BitReader; #[doc = "Field `OVRIE` writer - ADC group regular overrun interrupt"] pub type OVRIE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; #[doc = "Field `AWDIE` reader - ADC analog watchdog interrupt"] pub type AWDIE_R = crate::BitReader; #[doc = "Field `AWDIE` writer - ADC analog watchdog interrupt"] pub type AWDIE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; impl R { #[doc = "Bit 1 - ADC group regular end of sampling interrupt"] #[inline(always)] pub fn eosmpie(&self) -> EOSMPIE_R { EOSMPIE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - ADC group regular end of unitary conversion interrupt"] #[inline(always)] pub fn eocie(&self) -> EOCIE_R { EOCIE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - ADC group regular end of sequence conversions interrupt"] #[inline(always)] pub fn eoseqie(&self) -> EOSEQIE_R { EOSEQIE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - ADC group regular overrun interrupt"] #[inline(always)] pub fn ovrie(&self) -> OVRIE_R { OVRIE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 7 - ADC analog watchdog interrupt"] #[inline(always)] pub fn awdie(&self) -> AWDIE_R { AWDIE_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 1 - ADC group regular end of sampling interrupt"] #[inline(always)] #[must_use] pub fn eosmpie(&mut self) -> EOSMPIE_W<1> { EOSMPIE_W::new(self) } #[doc = "Bit 2 - ADC group regular end of unitary conversion interrupt"] #[inline(always)] #[must_use] pub fn eocie(&mut self) -> EOCIE_W<2> { EOCIE_W::new(self) } #[doc = "Bit 3 - ADC group regular end of sequence conversions interrupt"] #[inline(always)] #[must_use] pub fn eoseqie(&mut self) -> EOSEQIE_W<3> { EOSEQIE_W::new(self) } #[doc = "Bit 4 - ADC group regular overrun interrupt"] #[inline(always)] #[must_use] pub fn ovrie(&mut self) -> OVRIE_W<4> { OVRIE_W::new(self) } #[doc = "Bit 7 - ADC analog watchdog interrupt"] #[inline(always)] #[must_use] pub fn awdie(&mut self) -> AWDIE_W<7> { AWDIE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ier::R](R) reader structure"] impl crate::Readable for IER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] impl crate::Writable for IER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IER to value 0"] impl crate::Resettable for IER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "ADC control register"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ADEN` reader - ADC enable"] pub type ADEN_R = crate::BitReader; #[doc = "Field `ADEN` writer - ADC enable"] pub type ADEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `ADSTART` reader - ADC group regular conversion start"] pub type ADSTART_R = crate::BitReader; #[doc = "Field `ADSTART` writer - ADC group regular conversion start"] pub type ADSTART_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `ADSTP` reader - ADC group regular conversion stop"] pub type ADSTP_R = crate::BitReader; #[doc = "Field `ADSTP` writer - ADC group regular conversion stop"] pub type ADSTP_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `ADCAL` reader - ADC group regular conversion calibration"] pub type ADCAL_R = crate::BitReader; #[doc = "Field `ADCAL` writer - ADC group regular conversion calibration"] pub type ADCAL_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl R { #[doc = "Bit 0 - ADC enable"] #[inline(always)] pub fn aden(&self) -> ADEN_R { ADEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 2 - ADC group regular conversion start"] #[inline(always)] pub fn adstart(&self) -> ADSTART_R { ADSTART_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 4 - ADC group regular conversion stop"] #[inline(always)] pub fn adstp(&self) -> ADSTP_R { ADSTP_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 31 - ADC group regular conversion calibration"] #[inline(always)] pub fn adcal(&self) -> ADCAL_R { ADCAL_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 0 - ADC enable"] #[inline(always)] #[must_use] pub fn aden(&mut self) -> ADEN_W<0> { ADEN_W::new(self) } #[doc = "Bit 2 - ADC group regular conversion start"] #[inline(always)] #[must_use] pub fn adstart(&mut self) -> ADSTART_W<2> { ADSTART_W::new(self) } #[doc = "Bit 4 - ADC group regular conversion stop"] #[inline(always)] #[must_use] pub fn adstp(&mut self) -> ADSTP_W<4> { ADSTP_W::new(self) } #[doc = "Bit 31 - ADC group regular conversion calibration"] #[inline(always)] #[must_use] pub fn adcal(&mut self) -> ADCAL_W<31> { ADCAL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CFGR1 (rw) register accessor: an alias for `Reg`"] pub type CFGR1 = crate::Reg; #[doc = "ADC configuration register 1"] pub mod cfgr1 { #[doc = "Register `CFGR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMAEN` reader - ADC DMA transfer enable"] pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - ADC DMA transfer enable"] pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `DMACFG` reader - ADC DMA transfer configuration"] pub type DMACFG_R = crate::BitReader; #[doc = "Field `DMACFG` writer - ADC DMA transfer configuration"] pub type DMACFG_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `SCANDIR` reader - Scan sequence direction"] pub type SCANDIR_R = crate::BitReader; #[doc = "Field `SCANDIR` writer - Scan sequence direction"] pub type SCANDIR_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `RESSEL` reader - ADC data resolution"] pub type RESSEL_R = crate::FieldReader; #[doc = "Field `RESSEL` writer - ADC data resolution"] pub type RESSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR1_SPEC, 2, O>; #[doc = "Field `ALIGN` reader - ADC data alignement"] pub type ALIGN_R = crate::BitReader; #[doc = "Field `ALIGN` writer - ADC data alignement"] pub type ALIGN_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `EXTSEL` reader - ADC group regular external trigger source"] pub type EXTSEL_R = crate::FieldReader; #[doc = "Field `EXTSEL` writer - ADC group regular external trigger source"] pub type EXTSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR1_SPEC, 3, O>; #[doc = "Field `EXTEN` reader - ADC group regular external trigger polarity"] pub type EXTEN_R = crate::FieldReader; #[doc = "Field `EXTEN` writer - ADC group regular external trigger polarity"] pub type EXTEN_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR1_SPEC, 2, O>; #[doc = "Field `OVRMOD` reader - ADC group regular overrun configuration"] pub type OVRMOD_R = crate::BitReader; #[doc = "Field `OVRMOD` writer - ADC group regular overrun configuration"] pub type OVRMOD_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `CONT` reader - ADC group regular continuous conversion mode"] pub type CONT_R = crate::BitReader; #[doc = "Field `CONT` writer - ADC group regular continuous conversion mode"] pub type CONT_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `WAIT` reader - Wait conversion mode"] pub type WAIT_R = crate::BitReader; #[doc = "Field `WAIT` writer - Wait conversion mode"] pub type WAIT_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `DISCEN` reader - ADC group regular sequencer discontinuous mode"] pub type DISCEN_R = crate::BitReader; #[doc = "Field `DISCEN` writer - ADC group regular sequencer discontinuous mode"] pub type DISCEN_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `AWDSGL` reader - ADC analog watchdog monitoring a single channel or all channels"] pub type AWDSGL_R = crate::BitReader; #[doc = "Field `AWDSGL` writer - ADC analog watchdog monitoring a single channel or all channels"] pub type AWDSGL_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `AWDEN` reader - ADC analog watchdog enable on scope ADC group regular"] pub type AWDEN_R = crate::BitReader; #[doc = "Field `AWDEN` writer - ADC analog watchdog enable on scope ADC group regular"] pub type AWDEN_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `AWDCH` reader - ADC analog watchdog monitored channel selection"] pub type AWDCH_R = crate::FieldReader; #[doc = "Field `AWDCH` writer - ADC analog watchdog monitored channel selection"] pub type AWDCH_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR1_SPEC, 4, O>; impl R { #[doc = "Bit 0 - ADC DMA transfer enable"] #[inline(always)] pub fn dmaen(&self) -> DMAEN_R { DMAEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - ADC DMA transfer configuration"] #[inline(always)] pub fn dmacfg(&self) -> DMACFG_R { DMACFG_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Scan sequence direction"] #[inline(always)] pub fn scandir(&self) -> SCANDIR_R { SCANDIR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bits 3:4 - ADC data resolution"] #[inline(always)] pub fn ressel(&self) -> RESSEL_R { RESSEL_R::new(((self.bits >> 3) & 3) as u8) } #[doc = "Bit 5 - ADC data alignement"] #[inline(always)] pub fn align(&self) -> ALIGN_R { ALIGN_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bits 6:8 - ADC group regular external trigger source"] #[inline(always)] pub fn extsel(&self) -> EXTSEL_R { EXTSEL_R::new(((self.bits >> 6) & 7) as u8) } #[doc = "Bits 10:11 - ADC group regular external trigger polarity"] #[inline(always)] pub fn exten(&self) -> EXTEN_R { EXTEN_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bit 12 - ADC group regular overrun configuration"] #[inline(always)] pub fn ovrmod(&self) -> OVRMOD_R { OVRMOD_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - ADC group regular continuous conversion mode"] #[inline(always)] pub fn cont(&self) -> CONT_R { CONT_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Wait conversion mode"] #[inline(always)] pub fn wait(&self) -> WAIT_R { WAIT_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 16 - ADC group regular sequencer discontinuous mode"] #[inline(always)] pub fn discen(&self) -> DISCEN_R { DISCEN_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 22 - ADC analog watchdog monitoring a single channel or all channels"] #[inline(always)] pub fn awdsgl(&self) -> AWDSGL_R { AWDSGL_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - ADC analog watchdog enable on scope ADC group regular"] #[inline(always)] pub fn awden(&self) -> AWDEN_R { AWDEN_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bits 26:29 - ADC analog watchdog monitored channel selection"] #[inline(always)] pub fn awdch(&self) -> AWDCH_R { AWDCH_R::new(((self.bits >> 26) & 0x0f) as u8) } } impl W { #[doc = "Bit 0 - ADC DMA transfer enable"] #[inline(always)] #[must_use] pub fn dmaen(&mut self) -> DMAEN_W<0> { DMAEN_W::new(self) } #[doc = "Bit 1 - ADC DMA transfer configuration"] #[inline(always)] #[must_use] pub fn dmacfg(&mut self) -> DMACFG_W<1> { DMACFG_W::new(self) } #[doc = "Bit 2 - Scan sequence direction"] #[inline(always)] #[must_use] pub fn scandir(&mut self) -> SCANDIR_W<2> { SCANDIR_W::new(self) } #[doc = "Bits 3:4 - ADC data resolution"] #[inline(always)] #[must_use] pub fn ressel(&mut self) -> RESSEL_W<3> { RESSEL_W::new(self) } #[doc = "Bit 5 - ADC data alignement"] #[inline(always)] #[must_use] pub fn align(&mut self) -> ALIGN_W<5> { ALIGN_W::new(self) } #[doc = "Bits 6:8 - ADC group regular external trigger source"] #[inline(always)] #[must_use] pub fn extsel(&mut self) -> EXTSEL_W<6> { EXTSEL_W::new(self) } #[doc = "Bits 10:11 - ADC group regular external trigger polarity"] #[inline(always)] #[must_use] pub fn exten(&mut self) -> EXTEN_W<10> { EXTEN_W::new(self) } #[doc = "Bit 12 - ADC group regular overrun configuration"] #[inline(always)] #[must_use] pub fn ovrmod(&mut self) -> OVRMOD_W<12> { OVRMOD_W::new(self) } #[doc = "Bit 13 - ADC group regular continuous conversion mode"] #[inline(always)] #[must_use] pub fn cont(&mut self) -> CONT_W<13> { CONT_W::new(self) } #[doc = "Bit 14 - Wait conversion mode"] #[inline(always)] #[must_use] pub fn wait(&mut self) -> WAIT_W<14> { WAIT_W::new(self) } #[doc = "Bit 16 - ADC group regular sequencer discontinuous mode"] #[inline(always)] #[must_use] pub fn discen(&mut self) -> DISCEN_W<16> { DISCEN_W::new(self) } #[doc = "Bit 22 - ADC analog watchdog monitoring a single channel or all channels"] #[inline(always)] #[must_use] pub fn awdsgl(&mut self) -> AWDSGL_W<22> { AWDSGL_W::new(self) } #[doc = "Bit 23 - ADC analog watchdog enable on scope ADC group regular"] #[inline(always)] #[must_use] pub fn awden(&mut self) -> AWDEN_W<23> { AWDEN_W::new(self) } #[doc = "Bits 26:29 - ADC analog watchdog monitored channel selection"] #[inline(always)] #[must_use] pub fn awdch(&mut self) -> AWDCH_W<26> { AWDCH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC configuration register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr1](index.html) module"] pub struct CFGR1_SPEC; impl crate::RegisterSpec for CFGR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr1::R](R) reader structure"] impl crate::Readable for CFGR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr1::W](W) writer structure"] impl crate::Writable for CFGR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR1 to value 0"] impl crate::Resettable for CFGR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CFGR2 (rw) register accessor: an alias for `Reg`"] pub type CFGR2 = crate::Reg; #[doc = "ADC configuration register 2"] pub mod cfgr2 { #[doc = "Register `CFGR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CKMODE` reader - ADC clock mode"] pub type CKMODE_R = crate::FieldReader; #[doc = "Field `CKMODE` writer - ADC clock mode"] pub type CKMODE_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR2_SPEC, 4, O>; impl R { #[doc = "Bits 28:31 - ADC clock mode"] #[inline(always)] pub fn ckmode(&self) -> CKMODE_R { CKMODE_R::new(((self.bits >> 28) & 0x0f) as u8) } } impl W { #[doc = "Bits 28:31 - ADC clock mode"] #[inline(always)] #[must_use] pub fn ckmode(&mut self) -> CKMODE_W<28> { CKMODE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC configuration register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"] pub struct CFGR2_SPEC; impl crate::RegisterSpec for CFGR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr2::R](R) reader structure"] impl crate::Readable for CFGR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"] impl crate::Writable for CFGR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR2 to value 0"] impl crate::Resettable for CFGR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SMPR (rw) register accessor: an alias for `Reg`"] pub type SMPR = crate::Reg; #[doc = "ADC sampling time register"] pub mod smpr { #[doc = "Register `SMPR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SMPR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SMP` reader - Sampling time selection"] pub type SMP_R = crate::FieldReader; #[doc = "Field `SMP` writer - Sampling time selection"] pub type SMP_W<'a, const O: u8> = crate::FieldWriter<'a, SMPR_SPEC, 3, O>; impl R { #[doc = "Bits 0:2 - Sampling time selection"] #[inline(always)] pub fn smp(&self) -> SMP_R { SMP_R::new((self.bits & 7) as u8) } } impl W { #[doc = "Bits 0:2 - Sampling time selection"] #[inline(always)] #[must_use] pub fn smp(&mut self) -> SMP_W<0> { SMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC sampling time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smpr](index.html) module"] pub struct SMPR_SPEC; impl crate::RegisterSpec for SMPR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [smpr::R](R) reader structure"] impl crate::Readable for SMPR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [smpr::W](W) writer structure"] impl crate::Writable for SMPR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SMPR to value 0"] impl crate::Resettable for SMPR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "TR (rw) register accessor: an alias for `Reg`"] pub type TR = crate::Reg; #[doc = "ADC analog watchdog 1 threshold register"] pub mod tr { #[doc = "Register `TR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LT` reader - ADC analog watchdog threshold low"] pub type LT_R = crate::FieldReader; #[doc = "Field `LT` writer - ADC analog watchdog threshold low"] pub type LT_W<'a, const O: u8> = crate::FieldWriter<'a, TR_SPEC, 12, O, u16>; #[doc = "Field `HT` reader - ADC analog watchdog threshold high"] pub type HT_R = crate::FieldReader; #[doc = "Field `HT` writer - ADC analog watchdog threshold high"] pub type HT_W<'a, const O: u8> = crate::FieldWriter<'a, TR_SPEC, 12, O, u16>; impl R { #[doc = "Bits 0:11 - ADC analog watchdog threshold low"] #[inline(always)] pub fn lt(&self) -> LT_R { LT_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bits 16:27 - ADC analog watchdog threshold high"] #[inline(always)] pub fn ht(&self) -> HT_R { HT_R::new(((self.bits >> 16) & 0x0fff) as u16) } } impl W { #[doc = "Bits 0:11 - ADC analog watchdog threshold low"] #[inline(always)] #[must_use] pub fn lt(&mut self) -> LT_W<0> { LT_W::new(self) } #[doc = "Bits 16:27 - ADC analog watchdog threshold high"] #[inline(always)] #[must_use] pub fn ht(&mut self) -> HT_W<16> { HT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC analog watchdog 1 threshold register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tr](index.html) module"] pub struct TR_SPEC; impl crate::RegisterSpec for TR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [tr::R](R) reader structure"] impl crate::Readable for TR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [tr::W](W) writer structure"] impl crate::Writable for TR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TR to value 0x0fff_0000"] impl crate::Resettable for TR_SPEC { const RESET_VALUE: Self::Ux = 0x0fff_0000; } } #[doc = "CHSELR (rw) register accessor: an alias for `Reg`"] pub type CHSELR = crate::Reg; #[doc = "ADC group regular sequencer register"] pub mod chselr { #[doc = "Register `CHSELR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CHSELR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CHSEL0` reader - Channel-0 selection"] pub type CHSEL0_R = crate::BitReader; #[doc = "Field `CHSEL0` writer - Channel-0 selection"] pub type CHSEL0_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL1` reader - Channel-1 selection"] pub type CHSEL1_R = crate::BitReader; #[doc = "Field `CHSEL1` writer - Channel-1 selection"] pub type CHSEL1_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL2` reader - Channel-2 selection"] pub type CHSEL2_R = crate::BitReader; #[doc = "Field `CHSEL2` writer - Channel-2 selection"] pub type CHSEL2_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL3` reader - Channel-3 selection"] pub type CHSEL3_R = crate::BitReader; #[doc = "Field `CHSEL3` writer - Channel-3 selection"] pub type CHSEL3_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL4` reader - Channel-4 selection"] pub type CHSEL4_R = crate::BitReader; #[doc = "Field `CHSEL4` writer - Channel-4 selection"] pub type CHSEL4_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL5` reader - Channel-5 selection"] pub type CHSEL5_R = crate::BitReader; #[doc = "Field `CHSEL5` writer - Channel-5 selection"] pub type CHSEL5_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL6` reader - Channel-6 selection"] pub type CHSEL6_R = crate::BitReader; #[doc = "Field `CHSEL6` writer - Channel-6 selection"] pub type CHSEL6_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL7` reader - Channel-7 selection"] pub type CHSEL7_R = crate::BitReader; #[doc = "Field `CHSEL7` writer - Channel-7 selection"] pub type CHSEL7_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL8` reader - Channel-8 selection"] pub type CHSEL8_R = crate::BitReader; #[doc = "Field `CHSEL8` writer - Channel-8 selection"] pub type CHSEL8_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL9` reader - Channel-9 selection"] pub type CHSEL9_R = crate::BitReader; #[doc = "Field `CHSEL9` writer - Channel-9 selection"] pub type CHSEL9_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL11` reader - Channel-11 selection"] pub type CHSEL11_R = crate::BitReader; #[doc = "Field `CHSEL11` writer - Channel-11 selection"] pub type CHSEL11_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; #[doc = "Field `CHSEL12` reader - Channel-12 selection"] pub type CHSEL12_R = crate::BitReader; #[doc = "Field `CHSEL12` writer - Channel-12 selection"] pub type CHSEL12_W<'a, const O: u8> = crate::BitWriter<'a, CHSELR_SPEC, O>; impl R { #[doc = "Bit 0 - Channel-0 selection"] #[inline(always)] pub fn chsel0(&self) -> CHSEL0_R { CHSEL0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Channel-1 selection"] #[inline(always)] pub fn chsel1(&self) -> CHSEL1_R { CHSEL1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Channel-2 selection"] #[inline(always)] pub fn chsel2(&self) -> CHSEL2_R { CHSEL2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Channel-3 selection"] #[inline(always)] pub fn chsel3(&self) -> CHSEL3_R { CHSEL3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Channel-4 selection"] #[inline(always)] pub fn chsel4(&self) -> CHSEL4_R { CHSEL4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Channel-5 selection"] #[inline(always)] pub fn chsel5(&self) -> CHSEL5_R { CHSEL5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Channel-6 selection"] #[inline(always)] pub fn chsel6(&self) -> CHSEL6_R { CHSEL6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Channel-7 selection"] #[inline(always)] pub fn chsel7(&self) -> CHSEL7_R { CHSEL7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Channel-8 selection"] #[inline(always)] pub fn chsel8(&self) -> CHSEL8_R { CHSEL8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Channel-9 selection"] #[inline(always)] pub fn chsel9(&self) -> CHSEL9_R { CHSEL9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 11 - Channel-11 selection"] #[inline(always)] pub fn chsel11(&self) -> CHSEL11_R { CHSEL11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Channel-12 selection"] #[inline(always)] pub fn chsel12(&self) -> CHSEL12_R { CHSEL12_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - Channel-0 selection"] #[inline(always)] #[must_use] pub fn chsel0(&mut self) -> CHSEL0_W<0> { CHSEL0_W::new(self) } #[doc = "Bit 1 - Channel-1 selection"] #[inline(always)] #[must_use] pub fn chsel1(&mut self) -> CHSEL1_W<1> { CHSEL1_W::new(self) } #[doc = "Bit 2 - Channel-2 selection"] #[inline(always)] #[must_use] pub fn chsel2(&mut self) -> CHSEL2_W<2> { CHSEL2_W::new(self) } #[doc = "Bit 3 - Channel-3 selection"] #[inline(always)] #[must_use] pub fn chsel3(&mut self) -> CHSEL3_W<3> { CHSEL3_W::new(self) } #[doc = "Bit 4 - Channel-4 selection"] #[inline(always)] #[must_use] pub fn chsel4(&mut self) -> CHSEL4_W<4> { CHSEL4_W::new(self) } #[doc = "Bit 5 - Channel-5 selection"] #[inline(always)] #[must_use] pub fn chsel5(&mut self) -> CHSEL5_W<5> { CHSEL5_W::new(self) } #[doc = "Bit 6 - Channel-6 selection"] #[inline(always)] #[must_use] pub fn chsel6(&mut self) -> CHSEL6_W<6> { CHSEL6_W::new(self) } #[doc = "Bit 7 - Channel-7 selection"] #[inline(always)] #[must_use] pub fn chsel7(&mut self) -> CHSEL7_W<7> { CHSEL7_W::new(self) } #[doc = "Bit 8 - Channel-8 selection"] #[inline(always)] #[must_use] pub fn chsel8(&mut self) -> CHSEL8_W<8> { CHSEL8_W::new(self) } #[doc = "Bit 9 - Channel-9 selection"] #[inline(always)] #[must_use] pub fn chsel9(&mut self) -> CHSEL9_W<9> { CHSEL9_W::new(self) } #[doc = "Bit 11 - Channel-11 selection"] #[inline(always)] #[must_use] pub fn chsel11(&mut self) -> CHSEL11_W<11> { CHSEL11_W::new(self) } #[doc = "Bit 12 - Channel-12 selection"] #[inline(always)] #[must_use] pub fn chsel12(&mut self) -> CHSEL12_W<12> { CHSEL12_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC group regular sequencer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chselr](index.html) module"] pub struct CHSELR_SPEC; impl crate::RegisterSpec for CHSELR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [chselr::R](R) reader structure"] impl crate::Readable for CHSELR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [chselr::W](W) writer structure"] impl crate::Writable for CHSELR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CHSELR to value 0x0fff_0000"] impl crate::Resettable for CHSELR_SPEC { const RESET_VALUE: Self::Ux = 0x0fff_0000; } } #[doc = "DR (r) register accessor: an alias for `Reg`"] pub type DR = crate::Reg; #[doc = "ADC group regular data register"] pub mod dr { #[doc = "Register `DR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `DATA` reader - ADC group regular conversion data"] pub type DATA_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - ADC group regular conversion data"] #[inline(always)] pub fn data(&self) -> DATA_R { DATA_R::new((self.bits & 0xffff) as u16) } } #[doc = "ADC group regular data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr::R](R) reader structure"] impl crate::Readable for DR_SPEC { type Reader = R; } #[doc = "`reset()` method sets DR to value 0"] impl crate::Resettable for DR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCSR (rw) register accessor: an alias for `Reg`"] pub type CCSR = crate::Reg; #[doc = "ADC calibration configuration and status register"] pub mod ccsr { #[doc = "Register `CCSR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCSR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CALSEL` reader - Calibration contents selection"] pub type CALSEL_R = crate::BitReader; #[doc = "Field `CALSEL` writer - Calibration contents selection"] pub type CALSEL_W<'a, const O: u8> = crate::BitWriter<'a, CCSR_SPEC, O>; #[doc = "Field `CALSMP` reader - Calibration sample time selection"] pub type CALSMP_R = crate::FieldReader; #[doc = "Field `CALSMP` writer - Calibration sample time selection"] pub type CALSMP_W<'a, const O: u8> = crate::FieldWriter<'a, CCSR_SPEC, 2, O>; #[doc = "Field `CALSET` reader - Calibration factor selection"] pub type CALSET_R = crate::BitReader; #[doc = "Field `CALSET` writer - Calibration factor selection"] pub type CALSET_W<'a, const O: u8> = crate::BitWriter<'a, CCSR_SPEC, O>; #[doc = "Field `CALFAIL` reader - Calibration fail flag"] pub type CALFAIL_R = crate::BitReader; #[doc = "Field `CALFAIL` writer - Calibration fail flag"] pub type CALFAIL_W<'a, const O: u8> = crate::BitWriter<'a, CCSR_SPEC, O>; #[doc = "Field `CALON` reader - Calibration flag"] pub type CALON_R = crate::BitReader; impl R { #[doc = "Bit 11 - Calibration contents selection"] #[inline(always)] pub fn calsel(&self) -> CALSEL_R { CALSEL_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bits 12:13 - Calibration sample time selection"] #[inline(always)] pub fn calsmp(&self) -> CALSMP_R { CALSMP_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bit 15 - Calibration factor selection"] #[inline(always)] pub fn calset(&self) -> CALSET_R { CALSET_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 30 - Calibration fail flag"] #[inline(always)] pub fn calfail(&self) -> CALFAIL_R { CALFAIL_R::new(((self.bits >> 30) & 1) != 0) } #[doc = "Bit 31 - Calibration flag"] #[inline(always)] pub fn calon(&self) -> CALON_R { CALON_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 11 - Calibration contents selection"] #[inline(always)] #[must_use] pub fn calsel(&mut self) -> CALSEL_W<11> { CALSEL_W::new(self) } #[doc = "Bits 12:13 - Calibration sample time selection"] #[inline(always)] #[must_use] pub fn calsmp(&mut self) -> CALSMP_W<12> { CALSMP_W::new(self) } #[doc = "Bit 15 - Calibration factor selection"] #[inline(always)] #[must_use] pub fn calset(&mut self) -> CALSET_W<15> { CALSET_W::new(self) } #[doc = "Bit 30 - Calibration fail flag"] #[inline(always)] #[must_use] pub fn calfail(&mut self) -> CALFAIL_W<30> { CALFAIL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC calibration configuration and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccsr](index.html) module"] pub struct CCSR_SPEC; impl crate::RegisterSpec for CCSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccsr::R](R) reader structure"] impl crate::Readable for CCSR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccsr::W](W) writer structure"] impl crate::Writable for CCSR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCSR to value 0"] impl crate::Resettable for CCSR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CALRR1 (r) register accessor: an alias for `Reg`"] pub type CALRR1 = crate::Reg; #[doc = "ADC calibration result register 1"] pub mod calrr1 { #[doc = "Register `CALRR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `CALC4OUT` reader - C4 result"] pub type CALC4OUT_R = crate::FieldReader; #[doc = "Field `CALC5OUT` reader - C5 result"] pub type CALC5OUT_R = crate::FieldReader; #[doc = "Field `CALBOUT` reader - offset result"] pub type CALBOUT_R = crate::FieldReader; impl R { #[doc = "Bits 0:7 - C4 result"] #[inline(always)] pub fn calc4out(&self) -> CALC4OUT_R { CALC4OUT_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - C5 result"] #[inline(always)] pub fn calc5out(&self) -> CALC5OUT_R { CALC5OUT_R::new(((self.bits >> 8) & 0xff) as u8) } #[doc = "Bits 16:22 - offset result"] #[inline(always)] pub fn calbout(&self) -> CALBOUT_R { CALBOUT_R::new(((self.bits >> 16) & 0x7f) as u8) } } #[doc = "ADC calibration result register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calrr1](index.html) module"] pub struct CALRR1_SPEC; impl crate::RegisterSpec for CALRR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [calrr1::R](R) reader structure"] impl crate::Readable for CALRR1_SPEC { type Reader = R; } #[doc = "`reset()` method sets CALRR1 to value 0"] impl crate::Resettable for CALRR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CALRR2 (r) register accessor: an alias for `Reg`"] pub type CALRR2 = crate::Reg; #[doc = "ADC calibration result register 2"] pub mod calrr2 { #[doc = "Register `CALRR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `CALC0OUT` reader - C0 result"] pub type CALC0OUT_R = crate::FieldReader; #[doc = "Field `CALC1OUT` reader - C1 result"] pub type CALC1OUT_R = crate::FieldReader; #[doc = "Field `CALC2OUT` reader - C2 result"] pub type CALC2OUT_R = crate::FieldReader; #[doc = "Field `CALC3OUT` reader - C3 result"] pub type CALC3OUT_R = crate::FieldReader; impl R { #[doc = "Bits 0:7 - C0 result"] #[inline(always)] pub fn calc0out(&self) -> CALC0OUT_R { CALC0OUT_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - C1 result"] #[inline(always)] pub fn calc1out(&self) -> CALC1OUT_R { CALC1OUT_R::new(((self.bits >> 8) & 0xff) as u8) } #[doc = "Bits 16:23 - C2 result"] #[inline(always)] pub fn calc2out(&self) -> CALC2OUT_R { CALC2OUT_R::new(((self.bits >> 16) & 0xff) as u8) } #[doc = "Bits 24:31 - C3 result"] #[inline(always)] pub fn calc3out(&self) -> CALC3OUT_R { CALC3OUT_R::new(((self.bits >> 24) & 0xff) as u8) } } #[doc = "ADC calibration result register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calrr2](index.html) module"] pub struct CALRR2_SPEC; impl crate::RegisterSpec for CALRR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [calrr2::R](R) reader structure"] impl crate::Readable for CALRR2_SPEC { type Reader = R; } #[doc = "`reset()` method sets CALRR2 to value 0"] impl crate::Resettable for CALRR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CALFIR1 (rw) register accessor: an alias for `Reg`"] pub type CALFIR1 = crate::Reg; #[doc = "ADC calibration factor input register 1"] pub mod calfir1 { #[doc = "Register `CALFIR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CALFIR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CALC4IO` reader - Calibration C4 factor input"] pub type CALC4IO_R = crate::FieldReader; #[doc = "Field `CALC4IO` writer - Calibration C4 factor input"] pub type CALC4IO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR1_SPEC, 8, O>; #[doc = "Field `CALC5IO` reader - Calibration C5 factor input"] pub type CALC5IO_R = crate::FieldReader; #[doc = "Field `CALC5IO` writer - Calibration C5 factor input"] pub type CALC5IO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR1_SPEC, 8, O>; #[doc = "Field `CALBIO` reader - Calibration offset factor input"] pub type CALBIO_R = crate::FieldReader; #[doc = "Field `CALBIO` writer - Calibration offset factor input"] pub type CALBIO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR1_SPEC, 7, O>; impl R { #[doc = "Bits 0:7 - Calibration C4 factor input"] #[inline(always)] pub fn calc4io(&self) -> CALC4IO_R { CALC4IO_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - Calibration C5 factor input"] #[inline(always)] pub fn calc5io(&self) -> CALC5IO_R { CALC5IO_R::new(((self.bits >> 8) & 0xff) as u8) } #[doc = "Bits 16:22 - Calibration offset factor input"] #[inline(always)] pub fn calbio(&self) -> CALBIO_R { CALBIO_R::new(((self.bits >> 16) & 0x7f) as u8) } } impl W { #[doc = "Bits 0:7 - Calibration C4 factor input"] #[inline(always)] #[must_use] pub fn calc4io(&mut self) -> CALC4IO_W<0> { CALC4IO_W::new(self) } #[doc = "Bits 8:15 - Calibration C5 factor input"] #[inline(always)] #[must_use] pub fn calc5io(&mut self) -> CALC5IO_W<8> { CALC5IO_W::new(self) } #[doc = "Bits 16:22 - Calibration offset factor input"] #[inline(always)] #[must_use] pub fn calbio(&mut self) -> CALBIO_W<16> { CALBIO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC calibration factor input register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calfir1](index.html) module"] pub struct CALFIR1_SPEC; impl crate::RegisterSpec for CALFIR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [calfir1::R](R) reader structure"] impl crate::Readable for CALFIR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [calfir1::W](W) writer structure"] impl crate::Writable for CALFIR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CALFIR1 to value 0"] impl crate::Resettable for CALFIR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CALFIR2 (rw) register accessor: an alias for `Reg`"] pub type CALFIR2 = crate::Reg; #[doc = "ADC calibration factor input register 2"] pub mod calfir2 { #[doc = "Register `CALFIR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CALFIR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CALC0IO` reader - Calibration C0 factor input"] pub type CALC0IO_R = crate::FieldReader; #[doc = "Field `CALC0IO` writer - Calibration C0 factor input"] pub type CALC0IO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR2_SPEC, 8, O>; #[doc = "Field `CALC1IO` reader - Calibration C1 factor input"] pub type CALC1IO_R = crate::FieldReader; #[doc = "Field `CALC1IO` writer - Calibration C1 factor input"] pub type CALC1IO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR2_SPEC, 8, O>; #[doc = "Field `CALC2IO` reader - Calibration C2 factor input"] pub type CALC2IO_R = crate::FieldReader; #[doc = "Field `CALC2IO` writer - Calibration C2 factor input"] pub type CALC2IO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR2_SPEC, 8, O>; #[doc = "Field `CALC3IO` reader - Calibration C3 factor input"] pub type CALC3IO_R = crate::FieldReader; #[doc = "Field `CALC3IO` writer - Calibration C3 factor input"] pub type CALC3IO_W<'a, const O: u8> = crate::FieldWriter<'a, CALFIR2_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - Calibration C0 factor input"] #[inline(always)] pub fn calc0io(&self) -> CALC0IO_R { CALC0IO_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - Calibration C1 factor input"] #[inline(always)] pub fn calc1io(&self) -> CALC1IO_R { CALC1IO_R::new(((self.bits >> 8) & 0xff) as u8) } #[doc = "Bits 16:23 - Calibration C2 factor input"] #[inline(always)] pub fn calc2io(&self) -> CALC2IO_R { CALC2IO_R::new(((self.bits >> 16) & 0xff) as u8) } #[doc = "Bits 24:31 - Calibration C3 factor input"] #[inline(always)] pub fn calc3io(&self) -> CALC3IO_R { CALC3IO_R::new(((self.bits >> 24) & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - Calibration C0 factor input"] #[inline(always)] #[must_use] pub fn calc0io(&mut self) -> CALC0IO_W<0> { CALC0IO_W::new(self) } #[doc = "Bits 8:15 - Calibration C1 factor input"] #[inline(always)] #[must_use] pub fn calc1io(&mut self) -> CALC1IO_W<8> { CALC1IO_W::new(self) } #[doc = "Bits 16:23 - Calibration C2 factor input"] #[inline(always)] #[must_use] pub fn calc2io(&mut self) -> CALC2IO_W<16> { CALC2IO_W::new(self) } #[doc = "Bits 24:31 - Calibration C3 factor input"] #[inline(always)] #[must_use] pub fn calc3io(&mut self) -> CALC3IO_W<24> { CALC3IO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC calibration factor input register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calfir2](index.html) module"] pub struct CALFIR2_SPEC; impl crate::RegisterSpec for CALFIR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [calfir2::R](R) reader structure"] impl crate::Readable for CALFIR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [calfir2::W](W) writer structure"] impl crate::Writable for CALFIR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CALFIR2 to value 0"] impl crate::Resettable for CALFIR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR (rw) register accessor: an alias for `Reg`"] pub type CCR = crate::Reg; #[doc = "ADC common configuration register"] pub mod ccr { #[doc = "Register `CCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `VREFEN` reader - VREFINT enable"] pub type VREFEN_R = crate::BitReader; #[doc = "Field `VREFEN` writer - VREFINT enable"] pub type VREFEN_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; #[doc = "Field `TSEN` reader - Temperature sensor enable"] pub type TSEN_R = crate::BitReader; #[doc = "Field `TSEN` writer - Temperature sensor enable"] pub type TSEN_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; impl R { #[doc = "Bit 22 - VREFINT enable"] #[inline(always)] pub fn vrefen(&self) -> VREFEN_R { VREFEN_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Temperature sensor enable"] #[inline(always)] pub fn tsen(&self) -> TSEN_R { TSEN_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bit 22 - VREFINT enable"] #[inline(always)] #[must_use] pub fn vrefen(&mut self) -> VREFEN_W<22> { VREFEN_W::new(self) } #[doc = "Bit 23 - Temperature sensor enable"] #[inline(always)] #[must_use] pub fn tsen(&mut self) -> TSEN_W<23> { TSEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "ADC common configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] pub struct CCR_SPEC; impl crate::RegisterSpec for CCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr::R](R) reader structure"] impl crate::Readable for CCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr::W](W) writer structure"] impl crate::Writable for CCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR to value 0"] impl crate::Resettable for CCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Comparator"] pub struct COMP1 { _marker: PhantomData<*const ()>, } unsafe impl Send for COMP1 {} impl COMP1 { #[doc = r"Pointer to the register block"] pub const PTR: *const comp1::RegisterBlock = 0x4001_0200 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const comp1::RegisterBlock { Self::PTR } } impl Deref for COMP1 { type Target = comp1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for COMP1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("COMP1").finish() } } #[doc = "Comparator"] pub mod comp1 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - COMP control and status register"] pub csr: CSR, #[doc = "0x04 - Comparator Filter register"] pub fr: FR, } #[doc = "CSR (rw) register accessor: an alias for `Reg`"] pub type CSR = crate::Reg; #[doc = "COMP control and status register"] pub mod csr { #[doc = "Register `CSR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CSR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `COMP_EN` reader - COMP enable bit"] pub type COMP_EN_R = crate::BitReader; #[doc = "Field `COMP_EN` writer - COMP enable bit"] pub type COMP_EN_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `SCALER_EN` reader - SCALER enable bit"] pub type SCALER_EN_R = crate::BitReader; #[doc = "Field `SCALER_EN` writer - SCALER enable bit"] pub type SCALER_EN_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `INMSEL` reader - Comparator signal selector for inverting input INM"] pub type INMSEL_R = crate::FieldReader; #[doc = "Field `INMSEL` writer - Comparator signal selector for inverting input INM"] pub type INMSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 4, O>; #[doc = "Field `INPSEL` reader - Comparator signal selector for non-inverting input"] pub type INPSEL_R = crate::FieldReader; #[doc = "Field `INPSEL` writer - Comparator signal selector for non-inverting input"] pub type INPSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 2, O>; #[doc = "Field `WINMODE` reader - Comparator non-inverting input selector for window mode"] pub type WINMODE_R = crate::BitReader; #[doc = "Field `WINMODE` writer - Comparator non-inverting input selector for window mode"] pub type WINMODE_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `POLARITY` reader - Comparator polarity selector"] pub type POLARITY_R = crate::BitReader; #[doc = "Field `POLARITY` writer - Comparator polarity selector"] pub type POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `HYST` reader - Comparator hysteresis enable selector"] pub type HYST_R = crate::BitReader; #[doc = "Field `HYST` writer - Comparator hysteresis enable selector"] pub type HYST_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `PWRMODE` reader - Comparator power mode selector"] pub type PWRMODE_R = crate::FieldReader; #[doc = "Field `PWRMODE` writer - Comparator power mode selector"] pub type PWRMODE_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 2, O>; #[doc = "Field `COMP_OUT` reader - Comparator output status"] pub type COMP_OUT_R = crate::BitReader; #[doc = "Field `COMP_OUT` writer - Comparator output status"] pub type COMP_OUT_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `LOCK` reader - CSR register lock"] pub type LOCK_R = crate::BitReader; #[doc = "Field `LOCK` writer - CSR register lock"] pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; impl R { #[doc = "Bit 0 - COMP enable bit"] #[inline(always)] pub fn comp_en(&self) -> COMP_EN_R { COMP_EN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - SCALER enable bit"] #[inline(always)] pub fn scaler_en(&self) -> SCALER_EN_R { SCALER_EN_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 4:7 - Comparator signal selector for inverting input INM"] #[inline(always)] pub fn inmsel(&self) -> INMSEL_R { INMSEL_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:9 - Comparator signal selector for non-inverting input"] #[inline(always)] pub fn inpsel(&self) -> INPSEL_R { INPSEL_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 11 - Comparator non-inverting input selector for window mode"] #[inline(always)] pub fn winmode(&self) -> WINMODE_R { WINMODE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 15 - Comparator polarity selector"] #[inline(always)] pub fn polarity(&self) -> POLARITY_R { POLARITY_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Comparator hysteresis enable selector"] #[inline(always)] pub fn hyst(&self) -> HYST_R { HYST_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bits 18:19 - Comparator power mode selector"] #[inline(always)] pub fn pwrmode(&self) -> PWRMODE_R { PWRMODE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bit 30 - Comparator output status"] #[inline(always)] pub fn comp_out(&self) -> COMP_OUT_R { COMP_OUT_R::new(((self.bits >> 30) & 1) != 0) } #[doc = "Bit 31 - CSR register lock"] #[inline(always)] pub fn lock(&self) -> LOCK_R { LOCK_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 0 - COMP enable bit"] #[inline(always)] #[must_use] pub fn comp_en(&mut self) -> COMP_EN_W<0> { COMP_EN_W::new(self) } #[doc = "Bit 1 - SCALER enable bit"] #[inline(always)] #[must_use] pub fn scaler_en(&mut self) -> SCALER_EN_W<1> { SCALER_EN_W::new(self) } #[doc = "Bits 4:7 - Comparator signal selector for inverting input INM"] #[inline(always)] #[must_use] pub fn inmsel(&mut self) -> INMSEL_W<4> { INMSEL_W::new(self) } #[doc = "Bits 8:9 - Comparator signal selector for non-inverting input"] #[inline(always)] #[must_use] pub fn inpsel(&mut self) -> INPSEL_W<8> { INPSEL_W::new(self) } #[doc = "Bit 11 - Comparator non-inverting input selector for window mode"] #[inline(always)] #[must_use] pub fn winmode(&mut self) -> WINMODE_W<11> { WINMODE_W::new(self) } #[doc = "Bit 15 - Comparator polarity selector"] #[inline(always)] #[must_use] pub fn polarity(&mut self) -> POLARITY_W<15> { POLARITY_W::new(self) } #[doc = "Bit 16 - Comparator hysteresis enable selector"] #[inline(always)] #[must_use] pub fn hyst(&mut self) -> HYST_W<16> { HYST_W::new(self) } #[doc = "Bits 18:19 - Comparator power mode selector"] #[inline(always)] #[must_use] pub fn pwrmode(&mut self) -> PWRMODE_W<18> { PWRMODE_W::new(self) } #[doc = "Bit 30 - Comparator output status"] #[inline(always)] #[must_use] pub fn comp_out(&mut self) -> COMP_OUT_W<30> { COMP_OUT_W::new(self) } #[doc = "Bit 31 - CSR register lock"] #[inline(always)] #[must_use] pub fn lock(&mut self) -> LOCK_W<31> { LOCK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "COMP control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] pub struct CSR_SPEC; impl crate::RegisterSpec for CSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [csr::R](R) reader structure"] impl crate::Readable for CSR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] impl crate::Writable for CSR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CSR to value 0"] impl crate::Resettable for CSR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "FR (rw) register accessor: an alias for `Reg`"] pub type FR = crate::Reg; #[doc = "Comparator Filter register"] pub mod fr { #[doc = "Register `FR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `FR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `FLTEN` reader - Filter enable bit"] pub type FLTEN_R = crate::BitReader; #[doc = "Field `FLTEN` writer - Filter enable bit"] pub type FLTEN_W<'a, const O: u8> = crate::BitWriter<'a, FR_SPEC, O>; #[doc = "Field `FLTCNT` reader - Comparator filter and counter"] pub type FLTCNT_R = crate::FieldReader; #[doc = "Field `FLTCNT` writer - Comparator filter and counter"] pub type FLTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, FR_SPEC, 16, O, u16>; impl R { #[doc = "Bit 0 - Filter enable bit"] #[inline(always)] pub fn flten(&self) -> FLTEN_R { FLTEN_R::new((self.bits & 1) != 0) } #[doc = "Bits 16:31 - Comparator filter and counter"] #[inline(always)] pub fn fltcnt(&self) -> FLTCNT_R { FLTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) } } impl W { #[doc = "Bit 0 - Filter enable bit"] #[inline(always)] #[must_use] pub fn flten(&mut self) -> FLTEN_W<0> { FLTEN_W::new(self) } #[doc = "Bits 16:31 - Comparator filter and counter"] #[inline(always)] #[must_use] pub fn fltcnt(&mut self) -> FLTCNT_W<16> { FLTCNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Comparator Filter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] pub struct FR_SPEC; impl crate::RegisterSpec for FR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [fr::R](R) reader structure"] impl crate::Readable for FR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] impl crate::Writable for FR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets FR to value 0"] impl crate::Resettable for FR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Comparator"] pub struct COMP2 { _marker: PhantomData<*const ()>, } unsafe impl Send for COMP2 {} impl COMP2 { #[doc = r"Pointer to the register block"] pub const PTR: *const comp2::RegisterBlock = 0x4001_0210 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const comp2::RegisterBlock { Self::PTR } } impl Deref for COMP2 { type Target = comp2::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for COMP2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("COMP2").finish() } } #[doc = "Comparator"] pub mod comp2 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - COMP control and status register"] pub csr: CSR, #[doc = "0x04 - Comparator Filter register"] pub fr: FR, } #[doc = "CSR (rw) register accessor: an alias for `Reg`"] pub type CSR = crate::Reg; #[doc = "COMP control and status register"] pub mod csr { #[doc = "Register `CSR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CSR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `COMP_EN` reader - COMP enable bit"] pub type COMP_EN_R = crate::BitReader; #[doc = "Field `COMP_EN` writer - COMP enable bit"] pub type COMP_EN_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `INMSEL` reader - Comparator signal selector for inverting input INM"] pub type INMSEL_R = crate::FieldReader; #[doc = "Field `INMSEL` writer - Comparator signal selector for inverting input INM"] pub type INMSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 4, O>; #[doc = "Field `INPSEL` reader - Comparator signal selector for non-inverting input"] pub type INPSEL_R = crate::FieldReader; #[doc = "Field `INPSEL` writer - Comparator signal selector for non-inverting input"] pub type INPSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 2, O>; #[doc = "Field `WINMODE` reader - Comparator non-inverting input selector for window mode"] pub type WINMODE_R = crate::BitReader; #[doc = "Field `WINMODE` writer - Comparator non-inverting input selector for window mode"] pub type WINMODE_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `POLARITY` reader - Comparator polarity selector"] pub type POLARITY_R = crate::BitReader; #[doc = "Field `POLARITY` writer - Comparator polarity selector"] pub type POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `PWRMODE` reader - Comparator power mode selector"] pub type PWRMODE_R = crate::FieldReader; #[doc = "Field `PWRMODE` writer - Comparator power mode selector"] pub type PWRMODE_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 2, O>; #[doc = "Field `COMP_OUT` reader - Comparator output status"] pub type COMP_OUT_R = crate::BitReader; #[doc = "Field `COMP_OUT` writer - Comparator output status"] pub type COMP_OUT_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `LOCK` reader - CSR register lock"] pub type LOCK_R = crate::BitReader; #[doc = "Field `LOCK` writer - CSR register lock"] pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; impl R { #[doc = "Bit 0 - COMP enable bit"] #[inline(always)] pub fn comp_en(&self) -> COMP_EN_R { COMP_EN_R::new((self.bits & 1) != 0) } #[doc = "Bits 4:7 - Comparator signal selector for inverting input INM"] #[inline(always)] pub fn inmsel(&self) -> INMSEL_R { INMSEL_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:9 - Comparator signal selector for non-inverting input"] #[inline(always)] pub fn inpsel(&self) -> INPSEL_R { INPSEL_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 11 - Comparator non-inverting input selector for window mode"] #[inline(always)] pub fn winmode(&self) -> WINMODE_R { WINMODE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 15 - Comparator polarity selector"] #[inline(always)] pub fn polarity(&self) -> POLARITY_R { POLARITY_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bits 18:19 - Comparator power mode selector"] #[inline(always)] pub fn pwrmode(&self) -> PWRMODE_R { PWRMODE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bit 30 - Comparator output status"] #[inline(always)] pub fn comp_out(&self) -> COMP_OUT_R { COMP_OUT_R::new(((self.bits >> 30) & 1) != 0) } #[doc = "Bit 31 - CSR register lock"] #[inline(always)] pub fn lock(&self) -> LOCK_R { LOCK_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 0 - COMP enable bit"] #[inline(always)] #[must_use] pub fn comp_en(&mut self) -> COMP_EN_W<0> { COMP_EN_W::new(self) } #[doc = "Bits 4:7 - Comparator signal selector for inverting input INM"] #[inline(always)] #[must_use] pub fn inmsel(&mut self) -> INMSEL_W<4> { INMSEL_W::new(self) } #[doc = "Bits 8:9 - Comparator signal selector for non-inverting input"] #[inline(always)] #[must_use] pub fn inpsel(&mut self) -> INPSEL_W<8> { INPSEL_W::new(self) } #[doc = "Bit 11 - Comparator non-inverting input selector for window mode"] #[inline(always)] #[must_use] pub fn winmode(&mut self) -> WINMODE_W<11> { WINMODE_W::new(self) } #[doc = "Bit 15 - Comparator polarity selector"] #[inline(always)] #[must_use] pub fn polarity(&mut self) -> POLARITY_W<15> { POLARITY_W::new(self) } #[doc = "Bits 18:19 - Comparator power mode selector"] #[inline(always)] #[must_use] pub fn pwrmode(&mut self) -> PWRMODE_W<18> { PWRMODE_W::new(self) } #[doc = "Bit 30 - Comparator output status"] #[inline(always)] #[must_use] pub fn comp_out(&mut self) -> COMP_OUT_W<30> { COMP_OUT_W::new(self) } #[doc = "Bit 31 - CSR register lock"] #[inline(always)] #[must_use] pub fn lock(&mut self) -> LOCK_W<31> { LOCK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "COMP control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] pub struct CSR_SPEC; impl crate::RegisterSpec for CSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [csr::R](R) reader structure"] impl crate::Readable for CSR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] impl crate::Writable for CSR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CSR to value 0"] impl crate::Resettable for CSR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "FR (rw) register accessor: an alias for `Reg`"] pub type FR = crate::Reg; #[doc = "Comparator Filter register"] pub mod fr { #[doc = "Register `FR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `FR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `FLTEN` reader - Filter enable bit"] pub type FLTEN_R = crate::BitReader; #[doc = "Field `FLTEN` writer - Filter enable bit"] pub type FLTEN_W<'a, const O: u8> = crate::BitWriter<'a, FR_SPEC, O>; #[doc = "Field `FLTCNT` reader - Comparator filter and counter"] pub type FLTCNT_R = crate::FieldReader; #[doc = "Field `FLTCNT` writer - Comparator filter and counter"] pub type FLTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, FR_SPEC, 16, O, u16>; impl R { #[doc = "Bit 0 - Filter enable bit"] #[inline(always)] pub fn flten(&self) -> FLTEN_R { FLTEN_R::new((self.bits & 1) != 0) } #[doc = "Bits 16:31 - Comparator filter and counter"] #[inline(always)] pub fn fltcnt(&self) -> FLTCNT_R { FLTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) } } impl W { #[doc = "Bit 0 - Filter enable bit"] #[inline(always)] #[must_use] pub fn flten(&mut self) -> FLTEN_W<0> { FLTEN_W::new(self) } #[doc = "Bits 16:31 - Comparator filter and counter"] #[inline(always)] #[must_use] pub fn fltcnt(&mut self) -> FLTCNT_W<16> { FLTCNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Comparator Filter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] pub struct FR_SPEC; impl crate::RegisterSpec for FR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [fr::R](R) reader structure"] impl crate::Readable for FR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] impl crate::Writable for FR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets FR to value 0"] impl crate::Resettable for FR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Reset and clock control"] pub struct RCC { _marker: PhantomData<*const ()>, } unsafe impl Send for RCC {} impl RCC { #[doc = r"Pointer to the register block"] pub const PTR: *const rcc::RegisterBlock = 0x4002_1000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const rcc::RegisterBlock { Self::PTR } } impl Deref for RCC { type Target = rcc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for RCC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("RCC").finish() } } #[doc = "Reset and clock control"] pub mod rcc { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Clock control register"] pub cr: CR, #[doc = "0x04 - Internal clock sources calibration register"] pub icscr: ICSCR, #[doc = "0x08 - Clock configuration register"] pub cfgr: CFGR, #[doc = "0x0c - PLL configuration register"] pub pllcfgr: PLLCFGR, #[doc = "0x10 - External clock source control register"] pub ecscr: ECSCR, _reserved5: [u8; 0x04], #[doc = "0x18 - Clock interrupt enable register"] pub cier: CIER, #[doc = "0x1c - Clock interrupt flag register"] pub cifr: CIFR, #[doc = "0x20 - Clock interrupt clear register"] pub cicr: CICR, #[doc = "0x24 - GPIO reset register"] pub ioprstr: IOPRSTR, #[doc = "0x28 - AHB peripheral reset register"] pub ahbrstr: AHBRSTR, #[doc = "0x2c - APB peripheral reset register 1"] pub apbrstr1: APBRSTR1, #[doc = "0x30 - APB peripheral reset register 2"] pub apbrstr2: APBRSTR2, #[doc = "0x34 - GPIO clock enable register"] pub iopenr: IOPENR, #[doc = "0x38 - AHB peripheral clock enable register"] pub ahbenr: AHBENR, #[doc = "0x3c - APB peripheral clock enable register 1"] pub apbenr1: APBENR1, #[doc = "0x40 - APB peripheral clock enable register 2"] pub apbenr2: APBENR2, _reserved16: [u8; 0x10], #[doc = "0x54 - Peripherals independent clock configuration register"] pub ccipr: CCIPR, _reserved17: [u8; 0x04], #[doc = "0x5c - RTC domain control register"] pub bdcr: BDCR, #[doc = "0x60 - Control/status register"] pub csr: CSR, } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Clock control register"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `HSION` reader - HSI16 clock enable"] pub type HSION_R = crate::BitReader; #[doc = "Field `HSION` writer - HSI16 clock enable"] pub type HSION_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `HSIKERON` reader - HSI16 always enable for peripheral kernels"] pub type HSIKERON_R = crate::BitReader; #[doc = "Field `HSIKERON` writer - HSI16 always enable for peripheral kernels"] pub type HSIKERON_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `HSIRDY` reader - HSI16 clock ready flag"] pub type HSIRDY_R = crate::BitReader; #[doc = "Field `HSIRDY` writer - HSI16 clock ready flag"] pub type HSIRDY_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `HSIDIV` reader - HSI16 clock division factor"] pub type HSIDIV_R = crate::FieldReader; #[doc = "Field `HSIDIV` writer - HSI16 clock division factor"] pub type HSIDIV_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 3, O>; #[doc = "Field `HSEON` reader - HSE clock enable"] pub type HSEON_R = crate::BitReader; #[doc = "Field `HSEON` writer - HSE clock enable"] pub type HSEON_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `HSERDY` reader - HSE clock ready flag"] pub type HSERDY_R = crate::BitReader; #[doc = "Field `HSERDY` writer - HSE clock ready flag"] pub type HSERDY_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `HSEBYP` reader - HSE crystal oscillator bypass"] pub type HSEBYP_R = crate::BitReader; #[doc = "Field `HSEBYP` writer - HSE crystal oscillator bypass"] pub type HSEBYP_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `CSSON` reader - Clock security system enable"] pub type CSSON_R = crate::BitReader; #[doc = "Field `CSSON` writer - Clock security system enable"] pub type CSSON_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `PLLON` reader - PLL enable"] pub type PLLON_R = crate::BitReader; #[doc = "Field `PLLON` writer - PLL enable"] pub type PLLON_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `PLLRDY` reader - PLL clock ready flag"] pub type PLLRDY_R = crate::BitReader; #[doc = "Field `PLLRDY` writer - PLL clock ready flag"] pub type PLLRDY_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl R { #[doc = "Bit 8 - HSI16 clock enable"] #[inline(always)] pub fn hsion(&self) -> HSION_R { HSION_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - HSI16 always enable for peripheral kernels"] #[inline(always)] pub fn hsikeron(&self) -> HSIKERON_R { HSIKERON_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - HSI16 clock ready flag"] #[inline(always)] pub fn hsirdy(&self) -> HSIRDY_R { HSIRDY_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bits 11:13 - HSI16 clock division factor"] #[inline(always)] pub fn hsidiv(&self) -> HSIDIV_R { HSIDIV_R::new(((self.bits >> 11) & 7) as u8) } #[doc = "Bit 16 - HSE clock enable"] #[inline(always)] pub fn hseon(&self) -> HSEON_R { HSEON_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - HSE clock ready flag"] #[inline(always)] pub fn hserdy(&self) -> HSERDY_R { HSERDY_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - HSE crystal oscillator bypass"] #[inline(always)] pub fn hsebyp(&self) -> HSEBYP_R { HSEBYP_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - Clock security system enable"] #[inline(always)] pub fn csson(&self) -> CSSON_R { CSSON_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 24 - PLL enable"] #[inline(always)] pub fn pllon(&self) -> PLLON_R { PLLON_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - PLL clock ready flag"] #[inline(always)] pub fn pllrdy(&self) -> PLLRDY_R { PLLRDY_R::new(((self.bits >> 25) & 1) != 0) } } impl W { #[doc = "Bit 8 - HSI16 clock enable"] #[inline(always)] #[must_use] pub fn hsion(&mut self) -> HSION_W<8> { HSION_W::new(self) } #[doc = "Bit 9 - HSI16 always enable for peripheral kernels"] #[inline(always)] #[must_use] pub fn hsikeron(&mut self) -> HSIKERON_W<9> { HSIKERON_W::new(self) } #[doc = "Bit 10 - HSI16 clock ready flag"] #[inline(always)] #[must_use] pub fn hsirdy(&mut self) -> HSIRDY_W<10> { HSIRDY_W::new(self) } #[doc = "Bits 11:13 - HSI16 clock division factor"] #[inline(always)] #[must_use] pub fn hsidiv(&mut self) -> HSIDIV_W<11> { HSIDIV_W::new(self) } #[doc = "Bit 16 - HSE clock enable"] #[inline(always)] #[must_use] pub fn hseon(&mut self) -> HSEON_W<16> { HSEON_W::new(self) } #[doc = "Bit 17 - HSE clock ready flag"] #[inline(always)] #[must_use] pub fn hserdy(&mut self) -> HSERDY_W<17> { HSERDY_W::new(self) } #[doc = "Bit 18 - HSE crystal oscillator bypass"] #[inline(always)] #[must_use] pub fn hsebyp(&mut self) -> HSEBYP_W<18> { HSEBYP_W::new(self) } #[doc = "Bit 19 - Clock security system enable"] #[inline(always)] #[must_use] pub fn csson(&mut self) -> CSSON_W<19> { CSSON_W::new(self) } #[doc = "Bit 24 - PLL enable"] #[inline(always)] #[must_use] pub fn pllon(&mut self) -> PLLON_W<24> { PLLON_W::new(self) } #[doc = "Bit 25 - PLL clock ready flag"] #[inline(always)] #[must_use] pub fn pllrdy(&mut self) -> PLLRDY_W<25> { PLLRDY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Clock control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0x0100"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0x0100; } } #[doc = "ICSCR (rw) register accessor: an alias for `Reg`"] pub type ICSCR = crate::Reg; #[doc = "Internal clock sources calibration register"] pub mod icscr { #[doc = "Register `ICSCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ICSCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `HSI_TRIM` reader - HSI clock trimming"] pub type HSI_TRIM_R = crate::FieldReader; #[doc = "Field `HSI_TRIM` writer - HSI clock trimming"] pub type HSI_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, ICSCR_SPEC, 13, O, u16>; #[doc = "Field `HSI_FS` reader - HSI frequency selection"] pub type HSI_FS_R = crate::FieldReader; #[doc = "Field `HSI_FS` writer - HSI frequency selection"] pub type HSI_FS_W<'a, const O: u8> = crate::FieldWriter<'a, ICSCR_SPEC, 3, O>; #[doc = "Field `LSI_TRIM` reader - LSI clock trimming"] pub type LSI_TRIM_R = crate::FieldReader; #[doc = "Field `LSI_TRIM` writer - LSI clock trimming"] pub type LSI_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, ICSCR_SPEC, 9, O, u16>; #[doc = "Field `LSI_STARTUP` reader - LSI startup time"] pub type LSI_STARTUP_R = crate::FieldReader; #[doc = "Field `LSI_STARTUP` writer - LSI startup time"] pub type LSI_STARTUP_W<'a, const O: u8> = crate::FieldWriter<'a, ICSCR_SPEC, 2, O>; impl R { #[doc = "Bits 0:12 - HSI clock trimming"] #[inline(always)] pub fn hsi_trim(&self) -> HSI_TRIM_R { HSI_TRIM_R::new((self.bits & 0x1fff) as u16) } #[doc = "Bits 13:15 - HSI frequency selection"] #[inline(always)] pub fn hsi_fs(&self) -> HSI_FS_R { HSI_FS_R::new(((self.bits >> 13) & 7) as u8) } #[doc = "Bits 16:24 - LSI clock trimming"] #[inline(always)] pub fn lsi_trim(&self) -> LSI_TRIM_R { LSI_TRIM_R::new(((self.bits >> 16) & 0x01ff) as u16) } #[doc = "Bits 26:27 - LSI startup time"] #[inline(always)] pub fn lsi_startup(&self) -> LSI_STARTUP_R { LSI_STARTUP_R::new(((self.bits >> 26) & 3) as u8) } } impl W { #[doc = "Bits 0:12 - HSI clock trimming"] #[inline(always)] #[must_use] pub fn hsi_trim(&mut self) -> HSI_TRIM_W<0> { HSI_TRIM_W::new(self) } #[doc = "Bits 13:15 - HSI frequency selection"] #[inline(always)] #[must_use] pub fn hsi_fs(&mut self) -> HSI_FS_W<13> { HSI_FS_W::new(self) } #[doc = "Bits 16:24 - LSI clock trimming"] #[inline(always)] #[must_use] pub fn lsi_trim(&mut self) -> LSI_TRIM_W<16> { LSI_TRIM_W::new(self) } #[doc = "Bits 26:27 - LSI startup time"] #[inline(always)] #[must_use] pub fn lsi_startup(&mut self) -> LSI_STARTUP_W<26> { LSI_STARTUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Internal clock sources calibration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icscr](index.html) module"] pub struct ICSCR_SPEC; impl crate::RegisterSpec for ICSCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [icscr::R](R) reader structure"] impl crate::Readable for ICSCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [icscr::W](W) writer structure"] impl crate::Writable for ICSCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ICSCR to value 0x1000_0000"] impl crate::Resettable for ICSCR_SPEC { const RESET_VALUE: Self::Ux = 0x1000_0000; } } #[doc = "CFGR (rw) register accessor: an alias for `Reg`"] pub type CFGR = crate::Reg; #[doc = "Clock configuration register"] pub mod cfgr { #[doc = "Register `CFGR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SW` reader - System clock switch"] pub type SW_R = crate::FieldReader; #[doc = "Field `SW` writer - System clock switch"] pub type SW_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR_SPEC, 3, O>; #[doc = "Field `SWS` reader - System clock switch status"] pub type SWS_R = crate::FieldReader; #[doc = "Field `HPRE` reader - AHB prescaler"] pub type HPRE_R = crate::FieldReader; #[doc = "Field `HPRE` writer - AHB prescaler"] pub type HPRE_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR_SPEC, 4, O>; #[doc = "Field `PPRE` reader - APB prescaler"] pub type PPRE_R = crate::FieldReader; #[doc = "Field `PPRE` writer - APB prescaler"] pub type PPRE_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR_SPEC, 3, O>; #[doc = "Field `MCOSEL` reader - Microcontroller clock output"] pub type MCOSEL_R = crate::FieldReader; #[doc = "Field `MCOSEL` writer - Microcontroller clock output"] pub type MCOSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR_SPEC, 3, O>; #[doc = "Field `MCOPRE` reader - Microcontroller clock output prescaler"] pub type MCOPRE_R = crate::FieldReader; #[doc = "Field `MCOPRE` writer - Microcontroller clock output prescaler"] pub type MCOPRE_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR_SPEC, 3, O>; impl R { #[doc = "Bits 0:2 - System clock switch"] #[inline(always)] pub fn sw(&self) -> SW_R { SW_R::new((self.bits & 7) as u8) } #[doc = "Bits 3:5 - System clock switch status"] #[inline(always)] pub fn sws(&self) -> SWS_R { SWS_R::new(((self.bits >> 3) & 7) as u8) } #[doc = "Bits 8:11 - AHB prescaler"] #[inline(always)] pub fn hpre(&self) -> HPRE_R { HPRE_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:14 - APB prescaler"] #[inline(always)] pub fn ppre(&self) -> PPRE_R { PPRE_R::new(((self.bits >> 12) & 7) as u8) } #[doc = "Bits 24:26 - Microcontroller clock output"] #[inline(always)] pub fn mcosel(&self) -> MCOSEL_R { MCOSEL_R::new(((self.bits >> 24) & 7) as u8) } #[doc = "Bits 28:30 - Microcontroller clock output prescaler"] #[inline(always)] pub fn mcopre(&self) -> MCOPRE_R { MCOPRE_R::new(((self.bits >> 28) & 7) as u8) } } impl W { #[doc = "Bits 0:2 - System clock switch"] #[inline(always)] #[must_use] pub fn sw(&mut self) -> SW_W<0> { SW_W::new(self) } #[doc = "Bits 8:11 - AHB prescaler"] #[inline(always)] #[must_use] pub fn hpre(&mut self) -> HPRE_W<8> { HPRE_W::new(self) } #[doc = "Bits 12:14 - APB prescaler"] #[inline(always)] #[must_use] pub fn ppre(&mut self) -> PPRE_W<12> { PPRE_W::new(self) } #[doc = "Bits 24:26 - Microcontroller clock output"] #[inline(always)] #[must_use] pub fn mcosel(&mut self) -> MCOSEL_W<24> { MCOSEL_W::new(self) } #[doc = "Bits 28:30 - Microcontroller clock output prescaler"] #[inline(always)] #[must_use] pub fn mcopre(&mut self) -> MCOPRE_W<28> { MCOPRE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Clock configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"] pub struct CFGR_SPEC; impl crate::RegisterSpec for CFGR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr::R](R) reader structure"] impl crate::Readable for CFGR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"] impl crate::Writable for CFGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR to value 0"] impl crate::Resettable for CFGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PLLCFGR (rw) register accessor: an alias for `Reg`"] pub type PLLCFGR = crate::Reg; #[doc = "PLL configuration register"] pub mod pllcfgr { #[doc = "Register `PLLCFGR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PLLCFGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PLLSRC` reader - PLL clock source selection"] pub type PLLSRC_R = crate::BitReader; #[doc = "Field `PLLSRC` writer - PLL clock source selection"] pub type PLLSRC_W<'a, const O: u8> = crate::BitWriter<'a, PLLCFGR_SPEC, O>; impl R { #[doc = "Bit 0 - PLL clock source selection"] #[inline(always)] pub fn pllsrc(&self) -> PLLSRC_R { PLLSRC_R::new((self.bits & 1) != 0) } } impl W { #[doc = "Bit 0 - PLL clock source selection"] #[inline(always)] #[must_use] pub fn pllsrc(&mut self) -> PLLSRC_W<0> { PLLSRC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "PLL configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pllcfgr](index.html) module"] pub struct PLLCFGR_SPEC; impl crate::RegisterSpec for PLLCFGR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pllcfgr::R](R) reader structure"] impl crate::Readable for PLLCFGR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pllcfgr::W](W) writer structure"] impl crate::Writable for PLLCFGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PLLCFGR to value 0"] impl crate::Resettable for PLLCFGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ECSCR (rw) register accessor: an alias for `Reg`"] pub type ECSCR = crate::Reg; #[doc = "External clock source control register"] pub mod ecscr { #[doc = "Register `ECSCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ECSCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `HSE_FREQ` reader - HSE clock freqency selection"] pub type HSE_FREQ_R = crate::FieldReader; #[doc = "Field `HSE_FREQ` writer - HSE clock freqency selection"] pub type HSE_FREQ_W<'a, const O: u8> = crate::FieldWriter<'a, ECSCR_SPEC, 2, O>; #[doc = "Field `LSE_DRIVER` reader - LSE clock driver selection"] pub type LSE_DRIVER_R = crate::FieldReader; #[doc = "Field `LSE_DRIVER` writer - LSE clock driver selection"] pub type LSE_DRIVER_W<'a, const O: u8> = crate::FieldWriter<'a, ECSCR_SPEC, 2, O>; impl R { #[doc = "Bits 2:3 - HSE clock freqency selection"] #[inline(always)] pub fn hse_freq(&self) -> HSE_FREQ_R { HSE_FREQ_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 16:17 - LSE clock driver selection"] #[inline(always)] pub fn lse_driver(&self) -> LSE_DRIVER_R { LSE_DRIVER_R::new(((self.bits >> 16) & 3) as u8) } } impl W { #[doc = "Bits 2:3 - HSE clock freqency selection"] #[inline(always)] #[must_use] pub fn hse_freq(&mut self) -> HSE_FREQ_W<2> { HSE_FREQ_W::new(self) } #[doc = "Bits 16:17 - LSE clock driver selection"] #[inline(always)] #[must_use] pub fn lse_driver(&mut self) -> LSE_DRIVER_W<16> { LSE_DRIVER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "External clock source control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecscr](index.html) module"] pub struct ECSCR_SPEC; impl crate::RegisterSpec for ECSCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ecscr::R](R) reader structure"] impl crate::Readable for ECSCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ecscr::W](W) writer structure"] impl crate::Writable for ECSCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ECSCR to value 0"] impl crate::Resettable for ECSCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CIER (rw) register accessor: an alias for `Reg`"] pub type CIER = crate::Reg; #[doc = "Clock interrupt enable register"] pub mod cier { #[doc = "Register `CIER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CIER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LSIRDYIE` reader - LSI ready interrupt enable"] pub type LSIRDYIE_R = crate::BitReader; #[doc = "Field `LSIRDYIE` writer - LSI ready interrupt enable"] pub type LSIRDYIE_W<'a, const O: u8> = crate::BitWriter<'a, CIER_SPEC, O>; #[doc = "Field `LSERDYIE` reader - LSE ready interrupt enable"] pub type LSERDYIE_R = crate::BitReader; #[doc = "Field `LSERDYIE` writer - LSE ready interrupt enable"] pub type LSERDYIE_W<'a, const O: u8> = crate::BitWriter<'a, CIER_SPEC, O>; #[doc = "Field `HSIRDYIE` reader - HSI ready interrupt enable"] pub type HSIRDYIE_R = crate::BitReader; #[doc = "Field `HSIRDYIE` writer - HSI ready interrupt enable"] pub type HSIRDYIE_W<'a, const O: u8> = crate::BitWriter<'a, CIER_SPEC, O>; #[doc = "Field `HSERDYIE` reader - HSE ready interrupt enable"] pub type HSERDYIE_R = crate::BitReader; #[doc = "Field `HSERDYIE` writer - HSE ready interrupt enable"] pub type HSERDYIE_W<'a, const O: u8> = crate::BitWriter<'a, CIER_SPEC, O>; #[doc = "Field `PLLRDYIE` reader - PLL ready interrupt enable"] pub type PLLRDYIE_R = crate::BitReader; #[doc = "Field `PLLRDYIE` writer - PLL ready interrupt enable"] pub type PLLRDYIE_W<'a, const O: u8> = crate::BitWriter<'a, CIER_SPEC, O>; impl R { #[doc = "Bit 0 - LSI ready interrupt enable"] #[inline(always)] pub fn lsirdyie(&self) -> LSIRDYIE_R { LSIRDYIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - LSE ready interrupt enable"] #[inline(always)] pub fn lserdyie(&self) -> LSERDYIE_R { LSERDYIE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 3 - HSI ready interrupt enable"] #[inline(always)] pub fn hsirdyie(&self) -> HSIRDYIE_R { HSIRDYIE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - HSE ready interrupt enable"] #[inline(always)] pub fn hserdyie(&self) -> HSERDYIE_R { HSERDYIE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - PLL ready interrupt enable"] #[inline(always)] pub fn pllrdyie(&self) -> PLLRDYIE_R { PLLRDYIE_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - LSI ready interrupt enable"] #[inline(always)] #[must_use] pub fn lsirdyie(&mut self) -> LSIRDYIE_W<0> { LSIRDYIE_W::new(self) } #[doc = "Bit 1 - LSE ready interrupt enable"] #[inline(always)] #[must_use] pub fn lserdyie(&mut self) -> LSERDYIE_W<1> { LSERDYIE_W::new(self) } #[doc = "Bit 3 - HSI ready interrupt enable"] #[inline(always)] #[must_use] pub fn hsirdyie(&mut self) -> HSIRDYIE_W<3> { HSIRDYIE_W::new(self) } #[doc = "Bit 4 - HSE ready interrupt enable"] #[inline(always)] #[must_use] pub fn hserdyie(&mut self) -> HSERDYIE_W<4> { HSERDYIE_W::new(self) } #[doc = "Bit 5 - PLL ready interrupt enable"] #[inline(always)] #[must_use] pub fn pllrdyie(&mut self) -> PLLRDYIE_W<5> { PLLRDYIE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Clock interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cier](index.html) module"] pub struct CIER_SPEC; impl crate::RegisterSpec for CIER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cier::R](R) reader structure"] impl crate::Readable for CIER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cier::W](W) writer structure"] impl crate::Writable for CIER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CIER to value 0"] impl crate::Resettable for CIER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CIFR (r) register accessor: an alias for `Reg`"] pub type CIFR = crate::Reg; #[doc = "Clock interrupt flag register"] pub mod cifr { #[doc = "Register `CIFR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `LSIRDYF` reader - LSI ready interrupt flag"] pub type LSIRDYF_R = crate::BitReader; #[doc = "Field `LSERDYF` reader - LSE ready interrupt flag"] pub type LSERDYF_R = crate::BitReader; #[doc = "Field `HSIRDYF` reader - HSI ready interrupt flag"] pub type HSIRDYF_R = crate::BitReader; #[doc = "Field `HSERDYF` reader - HSE ready interrupt flag"] pub type HSERDYF_R = crate::BitReader; #[doc = "Field `PLLRDYF` reader - PLL ready interrupt flag"] pub type PLLRDYF_R = crate::BitReader; #[doc = "Field `CSSF` reader - HSE clock secure system interrupt flag"] pub type CSSF_R = crate::BitReader; #[doc = "Field `LSECSSF` reader - LSE clock secure system interrupt flag"] pub type LSECSSF_R = crate::BitReader; impl R { #[doc = "Bit 0 - LSI ready interrupt flag"] #[inline(always)] pub fn lsirdyf(&self) -> LSIRDYF_R { LSIRDYF_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - LSE ready interrupt flag"] #[inline(always)] pub fn lserdyf(&self) -> LSERDYF_R { LSERDYF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 3 - HSI ready interrupt flag"] #[inline(always)] pub fn hsirdyf(&self) -> HSIRDYF_R { HSIRDYF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - HSE ready interrupt flag"] #[inline(always)] pub fn hserdyf(&self) -> HSERDYF_R { HSERDYF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - PLL ready interrupt flag"] #[inline(always)] pub fn pllrdyf(&self) -> PLLRDYF_R { PLLRDYF_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 8 - HSE clock secure system interrupt flag"] #[inline(always)] pub fn cssf(&self) -> CSSF_R { CSSF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - LSE clock secure system interrupt flag"] #[inline(always)] pub fn lsecssf(&self) -> LSECSSF_R { LSECSSF_R::new(((self.bits >> 9) & 1) != 0) } } #[doc = "Clock interrupt flag register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cifr](index.html) module"] pub struct CIFR_SPEC; impl crate::RegisterSpec for CIFR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cifr::R](R) reader structure"] impl crate::Readable for CIFR_SPEC { type Reader = R; } #[doc = "`reset()` method sets CIFR to value 0"] impl crate::Resettable for CIFR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CICR (w) register accessor: an alias for `Reg`"] pub type CICR = crate::Reg; #[doc = "Clock interrupt clear register"] pub mod cicr { #[doc = "Register `CICR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LSIRDYC` writer - LSI ready interrupt clear"] pub type LSIRDYC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; #[doc = "Field `LSERDYC` writer - LSE ready interrupt clear"] pub type LSERDYC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; #[doc = "Field `HSIRDYC` writer - HSI ready interrupt clear"] pub type HSIRDYC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; #[doc = "Field `HSERDYC` writer - HSE ready interrupt clear"] pub type HSERDYC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; #[doc = "Field `PLLRDYC` writer - PLL ready interrupt clear"] pub type PLLRDYC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; #[doc = "Field `CSSC` writer - clock secure system interrupt flag clear"] pub type CSSC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; #[doc = "Field `LSECSSC` writer - LSE clock secure system interrupt flag clear"] pub type LSECSSC_W<'a, const O: u8> = crate::BitWriter<'a, CICR_SPEC, O>; impl W { #[doc = "Bit 0 - LSI ready interrupt clear"] #[inline(always)] #[must_use] pub fn lsirdyc(&mut self) -> LSIRDYC_W<0> { LSIRDYC_W::new(self) } #[doc = "Bit 1 - LSE ready interrupt clear"] #[inline(always)] #[must_use] pub fn lserdyc(&mut self) -> LSERDYC_W<1> { LSERDYC_W::new(self) } #[doc = "Bit 3 - HSI ready interrupt clear"] #[inline(always)] #[must_use] pub fn hsirdyc(&mut self) -> HSIRDYC_W<3> { HSIRDYC_W::new(self) } #[doc = "Bit 4 - HSE ready interrupt clear"] #[inline(always)] #[must_use] pub fn hserdyc(&mut self) -> HSERDYC_W<4> { HSERDYC_W::new(self) } #[doc = "Bit 5 - PLL ready interrupt clear"] #[inline(always)] #[must_use] pub fn pllrdyc(&mut self) -> PLLRDYC_W<5> { PLLRDYC_W::new(self) } #[doc = "Bit 8 - clock secure system interrupt flag clear"] #[inline(always)] #[must_use] pub fn cssc(&mut self) -> CSSC_W<8> { CSSC_W::new(self) } #[doc = "Bit 9 - LSE clock secure system interrupt flag clear"] #[inline(always)] #[must_use] pub fn lsecssc(&mut self) -> LSECSSC_W<9> { LSECSSC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Clock interrupt clear register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cicr](index.html) module"] pub struct CICR_SPEC; impl crate::RegisterSpec for CICR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [cicr::W](W) writer structure"] impl crate::Writable for CICR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CICR to value 0"] impl crate::Resettable for CICR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IOPRSTR (rw) register accessor: an alias for `Reg`"] pub type IOPRSTR = crate::Reg; #[doc = "GPIO reset register"] pub mod ioprstr { #[doc = "Register `IOPRSTR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IOPRSTR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `GPIOARST` reader - I/O port A reset"] pub type GPIOARST_R = crate::BitReader; #[doc = "Field `GPIOARST` writer - I/O port A reset"] pub type GPIOARST_W<'a, const O: u8> = crate::BitWriter<'a, IOPRSTR_SPEC, O>; #[doc = "Field `GPIOBRST` reader - I/O port B reset"] pub type GPIOBRST_R = crate::BitReader; #[doc = "Field `GPIOBRST` writer - I/O port B reset"] pub type GPIOBRST_W<'a, const O: u8> = crate::BitWriter<'a, IOPRSTR_SPEC, O>; #[doc = "Field `GPIOFRST` reader - I/O port F reset"] pub type GPIOFRST_R = crate::BitReader; #[doc = "Field `GPIOFRST` writer - I/O port F reset"] pub type GPIOFRST_W<'a, const O: u8> = crate::BitWriter<'a, IOPRSTR_SPEC, O>; impl R { #[doc = "Bit 0 - I/O port A reset"] #[inline(always)] pub fn gpioarst(&self) -> GPIOARST_R { GPIOARST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - I/O port B reset"] #[inline(always)] pub fn gpiobrst(&self) -> GPIOBRST_R { GPIOBRST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 5 - I/O port F reset"] #[inline(always)] pub fn gpiofrst(&self) -> GPIOFRST_R { GPIOFRST_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - I/O port A reset"] #[inline(always)] #[must_use] pub fn gpioarst(&mut self) -> GPIOARST_W<0> { GPIOARST_W::new(self) } #[doc = "Bit 1 - I/O port B reset"] #[inline(always)] #[must_use] pub fn gpiobrst(&mut self) -> GPIOBRST_W<1> { GPIOBRST_W::new(self) } #[doc = "Bit 5 - I/O port F reset"] #[inline(always)] #[must_use] pub fn gpiofrst(&mut self) -> GPIOFRST_W<5> { GPIOFRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ioprstr](index.html) module"] pub struct IOPRSTR_SPEC; impl crate::RegisterSpec for IOPRSTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ioprstr::R](R) reader structure"] impl crate::Readable for IOPRSTR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ioprstr::W](W) writer structure"] impl crate::Writable for IOPRSTR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IOPRSTR to value 0"] impl crate::Resettable for IOPRSTR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "AHBRSTR (rw) register accessor: an alias for `Reg`"] pub type AHBRSTR = crate::Reg; #[doc = "AHB peripheral reset register"] pub mod ahbrstr { #[doc = "Register `AHBRSTR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `AHBRSTR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMARST` reader - DMA reset"] pub type DMARST_R = crate::BitReader; #[doc = "Field `DMARST` writer - DMA reset"] pub type DMARST_W<'a, const O: u8> = crate::BitWriter<'a, AHBRSTR_SPEC, O>; #[doc = "Field `CRCRST` reader - CRC reset"] pub type CRCRST_R = crate::BitReader; #[doc = "Field `CRCRST` writer - CRC reset"] pub type CRCRST_W<'a, const O: u8> = crate::BitWriter<'a, AHBRSTR_SPEC, O>; impl R { #[doc = "Bit 0 - DMA reset"] #[inline(always)] pub fn dmarst(&self) -> DMARST_R { DMARST_R::new((self.bits & 1) != 0) } #[doc = "Bit 12 - CRC reset"] #[inline(always)] pub fn crcrst(&self) -> CRCRST_R { CRCRST_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - DMA reset"] #[inline(always)] #[must_use] pub fn dmarst(&mut self) -> DMARST_W<0> { DMARST_W::new(self) } #[doc = "Bit 12 - CRC reset"] #[inline(always)] #[must_use] pub fn crcrst(&mut self) -> CRCRST_W<12> { CRCRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "AHB peripheral reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbrstr](index.html) module"] pub struct AHBRSTR_SPEC; impl crate::RegisterSpec for AHBRSTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ahbrstr::R](R) reader structure"] impl crate::Readable for AHBRSTR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ahbrstr::W](W) writer structure"] impl crate::Writable for AHBRSTR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets AHBRSTR to value 0"] impl crate::Resettable for AHBRSTR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "APBRSTR1 (rw) register accessor: an alias for `Reg`"] pub type APBRSTR1 = crate::Reg; #[doc = "APB peripheral reset register 1"] pub mod apbrstr1 { #[doc = "Register `APBRSTR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `APBRSTR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TIM3RST` reader - TIM3 timer reset"] pub type TIM3RST_R = crate::BitReader; #[doc = "Field `TIM3RST` writer - TIM3 timer reset"] pub type TIM3RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; #[doc = "Field `SPI2RST` reader - SPI2 reset"] pub type SPI2RST_R = crate::BitReader; #[doc = "Field `SPI2RST` writer - SPI2 reset"] pub type SPI2RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; #[doc = "Field `USART2RST` reader - USART2 reset"] pub type USART2RST_R = crate::BitReader; #[doc = "Field `USART2RST` writer - USART2 reset"] pub type USART2RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; #[doc = "Field `I2CRST` reader - I2C reset"] pub type I2CRST_R = crate::BitReader; #[doc = "Field `I2CRST` writer - I2C reset"] pub type I2CRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; #[doc = "Field `DBGRST` reader - Debug support reset"] pub type DBGRST_R = crate::BitReader; #[doc = "Field `DBGRST` writer - Debug support reset"] pub type DBGRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; #[doc = "Field `PWRRST` reader - Power interface reset"] pub type PWRRST_R = crate::BitReader; #[doc = "Field `PWRRST` writer - Power interface reset"] pub type PWRRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; #[doc = "Field `LPTIMRST` reader - Low Power Timer reset"] pub type LPTIMRST_R = crate::BitReader; #[doc = "Field `LPTIMRST` writer - Low Power Timer reset"] pub type LPTIMRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR1_SPEC, O>; impl R { #[doc = "Bit 1 - TIM3 timer reset"] #[inline(always)] pub fn tim3rst(&self) -> TIM3RST_R { TIM3RST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 14 - SPI2 reset"] #[inline(always)] pub fn spi2rst(&self) -> SPI2RST_R { SPI2RST_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 17 - USART2 reset"] #[inline(always)] pub fn usart2rst(&self) -> USART2RST_R { USART2RST_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 21 - I2C reset"] #[inline(always)] pub fn i2crst(&self) -> I2CRST_R { I2CRST_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 27 - Debug support reset"] #[inline(always)] pub fn dbgrst(&self) -> DBGRST_R { DBGRST_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - Power interface reset"] #[inline(always)] pub fn pwrrst(&self) -> PWRRST_R { PWRRST_R::new(((self.bits >> 28) & 1) != 0) } #[doc = "Bit 31 - Low Power Timer reset"] #[inline(always)] pub fn lptimrst(&self) -> LPTIMRST_R { LPTIMRST_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 1 - TIM3 timer reset"] #[inline(always)] #[must_use] pub fn tim3rst(&mut self) -> TIM3RST_W<1> { TIM3RST_W::new(self) } #[doc = "Bit 14 - SPI2 reset"] #[inline(always)] #[must_use] pub fn spi2rst(&mut self) -> SPI2RST_W<14> { SPI2RST_W::new(self) } #[doc = "Bit 17 - USART2 reset"] #[inline(always)] #[must_use] pub fn usart2rst(&mut self) -> USART2RST_W<17> { USART2RST_W::new(self) } #[doc = "Bit 21 - I2C reset"] #[inline(always)] #[must_use] pub fn i2crst(&mut self) -> I2CRST_W<21> { I2CRST_W::new(self) } #[doc = "Bit 27 - Debug support reset"] #[inline(always)] #[must_use] pub fn dbgrst(&mut self) -> DBGRST_W<27> { DBGRST_W::new(self) } #[doc = "Bit 28 - Power interface reset"] #[inline(always)] #[must_use] pub fn pwrrst(&mut self) -> PWRRST_W<28> { PWRRST_W::new(self) } #[doc = "Bit 31 - Low Power Timer reset"] #[inline(always)] #[must_use] pub fn lptimrst(&mut self) -> LPTIMRST_W<31> { LPTIMRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "APB peripheral reset register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbrstr1](index.html) module"] pub struct APBRSTR1_SPEC; impl crate::RegisterSpec for APBRSTR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [apbrstr1::R](R) reader structure"] impl crate::Readable for APBRSTR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [apbrstr1::W](W) writer structure"] impl crate::Writable for APBRSTR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets APBRSTR1 to value 0"] impl crate::Resettable for APBRSTR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "APBRSTR2 (rw) register accessor: an alias for `Reg`"] pub type APBRSTR2 = crate::Reg; #[doc = "APB peripheral reset register 2"] pub mod apbrstr2 { #[doc = "Register `APBRSTR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `APBRSTR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SYSCFGRST` reader - SYSCFG and COMP reset"] pub type SYSCFGRST_R = crate::BitReader; #[doc = "Field `SYSCFGRST` writer - SYSCFG and COMP reset"] pub type SYSCFGRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `TIM1RST` reader - TIM1 timer reset"] pub type TIM1RST_R = crate::BitReader; #[doc = "Field `TIM1RST` writer - TIM1 timer reset"] pub type TIM1RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `SPI1RST` reader - SPI1 reset"] pub type SPI1RST_R = crate::BitReader; #[doc = "Field `SPI1RST` writer - SPI1 reset"] pub type SPI1RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `USART1RST` reader - USART1 reset"] pub type USART1RST_R = crate::BitReader; #[doc = "Field `USART1RST` writer - USART1 reset"] pub type USART1RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `TIM14RST` reader - TIM14 timer reset"] pub type TIM14RST_R = crate::BitReader; #[doc = "Field `TIM14RST` writer - TIM14 timer reset"] pub type TIM14RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `TIM16RST` reader - TIM16 timer reset"] pub type TIM16RST_R = crate::BitReader; #[doc = "Field `TIM16RST` writer - TIM16 timer reset"] pub type TIM16RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `TIM17RST` reader - TIM17 timer reset"] pub type TIM17RST_R = crate::BitReader; #[doc = "Field `TIM17RST` writer - TIM17 timer reset"] pub type TIM17RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `ADCRST` reader - ADC reset"] pub type ADCRST_R = crate::BitReader; #[doc = "Field `ADCRST` writer - ADC reset"] pub type ADCRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `COMP1RST` reader - COMP1 reset"] pub type COMP1RST_R = crate::BitReader; #[doc = "Field `COMP1RST` writer - COMP1 reset"] pub type COMP1RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `COMP2RST` reader - COMP2 reset"] pub type COMP2RST_R = crate::BitReader; #[doc = "Field `COMP2RST` writer - COMP2 reset"] pub type COMP2RST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; #[doc = "Field `LEDRST` reader - LED reset"] pub type LEDRST_R = crate::BitReader; #[doc = "Field `LEDRST` writer - LED reset"] pub type LEDRST_W<'a, const O: u8> = crate::BitWriter<'a, APBRSTR2_SPEC, O>; impl R { #[doc = "Bit 0 - SYSCFG and COMP reset"] #[inline(always)] pub fn syscfgrst(&self) -> SYSCFGRST_R { SYSCFGRST_R::new((self.bits & 1) != 0) } #[doc = "Bit 11 - TIM1 timer reset"] #[inline(always)] pub fn tim1rst(&self) -> TIM1RST_R { TIM1RST_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - SPI1 reset"] #[inline(always)] pub fn spi1rst(&self) -> SPI1RST_R { SPI1RST_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 14 - USART1 reset"] #[inline(always)] pub fn usart1rst(&self) -> USART1RST_R { USART1RST_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - TIM14 timer reset"] #[inline(always)] pub fn tim14rst(&self) -> TIM14RST_R { TIM14RST_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 17 - TIM16 timer reset"] #[inline(always)] pub fn tim16rst(&self) -> TIM16RST_R { TIM16RST_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - TIM17 timer reset"] #[inline(always)] pub fn tim17rst(&self) -> TIM17RST_R { TIM17RST_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 20 - ADC reset"] #[inline(always)] pub fn adcrst(&self) -> ADCRST_R { ADCRST_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - COMP1 reset"] #[inline(always)] pub fn comp1rst(&self) -> COMP1RST_R { COMP1RST_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - COMP2 reset"] #[inline(always)] pub fn comp2rst(&self) -> COMP2RST_R { COMP2RST_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - LED reset"] #[inline(always)] pub fn ledrst(&self) -> LEDRST_R { LEDRST_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bit 0 - SYSCFG and COMP reset"] #[inline(always)] #[must_use] pub fn syscfgrst(&mut self) -> SYSCFGRST_W<0> { SYSCFGRST_W::new(self) } #[doc = "Bit 11 - TIM1 timer reset"] #[inline(always)] #[must_use] pub fn tim1rst(&mut self) -> TIM1RST_W<11> { TIM1RST_W::new(self) } #[doc = "Bit 12 - SPI1 reset"] #[inline(always)] #[must_use] pub fn spi1rst(&mut self) -> SPI1RST_W<12> { SPI1RST_W::new(self) } #[doc = "Bit 14 - USART1 reset"] #[inline(always)] #[must_use] pub fn usart1rst(&mut self) -> USART1RST_W<14> { USART1RST_W::new(self) } #[doc = "Bit 15 - TIM14 timer reset"] #[inline(always)] #[must_use] pub fn tim14rst(&mut self) -> TIM14RST_W<15> { TIM14RST_W::new(self) } #[doc = "Bit 17 - TIM16 timer reset"] #[inline(always)] #[must_use] pub fn tim16rst(&mut self) -> TIM16RST_W<17> { TIM16RST_W::new(self) } #[doc = "Bit 18 - TIM17 timer reset"] #[inline(always)] #[must_use] pub fn tim17rst(&mut self) -> TIM17RST_W<18> { TIM17RST_W::new(self) } #[doc = "Bit 20 - ADC reset"] #[inline(always)] #[must_use] pub fn adcrst(&mut self) -> ADCRST_W<20> { ADCRST_W::new(self) } #[doc = "Bit 21 - COMP1 reset"] #[inline(always)] #[must_use] pub fn comp1rst(&mut self) -> COMP1RST_W<21> { COMP1RST_W::new(self) } #[doc = "Bit 22 - COMP2 reset"] #[inline(always)] #[must_use] pub fn comp2rst(&mut self) -> COMP2RST_W<22> { COMP2RST_W::new(self) } #[doc = "Bit 23 - LED reset"] #[inline(always)] #[must_use] pub fn ledrst(&mut self) -> LEDRST_W<23> { LEDRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "APB peripheral reset register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbrstr2](index.html) module"] pub struct APBRSTR2_SPEC; impl crate::RegisterSpec for APBRSTR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [apbrstr2::R](R) reader structure"] impl crate::Readable for APBRSTR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [apbrstr2::W](W) writer structure"] impl crate::Writable for APBRSTR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets APBRSTR2 to value 0"] impl crate::Resettable for APBRSTR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IOPENR (rw) register accessor: an alias for `Reg`"] pub type IOPENR = crate::Reg; #[doc = "GPIO clock enable register"] pub mod iopenr { #[doc = "Register `IOPENR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IOPENR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `GPIOAEN` reader - I/O port A clock enable"] pub type GPIOAEN_R = crate::BitReader; #[doc = "Field `GPIOAEN` writer - I/O port A clock enable"] pub type GPIOAEN_W<'a, const O: u8> = crate::BitWriter<'a, IOPENR_SPEC, O>; #[doc = "Field `GPIOBEN` reader - I/O port B clock enable"] pub type GPIOBEN_R = crate::BitReader; #[doc = "Field `GPIOBEN` writer - I/O port B clock enable"] pub type GPIOBEN_W<'a, const O: u8> = crate::BitWriter<'a, IOPENR_SPEC, O>; #[doc = "Field `GPIOFEN` reader - I/O port F clock enable"] pub type GPIOFEN_R = crate::BitReader; #[doc = "Field `GPIOFEN` writer - I/O port F clock enable"] pub type GPIOFEN_W<'a, const O: u8> = crate::BitWriter<'a, IOPENR_SPEC, O>; impl R { #[doc = "Bit 0 - I/O port A clock enable"] #[inline(always)] pub fn gpioaen(&self) -> GPIOAEN_R { GPIOAEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - I/O port B clock enable"] #[inline(always)] pub fn gpioben(&self) -> GPIOBEN_R { GPIOBEN_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 5 - I/O port F clock enable"] #[inline(always)] pub fn gpiofen(&self) -> GPIOFEN_R { GPIOFEN_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - I/O port A clock enable"] #[inline(always)] #[must_use] pub fn gpioaen(&mut self) -> GPIOAEN_W<0> { GPIOAEN_W::new(self) } #[doc = "Bit 1 - I/O port B clock enable"] #[inline(always)] #[must_use] pub fn gpioben(&mut self) -> GPIOBEN_W<1> { GPIOBEN_W::new(self) } #[doc = "Bit 5 - I/O port F clock enable"] #[inline(always)] #[must_use] pub fn gpiofen(&mut self) -> GPIOFEN_W<5> { GPIOFEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iopenr](index.html) module"] pub struct IOPENR_SPEC; impl crate::RegisterSpec for IOPENR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [iopenr::R](R) reader structure"] impl crate::Readable for IOPENR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [iopenr::W](W) writer structure"] impl crate::Writable for IOPENR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IOPENR to value 0"] impl crate::Resettable for IOPENR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "AHBENR (rw) register accessor: an alias for `Reg`"] pub type AHBENR = crate::Reg; #[doc = "AHB peripheral clock enable register"] pub mod ahbenr { #[doc = "Register `AHBENR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `AHBENR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMAEN` reader - DMA clock enable"] pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - DMA clock enable"] pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, AHBENR_SPEC, O>; #[doc = "Field `FLASHEN` reader - Flash memory interface clock enable"] pub type FLASHEN_R = crate::BitReader; #[doc = "Field `FLASHEN` writer - Flash memory interface clock enable"] pub type FLASHEN_W<'a, const O: u8> = crate::BitWriter<'a, AHBENR_SPEC, O>; #[doc = "Field `SRAMEN` reader - SRAM memory interface clock enable"] pub type SRAMEN_R = crate::BitReader; #[doc = "Field `SRAMEN` writer - SRAM memory interface clock enable"] pub type SRAMEN_W<'a, const O: u8> = crate::BitWriter<'a, AHBENR_SPEC, O>; #[doc = "Field `CRCEN` reader - CRC clock enable"] pub type CRCEN_R = crate::BitReader; #[doc = "Field `CRCEN` writer - CRC clock enable"] pub type CRCEN_W<'a, const O: u8> = crate::BitWriter<'a, AHBENR_SPEC, O>; impl R { #[doc = "Bit 0 - DMA clock enable"] #[inline(always)] pub fn dmaen(&self) -> DMAEN_R { DMAEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 8 - Flash memory interface clock enable"] #[inline(always)] pub fn flashen(&self) -> FLASHEN_R { FLASHEN_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - SRAM memory interface clock enable"] #[inline(always)] pub fn sramen(&self) -> SRAMEN_R { SRAMEN_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 12 - CRC clock enable"] #[inline(always)] pub fn crcen(&self) -> CRCEN_R { CRCEN_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - DMA clock enable"] #[inline(always)] #[must_use] pub fn dmaen(&mut self) -> DMAEN_W<0> { DMAEN_W::new(self) } #[doc = "Bit 8 - Flash memory interface clock enable"] #[inline(always)] #[must_use] pub fn flashen(&mut self) -> FLASHEN_W<8> { FLASHEN_W::new(self) } #[doc = "Bit 9 - SRAM memory interface clock enable"] #[inline(always)] #[must_use] pub fn sramen(&mut self) -> SRAMEN_W<9> { SRAMEN_W::new(self) } #[doc = "Bit 12 - CRC clock enable"] #[inline(always)] #[must_use] pub fn crcen(&mut self) -> CRCEN_W<12> { CRCEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "AHB peripheral clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbenr](index.html) module"] pub struct AHBENR_SPEC; impl crate::RegisterSpec for AHBENR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ahbenr::R](R) reader structure"] impl crate::Readable for AHBENR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ahbenr::W](W) writer structure"] impl crate::Writable for AHBENR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets AHBENR to value 0"] impl crate::Resettable for AHBENR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "APBENR1 (rw) register accessor: an alias for `Reg`"] pub type APBENR1 = crate::Reg; #[doc = "APB peripheral clock enable register 1"] pub mod apbenr1 { #[doc = "Register `APBENR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `APBENR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TIM3EN` reader - TIM3 timer clock enable"] pub type TIM3EN_R = crate::BitReader; #[doc = "Field `TIM3EN` writer - TIM3 timer clock enable"] pub type TIM3EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `RTCAPBEN` reader - RTC APB clock enable"] pub type RTCAPBEN_R = crate::BitReader; #[doc = "Field `RTCAPBEN` writer - RTC APB clock enable"] pub type RTCAPBEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `WWDGEN` reader - WWDG clock enable"] pub type WWDGEN_R = crate::BitReader; #[doc = "Field `WWDGEN` writer - WWDG clock enable"] pub type WWDGEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `SPI2EN` reader - SPI2 clock enable"] pub type SPI2EN_R = crate::BitReader; #[doc = "Field `SPI2EN` writer - SPI2 clock enable"] pub type SPI2EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `USART2EN` reader - USART2 clock enable"] pub type USART2EN_R = crate::BitReader; #[doc = "Field `USART2EN` writer - USART2 clock enable"] pub type USART2EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `I2CEN` reader - I2C clock enable"] pub type I2CEN_R = crate::BitReader; #[doc = "Field `I2CEN` writer - I2C clock enable"] pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `DBGEN` reader - Debug support clock enable"] pub type DBGEN_R = crate::BitReader; #[doc = "Field `DBGEN` writer - Debug support clock enable"] pub type DBGEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `PWREN` reader - Power interface clock enable"] pub type PWREN_R = crate::BitReader; #[doc = "Field `PWREN` writer - Power interface clock enable"] pub type PWREN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; #[doc = "Field `LPTIMEN` reader - LPTIM clock enable"] pub type LPTIMEN_R = crate::BitReader; #[doc = "Field `LPTIMEN` writer - LPTIM clock enable"] pub type LPTIMEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR1_SPEC, O>; impl R { #[doc = "Bit 1 - TIM3 timer clock enable"] #[inline(always)] pub fn tim3en(&self) -> TIM3EN_R { TIM3EN_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 10 - RTC APB clock enable"] #[inline(always)] pub fn rtcapben(&self) -> RTCAPBEN_R { RTCAPBEN_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - WWDG clock enable"] #[inline(always)] pub fn wwdgen(&self) -> WWDGEN_R { WWDGEN_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 14 - SPI2 clock enable"] #[inline(always)] pub fn spi2en(&self) -> SPI2EN_R { SPI2EN_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 17 - USART2 clock enable"] #[inline(always)] pub fn usart2en(&self) -> USART2EN_R { USART2EN_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 21 - I2C clock enable"] #[inline(always)] pub fn i2cen(&self) -> I2CEN_R { I2CEN_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 27 - Debug support clock enable"] #[inline(always)] pub fn dbgen(&self) -> DBGEN_R { DBGEN_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - Power interface clock enable"] #[inline(always)] pub fn pwren(&self) -> PWREN_R { PWREN_R::new(((self.bits >> 28) & 1) != 0) } #[doc = "Bit 31 - LPTIM clock enable"] #[inline(always)] pub fn lptimen(&self) -> LPTIMEN_R { LPTIMEN_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 1 - TIM3 timer clock enable"] #[inline(always)] #[must_use] pub fn tim3en(&mut self) -> TIM3EN_W<1> { TIM3EN_W::new(self) } #[doc = "Bit 10 - RTC APB clock enable"] #[inline(always)] #[must_use] pub fn rtcapben(&mut self) -> RTCAPBEN_W<10> { RTCAPBEN_W::new(self) } #[doc = "Bit 11 - WWDG clock enable"] #[inline(always)] #[must_use] pub fn wwdgen(&mut self) -> WWDGEN_W<11> { WWDGEN_W::new(self) } #[doc = "Bit 14 - SPI2 clock enable"] #[inline(always)] #[must_use] pub fn spi2en(&mut self) -> SPI2EN_W<14> { SPI2EN_W::new(self) } #[doc = "Bit 17 - USART2 clock enable"] #[inline(always)] #[must_use] pub fn usart2en(&mut self) -> USART2EN_W<17> { USART2EN_W::new(self) } #[doc = "Bit 21 - I2C clock enable"] #[inline(always)] #[must_use] pub fn i2cen(&mut self) -> I2CEN_W<21> { I2CEN_W::new(self) } #[doc = "Bit 27 - Debug support clock enable"] #[inline(always)] #[must_use] pub fn dbgen(&mut self) -> DBGEN_W<27> { DBGEN_W::new(self) } #[doc = "Bit 28 - Power interface clock enable"] #[inline(always)] #[must_use] pub fn pwren(&mut self) -> PWREN_W<28> { PWREN_W::new(self) } #[doc = "Bit 31 - LPTIM clock enable"] #[inline(always)] #[must_use] pub fn lptimen(&mut self) -> LPTIMEN_W<31> { LPTIMEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "APB peripheral clock enable register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbenr1](index.html) module"] pub struct APBENR1_SPEC; impl crate::RegisterSpec for APBENR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [apbenr1::R](R) reader structure"] impl crate::Readable for APBENR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [apbenr1::W](W) writer structure"] impl crate::Writable for APBENR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets APBENR1 to value 0"] impl crate::Resettable for APBENR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "APBENR2 (rw) register accessor: an alias for `Reg`"] pub type APBENR2 = crate::Reg; #[doc = "APB peripheral clock enable register 2"] pub mod apbenr2 { #[doc = "Register `APBENR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `APBENR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SYSCFGEN` reader - SYSCFG, COMP and VREFBUF clock enable"] pub type SYSCFGEN_R = crate::BitReader; #[doc = "Field `SYSCFGEN` writer - SYSCFG, COMP and VREFBUF clock enable"] pub type SYSCFGEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `TIM1EN` reader - TIM1 timer clock enable"] pub type TIM1EN_R = crate::BitReader; #[doc = "Field `TIM1EN` writer - TIM1 timer clock enable"] pub type TIM1EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `SPI1EN` reader - SPI1 clock enable"] pub type SPI1EN_R = crate::BitReader; #[doc = "Field `SPI1EN` writer - SPI1 clock enable"] pub type SPI1EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `USART1EN` reader - USART1 clock enable"] pub type USART1EN_R = crate::BitReader; #[doc = "Field `USART1EN` writer - USART1 clock enable"] pub type USART1EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `TIM14EN` reader - TIM14 timer clock enable"] pub type TIM14EN_R = crate::BitReader; #[doc = "Field `TIM14EN` writer - TIM14 timer clock enable"] pub type TIM14EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `TIM16EN` reader - TIM16 timer clock enable"] pub type TIM16EN_R = crate::BitReader; #[doc = "Field `TIM16EN` writer - TIM16 timer clock enable"] pub type TIM16EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `TIM17EN` reader - TIM16 timer clock enable"] pub type TIM17EN_R = crate::BitReader; #[doc = "Field `TIM17EN` writer - TIM16 timer clock enable"] pub type TIM17EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `ADCEN` reader - ADC clock enable"] pub type ADCEN_R = crate::BitReader; #[doc = "Field `ADCEN` writer - ADC clock enable"] pub type ADCEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `COMP1EN` reader - COMP1 clock enable"] pub type COMP1EN_R = crate::BitReader; #[doc = "Field `COMP1EN` writer - COMP1 clock enable"] pub type COMP1EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `COMP2EN` reader - COMP2 clock enable"] pub type COMP2EN_R = crate::BitReader; #[doc = "Field `COMP2EN` writer - COMP2 clock enable"] pub type COMP2EN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; #[doc = "Field `LEDEN` reader - LED clock enable"] pub type LEDEN_R = crate::BitReader; #[doc = "Field `LEDEN` writer - LED clock enable"] pub type LEDEN_W<'a, const O: u8> = crate::BitWriter<'a, APBENR2_SPEC, O>; impl R { #[doc = "Bit 0 - SYSCFG, COMP and VREFBUF clock enable"] #[inline(always)] pub fn syscfgen(&self) -> SYSCFGEN_R { SYSCFGEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 11 - TIM1 timer clock enable"] #[inline(always)] pub fn tim1en(&self) -> TIM1EN_R { TIM1EN_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - SPI1 clock enable"] #[inline(always)] pub fn spi1en(&self) -> SPI1EN_R { SPI1EN_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 14 - USART1 clock enable"] #[inline(always)] pub fn usart1en(&self) -> USART1EN_R { USART1EN_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - TIM14 timer clock enable"] #[inline(always)] pub fn tim14en(&self) -> TIM14EN_R { TIM14EN_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 17 - TIM16 timer clock enable"] #[inline(always)] pub fn tim16en(&self) -> TIM16EN_R { TIM16EN_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - TIM16 timer clock enable"] #[inline(always)] pub fn tim17en(&self) -> TIM17EN_R { TIM17EN_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 20 - ADC clock enable"] #[inline(always)] pub fn adcen(&self) -> ADCEN_R { ADCEN_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - COMP1 clock enable"] #[inline(always)] pub fn comp1en(&self) -> COMP1EN_R { COMP1EN_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - COMP2 clock enable"] #[inline(always)] pub fn comp2en(&self) -> COMP2EN_R { COMP2EN_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - LED clock enable"] #[inline(always)] pub fn leden(&self) -> LEDEN_R { LEDEN_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bit 0 - SYSCFG, COMP and VREFBUF clock enable"] #[inline(always)] #[must_use] pub fn syscfgen(&mut self) -> SYSCFGEN_W<0> { SYSCFGEN_W::new(self) } #[doc = "Bit 11 - TIM1 timer clock enable"] #[inline(always)] #[must_use] pub fn tim1en(&mut self) -> TIM1EN_W<11> { TIM1EN_W::new(self) } #[doc = "Bit 12 - SPI1 clock enable"] #[inline(always)] #[must_use] pub fn spi1en(&mut self) -> SPI1EN_W<12> { SPI1EN_W::new(self) } #[doc = "Bit 14 - USART1 clock enable"] #[inline(always)] #[must_use] pub fn usart1en(&mut self) -> USART1EN_W<14> { USART1EN_W::new(self) } #[doc = "Bit 15 - TIM14 timer clock enable"] #[inline(always)] #[must_use] pub fn tim14en(&mut self) -> TIM14EN_W<15> { TIM14EN_W::new(self) } #[doc = "Bit 17 - TIM16 timer clock enable"] #[inline(always)] #[must_use] pub fn tim16en(&mut self) -> TIM16EN_W<17> { TIM16EN_W::new(self) } #[doc = "Bit 18 - TIM16 timer clock enable"] #[inline(always)] #[must_use] pub fn tim17en(&mut self) -> TIM17EN_W<18> { TIM17EN_W::new(self) } #[doc = "Bit 20 - ADC clock enable"] #[inline(always)] #[must_use] pub fn adcen(&mut self) -> ADCEN_W<20> { ADCEN_W::new(self) } #[doc = "Bit 21 - COMP1 clock enable"] #[inline(always)] #[must_use] pub fn comp1en(&mut self) -> COMP1EN_W<21> { COMP1EN_W::new(self) } #[doc = "Bit 22 - COMP2 clock enable"] #[inline(always)] #[must_use] pub fn comp2en(&mut self) -> COMP2EN_W<22> { COMP2EN_W::new(self) } #[doc = "Bit 23 - LED clock enable"] #[inline(always)] #[must_use] pub fn leden(&mut self) -> LEDEN_W<23> { LEDEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "APB peripheral clock enable register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbenr2](index.html) module"] pub struct APBENR2_SPEC; impl crate::RegisterSpec for APBENR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [apbenr2::R](R) reader structure"] impl crate::Readable for APBENR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [apbenr2::W](W) writer structure"] impl crate::Writable for APBENR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets APBENR2 to value 0"] impl crate::Resettable for APBENR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCIPR (rw) register accessor: an alias for `Reg`"] pub type CCIPR = crate::Reg; #[doc = "Peripherals independent clock configuration register"] pub mod ccipr { #[doc = "Register `CCIPR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCIPR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PVDSEL` reader - PVD detect clock source selection"] pub type PVDSEL_R = crate::BitReader; #[doc = "Field `PVDSEL` writer - PVD detect clock source selection"] pub type PVDSEL_W<'a, const O: u8> = crate::BitWriter<'a, CCIPR_SPEC, O>; #[doc = "Field `COMP1SEL` reader - COMP1 clock source selection"] pub type COMP1SEL_R = crate::BitReader; #[doc = "Field `COMP1SEL` writer - COMP1 clock source selection"] pub type COMP1SEL_W<'a, const O: u8> = crate::BitWriter<'a, CCIPR_SPEC, O>; #[doc = "Field `COMP2SEL` reader - COMP2 clock source selection"] pub type COMP2SEL_R = crate::BitReader; #[doc = "Field `COMP2SEL` writer - COMP2 clock source selection"] pub type COMP2SEL_W<'a, const O: u8> = crate::BitWriter<'a, CCIPR_SPEC, O>; #[doc = "Field `LPTIM1SEL` reader - LPTIM1 clock source selection"] pub type LPTIM1SEL_R = crate::FieldReader; #[doc = "Field `LPTIM1SEL` writer - LPTIM1 clock source selection"] pub type LPTIM1SEL_W<'a, const O: u8> = crate::FieldWriter<'a, CCIPR_SPEC, 2, O>; impl R { #[doc = "Bit 7 - PVD detect clock source selection"] #[inline(always)] pub fn pvdsel(&self) -> PVDSEL_R { PVDSEL_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - COMP1 clock source selection"] #[inline(always)] pub fn comp1sel(&self) -> COMP1SEL_R { COMP1SEL_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - COMP2 clock source selection"] #[inline(always)] pub fn comp2sel(&self) -> COMP2SEL_R { COMP2SEL_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bits 18:19 - LPTIM1 clock source selection"] #[inline(always)] pub fn lptim1sel(&self) -> LPTIM1SEL_R { LPTIM1SEL_R::new(((self.bits >> 18) & 3) as u8) } } impl W { #[doc = "Bit 7 - PVD detect clock source selection"] #[inline(always)] #[must_use] pub fn pvdsel(&mut self) -> PVDSEL_W<7> { PVDSEL_W::new(self) } #[doc = "Bit 8 - COMP1 clock source selection"] #[inline(always)] #[must_use] pub fn comp1sel(&mut self) -> COMP1SEL_W<8> { COMP1SEL_W::new(self) } #[doc = "Bit 9 - COMP2 clock source selection"] #[inline(always)] #[must_use] pub fn comp2sel(&mut self) -> COMP2SEL_W<9> { COMP2SEL_W::new(self) } #[doc = "Bits 18:19 - LPTIM1 clock source selection"] #[inline(always)] #[must_use] pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<18> { LPTIM1SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Peripherals independent clock configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccipr](index.html) module"] pub struct CCIPR_SPEC; impl crate::RegisterSpec for CCIPR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccipr::R](R) reader structure"] impl crate::Readable for CCIPR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccipr::W](W) writer structure"] impl crate::Writable for CCIPR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCIPR to value 0"] impl crate::Resettable for CCIPR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BDCR (rw) register accessor: an alias for `Reg`"] pub type BDCR = crate::Reg; #[doc = "RTC domain control register"] pub mod bdcr { #[doc = "Register `BDCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `BDCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LSEON` reader - LSE oscillator enable"] pub type LSEON_R = crate::BitReader; #[doc = "Field `LSEON` writer - LSE oscillator enable"] pub type LSEON_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `LSERDY` reader - LSE oscillator ready"] pub type LSERDY_R = crate::BitReader; #[doc = "Field `LSERDY` writer - LSE oscillator ready"] pub type LSERDY_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `LSEBYP` reader - LSE oscillator bypass"] pub type LSEBYP_R = crate::BitReader; #[doc = "Field `LSEBYP` writer - LSE oscillator bypass"] pub type LSEBYP_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `LSECSSON` reader - LSE CSS enable"] pub type LSECSSON_R = crate::BitReader; #[doc = "Field `LSECSSON` writer - LSE CSS enable"] pub type LSECSSON_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `LSECSSD` reader - LSE CSS detect"] pub type LSECSSD_R = crate::BitReader; #[doc = "Field `LSECSSD` writer - LSE CSS detect"] pub type LSECSSD_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `RTCSEL` reader - RTC clock source selection"] pub type RTCSEL_R = crate::FieldReader; #[doc = "Field `RTCSEL` writer - RTC clock source selection"] pub type RTCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, BDCR_SPEC, 2, O>; #[doc = "Field `RTCEN` reader - RTC clock source enable"] pub type RTCEN_R = crate::BitReader; #[doc = "Field `RTCEN` writer - RTC clock source enable"] pub type RTCEN_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `BDRST` reader - RTC domain software reset"] pub type BDRST_R = crate::BitReader; #[doc = "Field `BDRST` writer - RTC domain software reset"] pub type BDRST_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `LSCOEN` reader - Low-speed clock output (LSCO) enable"] pub type LSCOEN_R = crate::BitReader; #[doc = "Field `LSCOEN` writer - Low-speed clock output (LSCO) enable"] pub type LSCOEN_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; #[doc = "Field `LSCOSEL` reader - Low-speed clock output selection"] pub type LSCOSEL_R = crate::BitReader; #[doc = "Field `LSCOSEL` writer - Low-speed clock output selection"] pub type LSCOSEL_W<'a, const O: u8> = crate::BitWriter<'a, BDCR_SPEC, O>; impl R { #[doc = "Bit 0 - LSE oscillator enable"] #[inline(always)] pub fn lseon(&self) -> LSEON_R { LSEON_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - LSE oscillator ready"] #[inline(always)] pub fn lserdy(&self) -> LSERDY_R { LSERDY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - LSE oscillator bypass"] #[inline(always)] pub fn lsebyp(&self) -> LSEBYP_R { LSEBYP_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 5 - LSE CSS enable"] #[inline(always)] pub fn lsecsson(&self) -> LSECSSON_R { LSECSSON_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - LSE CSS detect"] #[inline(always)] pub fn lsecssd(&self) -> LSECSSD_R { LSECSSD_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bits 8:9 - RTC clock source selection"] #[inline(always)] pub fn rtcsel(&self) -> RTCSEL_R { RTCSEL_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 15 - RTC clock source enable"] #[inline(always)] pub fn rtcen(&self) -> RTCEN_R { RTCEN_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - RTC domain software reset"] #[inline(always)] pub fn bdrst(&self) -> BDRST_R { BDRST_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 24 - Low-speed clock output (LSCO) enable"] #[inline(always)] pub fn lscoen(&self) -> LSCOEN_R { LSCOEN_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - Low-speed clock output selection"] #[inline(always)] pub fn lscosel(&self) -> LSCOSEL_R { LSCOSEL_R::new(((self.bits >> 25) & 1) != 0) } } impl W { #[doc = "Bit 0 - LSE oscillator enable"] #[inline(always)] #[must_use] pub fn lseon(&mut self) -> LSEON_W<0> { LSEON_W::new(self) } #[doc = "Bit 1 - LSE oscillator ready"] #[inline(always)] #[must_use] pub fn lserdy(&mut self) -> LSERDY_W<1> { LSERDY_W::new(self) } #[doc = "Bit 2 - LSE oscillator bypass"] #[inline(always)] #[must_use] pub fn lsebyp(&mut self) -> LSEBYP_W<2> { LSEBYP_W::new(self) } #[doc = "Bit 5 - LSE CSS enable"] #[inline(always)] #[must_use] pub fn lsecsson(&mut self) -> LSECSSON_W<5> { LSECSSON_W::new(self) } #[doc = "Bit 6 - LSE CSS detect"] #[inline(always)] #[must_use] pub fn lsecssd(&mut self) -> LSECSSD_W<6> { LSECSSD_W::new(self) } #[doc = "Bits 8:9 - RTC clock source selection"] #[inline(always)] #[must_use] pub fn rtcsel(&mut self) -> RTCSEL_W<8> { RTCSEL_W::new(self) } #[doc = "Bit 15 - RTC clock source enable"] #[inline(always)] #[must_use] pub fn rtcen(&mut self) -> RTCEN_W<15> { RTCEN_W::new(self) } #[doc = "Bit 16 - RTC domain software reset"] #[inline(always)] #[must_use] pub fn bdrst(&mut self) -> BDRST_W<16> { BDRST_W::new(self) } #[doc = "Bit 24 - Low-speed clock output (LSCO) enable"] #[inline(always)] #[must_use] pub fn lscoen(&mut self) -> LSCOEN_W<24> { LSCOEN_W::new(self) } #[doc = "Bit 25 - Low-speed clock output selection"] #[inline(always)] #[must_use] pub fn lscosel(&mut self) -> LSCOSEL_W<25> { LSCOSEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC domain control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bdcr](index.html) module"] pub struct BDCR_SPEC; impl crate::RegisterSpec for BDCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [bdcr::R](R) reader structure"] impl crate::Readable for BDCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [bdcr::W](W) writer structure"] impl crate::Writable for BDCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BDCR to value 0"] impl crate::Resettable for BDCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CSR (rw) register accessor: an alias for `Reg`"] pub type CSR = crate::Reg; #[doc = "Control/status register"] pub mod csr { #[doc = "Register `CSR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CSR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LSION` reader - LSI oscillator enable"] pub type LSION_R = crate::BitReader; #[doc = "Field `LSION` writer - LSI oscillator enable"] pub type LSION_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `LSIRDY` reader - LSI oscillator ready"] pub type LSIRDY_R = crate::BitReader; #[doc = "Field `LSIRDY` writer - LSI oscillator ready"] pub type LSIRDY_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `RMVF` reader - Remove reset flags"] pub type RMVF_R = crate::BitReader; #[doc = "Field `RMVF` writer - Remove reset flags"] pub type RMVF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `OBLRSTF` reader - Option byte loader reset flag"] pub type OBLRSTF_R = crate::BitReader; #[doc = "Field `OBLRSTF` writer - Option byte loader reset flag"] pub type OBLRSTF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `PINRSTF` reader - Pin reset flag"] pub type PINRSTF_R = crate::BitReader; #[doc = "Field `PINRSTF` writer - Pin reset flag"] pub type PINRSTF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `PWRRSTF` reader - BOR or POR/PDR flag"] pub type PWRRSTF_R = crate::BitReader; #[doc = "Field `PWRRSTF` writer - BOR or POR/PDR flag"] pub type PWRRSTF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `SFTRSTF` reader - Software reset flag"] pub type SFTRSTF_R = crate::BitReader; #[doc = "Field `SFTRSTF` writer - Software reset flag"] pub type SFTRSTF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `IWDGRSTF` reader - Independent window watchdog reset flag"] pub type IWDGRSTF_R = crate::BitReader; #[doc = "Field `IWDGRSTF` writer - Independent window watchdog reset flag"] pub type IWDGRSTF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; #[doc = "Field `WWDGRSTF` reader - Window watchdog reset flag"] pub type WWDGRSTF_R = crate::BitReader; #[doc = "Field `WWDGRSTF` writer - Window watchdog reset flag"] pub type WWDGRSTF_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; impl R { #[doc = "Bit 0 - LSI oscillator enable"] #[inline(always)] pub fn lsion(&self) -> LSION_R { LSION_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - LSI oscillator ready"] #[inline(always)] pub fn lsirdy(&self) -> LSIRDY_R { LSIRDY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 23 - Remove reset flags"] #[inline(always)] pub fn rmvf(&self) -> RMVF_R { RMVF_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 25 - Option byte loader reset flag"] #[inline(always)] pub fn oblrstf(&self) -> OBLRSTF_R { OBLRSTF_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - Pin reset flag"] #[inline(always)] pub fn pinrstf(&self) -> PINRSTF_R { PINRSTF_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - BOR or POR/PDR flag"] #[inline(always)] pub fn pwrrstf(&self) -> PWRRSTF_R { PWRRSTF_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - Software reset flag"] #[inline(always)] pub fn sftrstf(&self) -> SFTRSTF_R { SFTRSTF_R::new(((self.bits >> 28) & 1) != 0) } #[doc = "Bit 29 - Independent window watchdog reset flag"] #[inline(always)] pub fn iwdgrstf(&self) -> IWDGRSTF_R { IWDGRSTF_R::new(((self.bits >> 29) & 1) != 0) } #[doc = "Bit 30 - Window watchdog reset flag"] #[inline(always)] pub fn wwdgrstf(&self) -> WWDGRSTF_R { WWDGRSTF_R::new(((self.bits >> 30) & 1) != 0) } } impl W { #[doc = "Bit 0 - LSI oscillator enable"] #[inline(always)] #[must_use] pub fn lsion(&mut self) -> LSION_W<0> { LSION_W::new(self) } #[doc = "Bit 1 - LSI oscillator ready"] #[inline(always)] #[must_use] pub fn lsirdy(&mut self) -> LSIRDY_W<1> { LSIRDY_W::new(self) } #[doc = "Bit 23 - Remove reset flags"] #[inline(always)] #[must_use] pub fn rmvf(&mut self) -> RMVF_W<23> { RMVF_W::new(self) } #[doc = "Bit 25 - Option byte loader reset flag"] #[inline(always)] #[must_use] pub fn oblrstf(&mut self) -> OBLRSTF_W<25> { OBLRSTF_W::new(self) } #[doc = "Bit 26 - Pin reset flag"] #[inline(always)] #[must_use] pub fn pinrstf(&mut self) -> PINRSTF_W<26> { PINRSTF_W::new(self) } #[doc = "Bit 27 - BOR or POR/PDR flag"] #[inline(always)] #[must_use] pub fn pwrrstf(&mut self) -> PWRRSTF_W<27> { PWRRSTF_W::new(self) } #[doc = "Bit 28 - Software reset flag"] #[inline(always)] #[must_use] pub fn sftrstf(&mut self) -> SFTRSTF_W<28> { SFTRSTF_W::new(self) } #[doc = "Bit 29 - Independent window watchdog reset flag"] #[inline(always)] #[must_use] pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<29> { IWDGRSTF_W::new(self) } #[doc = "Bit 30 - Window watchdog reset flag"] #[inline(always)] #[must_use] pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<30> { WWDGRSTF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control/status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] pub struct CSR_SPEC; impl crate::RegisterSpec for CSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [csr::R](R) reader structure"] impl crate::Readable for CSR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] impl crate::Writable for CSR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CSR to value 0"] impl crate::Resettable for CSR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Power control"] pub struct PWR { _marker: PhantomData<*const ()>, } unsafe impl Send for PWR {} impl PWR { #[doc = r"Pointer to the register block"] pub const PTR: *const pwr::RegisterBlock = 0x4000_7000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const pwr::RegisterBlock { Self::PTR } } impl Deref for PWR { type Target = pwr::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for PWR { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("PWR").finish() } } #[doc = "Power control"] pub mod pwr { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Power control register 1"] pub cr1: CR1, #[doc = "0x04 - Power control register 2"] pub cr2: CR2, _reserved2: [u8; 0x0c], #[doc = "0x14 - Power status register"] pub sr: SR, } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "Power control register 1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `BIAS_CR` reader - MR Bias current"] pub type BIAS_CR_R = crate::FieldReader; #[doc = "Field `BIAS_CR` writer - MR Bias current"] pub type BIAS_CR_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 4, O>; #[doc = "Field `BIAS_CR_SEL` reader - MR Bias current selection"] pub type BIAS_CR_SEL_R = crate::BitReader; #[doc = "Field `BIAS_CR_SEL` writer - MR Bias current selection"] pub type BIAS_CR_SEL_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `DBP` reader - Disable backup domain write protection"] pub type DBP_R = crate::BitReader; #[doc = "Field `DBP` writer - Disable backup domain write protection"] pub type DBP_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `VOS` reader - Voltage scaling range selection"] pub type VOS_R = crate::BitReader; #[doc = "Field `VOS` writer - Voltage scaling range selection"] pub type VOS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `MRRDY_TIME` reader - Time selection wakeup from LP to VR"] pub type MRRDY_TIME_R = crate::FieldReader; #[doc = "Field `MRRDY_TIME` writer - Time selection wakeup from LP to VR"] pub type MRRDY_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; #[doc = "Field `FLS_SLPTIME` reader - Flash wait time after wakeup from the stop mode"] pub type FLS_SLPTIME_R = crate::FieldReader; #[doc = "Field `FLS_SLPTIME` writer - Flash wait time after wakeup from the stop mode"] pub type FLS_SLPTIME_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; #[doc = "Field `LPR` reader - Low-power run"] pub type LPR_R = crate::BitReader; #[doc = "Field `LPR` writer - Low-power run"] pub type LPR_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `SRAM_RETV` reader - SRAM retention voltage control"] pub type SRAM_RETV_R = crate::FieldReader; #[doc = "Field `SRAM_RETV` writer - SRAM retention voltage control"] pub type SRAM_RETV_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 3, O>; #[doc = "Field `HSION_CTRL` reader - HSI open time control"] pub type HSION_CTRL_R = crate::BitReader; #[doc = "Field `HSION_CTRL` writer - HSI open time control"] pub type HSION_CTRL_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; impl R { #[doc = "Bits 0:3 - MR Bias current"] #[inline(always)] pub fn bias_cr(&self) -> BIAS_CR_R { BIAS_CR_R::new((self.bits & 0x0f) as u8) } #[doc = "Bit 4 - MR Bias current selection"] #[inline(always)] pub fn bias_cr_sel(&self) -> BIAS_CR_SEL_R { BIAS_CR_SEL_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 8 - Disable backup domain write protection"] #[inline(always)] pub fn dbp(&self) -> DBP_R { DBP_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Voltage scaling range selection"] #[inline(always)] pub fn vos(&self) -> VOS_R { VOS_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bits 10:11 - Time selection wakeup from LP to VR"] #[inline(always)] pub fn mrrdy_time(&self) -> MRRDY_TIME_R { MRRDY_TIME_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Flash wait time after wakeup from the stop mode"] #[inline(always)] pub fn fls_slptime(&self) -> FLS_SLPTIME_R { FLS_SLPTIME_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bit 14 - Low-power run"] #[inline(always)] pub fn lpr(&self) -> LPR_R { LPR_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bits 16:18 - SRAM retention voltage control"] #[inline(always)] pub fn sram_retv(&self) -> SRAM_RETV_R { SRAM_RETV_R::new(((self.bits >> 16) & 7) as u8) } #[doc = "Bit 19 - HSI open time control"] #[inline(always)] pub fn hsion_ctrl(&self) -> HSION_CTRL_R { HSION_CTRL_R::new(((self.bits >> 19) & 1) != 0) } } impl W { #[doc = "Bits 0:3 - MR Bias current"] #[inline(always)] #[must_use] pub fn bias_cr(&mut self) -> BIAS_CR_W<0> { BIAS_CR_W::new(self) } #[doc = "Bit 4 - MR Bias current selection"] #[inline(always)] #[must_use] pub fn bias_cr_sel(&mut self) -> BIAS_CR_SEL_W<4> { BIAS_CR_SEL_W::new(self) } #[doc = "Bit 8 - Disable backup domain write protection"] #[inline(always)] #[must_use] pub fn dbp(&mut self) -> DBP_W<8> { DBP_W::new(self) } #[doc = "Bit 9 - Voltage scaling range selection"] #[inline(always)] #[must_use] pub fn vos(&mut self) -> VOS_W<9> { VOS_W::new(self) } #[doc = "Bits 10:11 - Time selection wakeup from LP to VR"] #[inline(always)] #[must_use] pub fn mrrdy_time(&mut self) -> MRRDY_TIME_W<10> { MRRDY_TIME_W::new(self) } #[doc = "Bits 12:13 - Flash wait time after wakeup from the stop mode"] #[inline(always)] #[must_use] pub fn fls_slptime(&mut self) -> FLS_SLPTIME_W<12> { FLS_SLPTIME_W::new(self) } #[doc = "Bit 14 - Low-power run"] #[inline(always)] #[must_use] pub fn lpr(&mut self) -> LPR_W<14> { LPR_W::new(self) } #[doc = "Bits 16:18 - SRAM retention voltage control"] #[inline(always)] #[must_use] pub fn sram_retv(&mut self) -> SRAM_RETV_W<16> { SRAM_RETV_W::new(self) } #[doc = "Bit 19 - HSI open time control"] #[inline(always)] #[must_use] pub fn hsion_ctrl(&mut self) -> HSION_CTRL_W<19> { HSION_CTRL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Power control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0x0003_0000"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0x0003_0000; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "Power control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PVDE` reader - Power voltage detector enable"] pub type PVDE_R = crate::BitReader; #[doc = "Field `PVDE` writer - Power voltage detector enable"] pub type PVDE_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `SRCSEL` reader - Power voltage detector volatage selection"] pub type SRCSEL_R = crate::BitReader; #[doc = "Field `SRCSEL` writer - Power voltage detector volatage selection"] pub type SRCSEL_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `PVDT` reader - Power voltage detector threshold selection"] pub type PVDT_R = crate::FieldReader; #[doc = "Field `PVDT` writer - Power voltage detector threshold selection"] pub type PVDT_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 3, O>; #[doc = "Field `FLTEN` reader - Digital filter enable"] pub type FLTEN_R = crate::BitReader; #[doc = "Field `FLTEN` writer - Digital filter enable"] pub type FLTEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `FLT_TIME` reader - Digital filter time configuration"] pub type FLT_TIME_R = crate::FieldReader; #[doc = "Field `FLT_TIME` writer - Digital filter time configuration"] pub type FLT_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 3, O>; impl R { #[doc = "Bit 0 - Power voltage detector enable"] #[inline(always)] pub fn pvde(&self) -> PVDE_R { PVDE_R::new((self.bits & 1) != 0) } #[doc = "Bit 2 - Power voltage detector volatage selection"] #[inline(always)] pub fn srcsel(&self) -> SRCSEL_R { SRCSEL_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bits 4:6 - Power voltage detector threshold selection"] #[inline(always)] pub fn pvdt(&self) -> PVDT_R { PVDT_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 8 - Digital filter enable"] #[inline(always)] pub fn flten(&self) -> FLTEN_R { FLTEN_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bits 9:11 - Digital filter time configuration"] #[inline(always)] pub fn flt_time(&self) -> FLT_TIME_R { FLT_TIME_R::new(((self.bits >> 9) & 7) as u8) } } impl W { #[doc = "Bit 0 - Power voltage detector enable"] #[inline(always)] #[must_use] pub fn pvde(&mut self) -> PVDE_W<0> { PVDE_W::new(self) } #[doc = "Bit 2 - Power voltage detector volatage selection"] #[inline(always)] #[must_use] pub fn srcsel(&mut self) -> SRCSEL_W<2> { SRCSEL_W::new(self) } #[doc = "Bits 4:6 - Power voltage detector threshold selection"] #[inline(always)] #[must_use] pub fn pvdt(&mut self) -> PVDT_W<4> { PVDT_W::new(self) } #[doc = "Bit 8 - Digital filter enable"] #[inline(always)] #[must_use] pub fn flten(&mut self) -> FLTEN_W<8> { FLTEN_W::new(self) } #[doc = "Bits 9:11 - Digital filter time configuration"] #[inline(always)] #[must_use] pub fn flt_time(&mut self) -> FLT_TIME_W<9> { FLT_TIME_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Power control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0x0500"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0x0500; } } #[doc = "SR (r) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "Power status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `PVDO` reader - PVD output"] pub type PVDO_R = crate::BitReader; impl R { #[doc = "Bit 11 - PVD output"] #[inline(always)] pub fn pvdo(&self) -> PVDO_R { PVDO_R::new(((self.bits >> 11) & 1) != 0) } } #[doc = "Power status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General-purpose I/Os"] pub struct GPIOA { _marker: PhantomData<*const ()>, } unsafe impl Send for GPIOA {} impl GPIOA { #[doc = r"Pointer to the register block"] pub const PTR: *const gpioa::RegisterBlock = 0x5000_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const gpioa::RegisterBlock { Self::PTR } } impl Deref for GPIOA { type Target = gpioa::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for GPIOA { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GPIOA").finish() } } #[doc = "General-purpose I/Os"] pub mod gpioa { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - GPIO port mode register"] pub moder: MODER, #[doc = "0x04 - GPIO port output type register"] pub otyper: OTYPER, #[doc = "0x08 - GPIO port output speed register"] pub ospeedr: OSPEEDR, #[doc = "0x0c - GPIO port pull-up/pull-down register"] pub pupdr: PUPDR, #[doc = "0x10 - GPIO port input data register"] pub idr: IDR, #[doc = "0x14 - GPIO port output data register"] pub odr: ODR, #[doc = "0x18 - GPIO port bit set/reset register"] pub bsrr: BSRR, #[doc = "0x1c - GPIO port configuration lock register"] pub lckr: LCKR, #[doc = "0x20 - GPIO alternate function low register"] pub afrl: AFRL, #[doc = "0x24 - GPIO alternate function high register"] pub afrh: AFRH, #[doc = "0x28 - port bit reset register"] pub brr: BRR, } #[doc = "MODER (rw) register accessor: an alias for `Reg`"] pub type MODER = crate::Reg; #[doc = "GPIO port mode register"] pub mod moder { #[doc = "Register `MODER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `MODER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `MODE0` reader - Port x configuration bits (y = 0..15)"] pub type MODE0_R = crate::FieldReader; #[doc = "Field `MODE0` writer - Port x configuration bits (y = 0..15)"] pub type MODE0_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE1` reader - Port x configuration bits (y = 0..15)"] pub type MODE1_R = crate::FieldReader; #[doc = "Field `MODE1` writer - Port x configuration bits (y = 0..15)"] pub type MODE1_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE2` reader - Port x configuration bits (y = 0..15)"] pub type MODE2_R = crate::FieldReader; #[doc = "Field `MODE2` writer - Port x configuration bits (y = 0..15)"] pub type MODE2_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE3` reader - Port x configuration bits (y = 0..15)"] pub type MODE3_R = crate::FieldReader; #[doc = "Field `MODE3` writer - Port x configuration bits (y = 0..15)"] pub type MODE3_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE4` reader - Port x configuration bits (y = 0..15)"] pub type MODE4_R = crate::FieldReader; #[doc = "Field `MODE4` writer - Port x configuration bits (y = 0..15)"] pub type MODE4_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE5` reader - Port x configuration bits (y = 0..15)"] pub type MODE5_R = crate::FieldReader; #[doc = "Field `MODE5` writer - Port x configuration bits (y = 0..15)"] pub type MODE5_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE6` reader - Port x configuration bits (y = 0..15)"] pub type MODE6_R = crate::FieldReader; #[doc = "Field `MODE6` writer - Port x configuration bits (y = 0..15)"] pub type MODE6_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE7` reader - Port x configuration bits (y = 0..15)"] pub type MODE7_R = crate::FieldReader; #[doc = "Field `MODE7` writer - Port x configuration bits (y = 0..15)"] pub type MODE7_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE8` reader - Port x configuration bits (y = 0..15)"] pub type MODE8_R = crate::FieldReader; #[doc = "Field `MODE8` writer - Port x configuration bits (y = 0..15)"] pub type MODE8_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE9` reader - Port x configuration bits (y = 0..15)"] pub type MODE9_R = crate::FieldReader; #[doc = "Field `MODE9` writer - Port x configuration bits (y = 0..15)"] pub type MODE9_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE10` reader - Port x configuration bits (y = 0..15)"] pub type MODE10_R = crate::FieldReader; #[doc = "Field `MODE10` writer - Port x configuration bits (y = 0..15)"] pub type MODE10_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE11` reader - Port x configuration bits (y = 0..15)"] pub type MODE11_R = crate::FieldReader; #[doc = "Field `MODE11` writer - Port x configuration bits (y = 0..15)"] pub type MODE11_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE12` reader - Port x configuration bits (y = 0..15)"] pub type MODE12_R = crate::FieldReader; #[doc = "Field `MODE12` writer - Port x configuration bits (y = 0..15)"] pub type MODE12_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE13` reader - Port x configuration bits (y = 0..15)"] pub type MODE13_R = crate::FieldReader; #[doc = "Field `MODE13` writer - Port x configuration bits (y = 0..15)"] pub type MODE13_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE14` reader - Port x configuration bits (y = 0..15)"] pub type MODE14_R = crate::FieldReader; #[doc = "Field `MODE14` writer - Port x configuration bits (y = 0..15)"] pub type MODE14_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE15` reader - Port x configuration bits (y = 0..15)"] pub type MODE15_R = crate::FieldReader; #[doc = "Field `MODE15` writer - Port x configuration bits (y = 0..15)"] pub type MODE15_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode0(&self) -> MODE0_R { MODE0_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode1(&self) -> MODE1_R { MODE1_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode2(&self) -> MODE2_R { MODE2_R::new(((self.bits >> 4) & 3) as u8) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode3(&self) -> MODE3_R { MODE3_R::new(((self.bits >> 6) & 3) as u8) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode4(&self) -> MODE4_R { MODE4_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode5(&self) -> MODE5_R { MODE5_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode6(&self) -> MODE6_R { MODE6_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode7(&self) -> MODE7_R { MODE7_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode8(&self) -> MODE8_R { MODE8_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode9(&self) -> MODE9_R { MODE9_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode10(&self) -> MODE10_R { MODE10_R::new(((self.bits >> 20) & 3) as u8) } #[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode11(&self) -> MODE11_R { MODE11_R::new(((self.bits >> 22) & 3) as u8) } #[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode12(&self) -> MODE12_R { MODE12_R::new(((self.bits >> 24) & 3) as u8) } #[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode13(&self) -> MODE13_R { MODE13_R::new(((self.bits >> 26) & 3) as u8) } #[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode14(&self) -> MODE14_R { MODE14_R::new(((self.bits >> 28) & 3) as u8) } #[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode15(&self) -> MODE15_R { MODE15_R::new(((self.bits >> 30) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode0(&mut self) -> MODE0_W<0> { MODE0_W::new(self) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode1(&mut self) -> MODE1_W<2> { MODE1_W::new(self) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode2(&mut self) -> MODE2_W<4> { MODE2_W::new(self) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode3(&mut self) -> MODE3_W<6> { MODE3_W::new(self) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode4(&mut self) -> MODE4_W<8> { MODE4_W::new(self) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode5(&mut self) -> MODE5_W<10> { MODE5_W::new(self) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode6(&mut self) -> MODE6_W<12> { MODE6_W::new(self) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode7(&mut self) -> MODE7_W<14> { MODE7_W::new(self) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode8(&mut self) -> MODE8_W<16> { MODE8_W::new(self) } #[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode9(&mut self) -> MODE9_W<18> { MODE9_W::new(self) } #[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode10(&mut self) -> MODE10_W<20> { MODE10_W::new(self) } #[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode11(&mut self) -> MODE11_W<22> { MODE11_W::new(self) } #[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode12(&mut self) -> MODE12_W<24> { MODE12_W::new(self) } #[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode13(&mut self) -> MODE13_W<26> { MODE13_W::new(self) } #[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode14(&mut self) -> MODE14_W<28> { MODE14_W::new(self) } #[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode15(&mut self) -> MODE15_W<30> { MODE15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port mode register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [moder](index.html) module"] pub struct MODER_SPEC; impl crate::RegisterSpec for MODER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [moder::R](R) reader structure"] impl crate::Readable for MODER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [moder::W](W) writer structure"] impl crate::Writable for MODER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets MODER to value 0xebff_ffff"] impl crate::Resettable for MODER_SPEC { const RESET_VALUE: Self::Ux = 0xebff_ffff; } } #[doc = "OTYPER (rw) register accessor: an alias for `Reg`"] pub type OTYPER = crate::Reg; #[doc = "GPIO port output type register"] pub mod otyper { #[doc = "Register `OTYPER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OTYPER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OT0` reader - Port x configuration bits (y = 0..15)"] pub type OT0_R = crate::BitReader; #[doc = "Field `OT0` writer - Port x configuration bits (y = 0..15)"] pub type OT0_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT1` reader - Port x configuration bits (y = 0..15)"] pub type OT1_R = crate::BitReader; #[doc = "Field `OT1` writer - Port x configuration bits (y = 0..15)"] pub type OT1_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT2` reader - Port x configuration bits (y = 0..15)"] pub type OT2_R = crate::BitReader; #[doc = "Field `OT2` writer - Port x configuration bits (y = 0..15)"] pub type OT2_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT3` reader - Port x configuration bits (y = 0..15)"] pub type OT3_R = crate::BitReader; #[doc = "Field `OT3` writer - Port x configuration bits (y = 0..15)"] pub type OT3_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT4` reader - Port x configuration bits (y = 0..15)"] pub type OT4_R = crate::BitReader; #[doc = "Field `OT4` writer - Port x configuration bits (y = 0..15)"] pub type OT4_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT5` reader - Port x configuration bits (y = 0..15)"] pub type OT5_R = crate::BitReader; #[doc = "Field `OT5` writer - Port x configuration bits (y = 0..15)"] pub type OT5_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT6` reader - Port x configuration bits (y = 0..15)"] pub type OT6_R = crate::BitReader; #[doc = "Field `OT6` writer - Port x configuration bits (y = 0..15)"] pub type OT6_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT7` reader - Port x configuration bits (y = 0..15)"] pub type OT7_R = crate::BitReader; #[doc = "Field `OT7` writer - Port x configuration bits (y = 0..15)"] pub type OT7_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT8` reader - Port x configuration bits (y = 0..15)"] pub type OT8_R = crate::BitReader; #[doc = "Field `OT8` writer - Port x configuration bits (y = 0..15)"] pub type OT8_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT9` reader - Port x configuration bits (y = 0..15)"] pub type OT9_R = crate::BitReader; #[doc = "Field `OT9` writer - Port x configuration bits (y = 0..15)"] pub type OT9_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT10` reader - Port x configuration bits (y = 0..15)"] pub type OT10_R = crate::BitReader; #[doc = "Field `OT10` writer - Port x configuration bits (y = 0..15)"] pub type OT10_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT11` reader - Port x configuration bits (y = 0..15)"] pub type OT11_R = crate::BitReader; #[doc = "Field `OT11` writer - Port x configuration bits (y = 0..15)"] pub type OT11_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT12` reader - Port x configuration bits (y = 0..15)"] pub type OT12_R = crate::BitReader; #[doc = "Field `OT12` writer - Port x configuration bits (y = 0..15)"] pub type OT12_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT13` reader - Port x configuration bits (y = 0..15)"] pub type OT13_R = crate::BitReader; #[doc = "Field `OT13` writer - Port x configuration bits (y = 0..15)"] pub type OT13_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT14` reader - Port x configuration bits (y = 0..15)"] pub type OT14_R = crate::BitReader; #[doc = "Field `OT14` writer - Port x configuration bits (y = 0..15)"] pub type OT14_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT15` reader - Port x configuration bits (y = 0..15)"] pub type OT15_R = crate::BitReader; #[doc = "Field `OT15` writer - Port x configuration bits (y = 0..15)"] pub type OT15_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; impl R { #[doc = "Bit 0 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot0(&self) -> OT0_R { OT0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot1(&self) -> OT1_R { OT1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot2(&self) -> OT2_R { OT2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot3(&self) -> OT3_R { OT3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot4(&self) -> OT4_R { OT4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot5(&self) -> OT5_R { OT5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot6(&self) -> OT6_R { OT6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot7(&self) -> OT7_R { OT7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot8(&self) -> OT8_R { OT8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot9(&self) -> OT9_R { OT9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot10(&self) -> OT10_R { OT10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot11(&self) -> OT11_R { OT11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot12(&self) -> OT12_R { OT12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot13(&self) -> OT13_R { OT13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot14(&self) -> OT14_R { OT14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot15(&self) -> OT15_R { OT15_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bit 0 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot0(&mut self) -> OT0_W<0> { OT0_W::new(self) } #[doc = "Bit 1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot1(&mut self) -> OT1_W<1> { OT1_W::new(self) } #[doc = "Bit 2 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot2(&mut self) -> OT2_W<2> { OT2_W::new(self) } #[doc = "Bit 3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot3(&mut self) -> OT3_W<3> { OT3_W::new(self) } #[doc = "Bit 4 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot4(&mut self) -> OT4_W<4> { OT4_W::new(self) } #[doc = "Bit 5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot5(&mut self) -> OT5_W<5> { OT5_W::new(self) } #[doc = "Bit 6 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot6(&mut self) -> OT6_W<6> { OT6_W::new(self) } #[doc = "Bit 7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot7(&mut self) -> OT7_W<7> { OT7_W::new(self) } #[doc = "Bit 8 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot8(&mut self) -> OT8_W<8> { OT8_W::new(self) } #[doc = "Bit 9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot9(&mut self) -> OT9_W<9> { OT9_W::new(self) } #[doc = "Bit 10 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot10(&mut self) -> OT10_W<10> { OT10_W::new(self) } #[doc = "Bit 11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot11(&mut self) -> OT11_W<11> { OT11_W::new(self) } #[doc = "Bit 12 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot12(&mut self) -> OT12_W<12> { OT12_W::new(self) } #[doc = "Bit 13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot13(&mut self) -> OT13_W<13> { OT13_W::new(self) } #[doc = "Bit 14 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot14(&mut self) -> OT14_W<14> { OT14_W::new(self) } #[doc = "Bit 15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot15(&mut self) -> OT15_W<15> { OT15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port output type register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [otyper](index.html) module"] pub struct OTYPER_SPEC; impl crate::RegisterSpec for OTYPER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [otyper::R](R) reader structure"] impl crate::Readable for OTYPER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [otyper::W](W) writer structure"] impl crate::Writable for OTYPER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OTYPER to value 0"] impl crate::Resettable for OTYPER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "OSPEEDR (rw) register accessor: an alias for `Reg`"] pub type OSPEEDR = crate::Reg; #[doc = "GPIO port output speed register"] pub mod ospeedr { #[doc = "Register `OSPEEDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OSPEEDR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OSPEED0` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED0_R = crate::FieldReader; #[doc = "Field `OSPEED0` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED0_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED1` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED1_R = crate::FieldReader; #[doc = "Field `OSPEED1` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED1_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED2` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED2_R = crate::FieldReader; #[doc = "Field `OSPEED2` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED2_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED3` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED3_R = crate::FieldReader; #[doc = "Field `OSPEED3` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED3_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED4` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED4_R = crate::FieldReader; #[doc = "Field `OSPEED4` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED4_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED5` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED5_R = crate::FieldReader; #[doc = "Field `OSPEED5` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED5_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED6` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED6_R = crate::FieldReader; #[doc = "Field `OSPEED6` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED6_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED7` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED7_R = crate::FieldReader; #[doc = "Field `OSPEED7` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED7_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED8` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED8_R = crate::FieldReader; #[doc = "Field `OSPEED8` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED8_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED9` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED9_R = crate::FieldReader; #[doc = "Field `OSPEED9` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED9_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED10` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED10_R = crate::FieldReader; #[doc = "Field `OSPEED10` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED10_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED11` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED11_R = crate::FieldReader; #[doc = "Field `OSPEED11` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED11_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED12` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED12_R = crate::FieldReader; #[doc = "Field `OSPEED12` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED12_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED13` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED13_R = crate::FieldReader; #[doc = "Field `OSPEED13` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED13_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED14` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED14_R = crate::FieldReader; #[doc = "Field `OSPEED14` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED14_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED15` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED15_R = crate::FieldReader; #[doc = "Field `OSPEED15` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED15_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed0(&self) -> OSPEED0_R { OSPEED0_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed1(&self) -> OSPEED1_R { OSPEED1_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed2(&self) -> OSPEED2_R { OSPEED2_R::new(((self.bits >> 4) & 3) as u8) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed3(&self) -> OSPEED3_R { OSPEED3_R::new(((self.bits >> 6) & 3) as u8) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed4(&self) -> OSPEED4_R { OSPEED4_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed5(&self) -> OSPEED5_R { OSPEED5_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed6(&self) -> OSPEED6_R { OSPEED6_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed7(&self) -> OSPEED7_R { OSPEED7_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed8(&self) -> OSPEED8_R { OSPEED8_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed9(&self) -> OSPEED9_R { OSPEED9_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed10(&self) -> OSPEED10_R { OSPEED10_R::new(((self.bits >> 20) & 3) as u8) } #[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed11(&self) -> OSPEED11_R { OSPEED11_R::new(((self.bits >> 22) & 3) as u8) } #[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed12(&self) -> OSPEED12_R { OSPEED12_R::new(((self.bits >> 24) & 3) as u8) } #[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed13(&self) -> OSPEED13_R { OSPEED13_R::new(((self.bits >> 26) & 3) as u8) } #[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed14(&self) -> OSPEED14_R { OSPEED14_R::new(((self.bits >> 28) & 3) as u8) } #[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed15(&self) -> OSPEED15_R { OSPEED15_R::new(((self.bits >> 30) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed0(&mut self) -> OSPEED0_W<0> { OSPEED0_W::new(self) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed1(&mut self) -> OSPEED1_W<2> { OSPEED1_W::new(self) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed2(&mut self) -> OSPEED2_W<4> { OSPEED2_W::new(self) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed3(&mut self) -> OSPEED3_W<6> { OSPEED3_W::new(self) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed4(&mut self) -> OSPEED4_W<8> { OSPEED4_W::new(self) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed5(&mut self) -> OSPEED5_W<10> { OSPEED5_W::new(self) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed6(&mut self) -> OSPEED6_W<12> { OSPEED6_W::new(self) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed7(&mut self) -> OSPEED7_W<14> { OSPEED7_W::new(self) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed8(&mut self) -> OSPEED8_W<16> { OSPEED8_W::new(self) } #[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed9(&mut self) -> OSPEED9_W<18> { OSPEED9_W::new(self) } #[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed10(&mut self) -> OSPEED10_W<20> { OSPEED10_W::new(self) } #[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed11(&mut self) -> OSPEED11_W<22> { OSPEED11_W::new(self) } #[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed12(&mut self) -> OSPEED12_W<24> { OSPEED12_W::new(self) } #[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed13(&mut self) -> OSPEED13_W<26> { OSPEED13_W::new(self) } #[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed14(&mut self) -> OSPEED14_W<28> { OSPEED14_W::new(self) } #[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed15(&mut self) -> OSPEED15_W<30> { OSPEED15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port output speed register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ospeedr](index.html) module"] pub struct OSPEEDR_SPEC; impl crate::RegisterSpec for OSPEEDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ospeedr::R](R) reader structure"] impl crate::Readable for OSPEEDR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ospeedr::W](W) writer structure"] impl crate::Writable for OSPEEDR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OSPEEDR to value 0x0c00_0000"] impl crate::Resettable for OSPEEDR_SPEC { const RESET_VALUE: Self::Ux = 0x0c00_0000; } } #[doc = "PUPDR (rw) register accessor: an alias for `Reg`"] pub type PUPDR = crate::Reg; #[doc = "GPIO port pull-up/pull-down register"] pub mod pupdr { #[doc = "Register `PUPDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PUPDR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PUPD0` reader - Port x configuration bits (y = 0..15)"] pub type PUPD0_R = crate::FieldReader; #[doc = "Field `PUPD0` writer - Port x configuration bits (y = 0..15)"] pub type PUPD0_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD1` reader - Port x configuration bits (y = 0..15)"] pub type PUPD1_R = crate::FieldReader; #[doc = "Field `PUPD1` writer - Port x configuration bits (y = 0..15)"] pub type PUPD1_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD2` reader - Port x configuration bits (y = 0..15)"] pub type PUPD2_R = crate::FieldReader; #[doc = "Field `PUPD2` writer - Port x configuration bits (y = 0..15)"] pub type PUPD2_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD3` reader - Port x configuration bits (y = 0..15)"] pub type PUPD3_R = crate::FieldReader; #[doc = "Field `PUPD3` writer - Port x configuration bits (y = 0..15)"] pub type PUPD3_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD4` reader - Port x configuration bits (y = 0..15)"] pub type PUPD4_R = crate::FieldReader; #[doc = "Field `PUPD4` writer - Port x configuration bits (y = 0..15)"] pub type PUPD4_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD5` reader - Port x configuration bits (y = 0..15)"] pub type PUPD5_R = crate::FieldReader; #[doc = "Field `PUPD5` writer - Port x configuration bits (y = 0..15)"] pub type PUPD5_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD6` reader - Port x configuration bits (y = 0..15)"] pub type PUPD6_R = crate::FieldReader; #[doc = "Field `PUPD6` writer - Port x configuration bits (y = 0..15)"] pub type PUPD6_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD7` reader - Port x configuration bits (y = 0..15)"] pub type PUPD7_R = crate::FieldReader; #[doc = "Field `PUPD7` writer - Port x configuration bits (y = 0..15)"] pub type PUPD7_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD8` reader - Port x configuration bits (y = 0..15)"] pub type PUPD8_R = crate::FieldReader; #[doc = "Field `PUPD8` writer - Port x configuration bits (y = 0..15)"] pub type PUPD8_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD9` reader - Port x configuration bits (y = 0..15)"] pub type PUPD9_R = crate::FieldReader; #[doc = "Field `PUPD9` writer - Port x configuration bits (y = 0..15)"] pub type PUPD9_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD10` reader - Port x configuration bits (y = 0..15)"] pub type PUPD10_R = crate::FieldReader; #[doc = "Field `PUPD10` writer - Port x configuration bits (y = 0..15)"] pub type PUPD10_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD11` reader - Port x configuration bits (y = 0..15)"] pub type PUPD11_R = crate::FieldReader; #[doc = "Field `PUPD11` writer - Port x configuration bits (y = 0..15)"] pub type PUPD11_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD12` reader - Port x configuration bits (y = 0..15)"] pub type PUPD12_R = crate::FieldReader; #[doc = "Field `PUPD12` writer - Port x configuration bits (y = 0..15)"] pub type PUPD12_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD13` reader - Port x configuration bits (y = 0..15)"] pub type PUPD13_R = crate::FieldReader; #[doc = "Field `PUPD13` writer - Port x configuration bits (y = 0..15)"] pub type PUPD13_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD14` reader - Port x configuration bits (y = 0..15)"] pub type PUPD14_R = crate::FieldReader; #[doc = "Field `PUPD14` writer - Port x configuration bits (y = 0..15)"] pub type PUPD14_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD15` reader - Port x configuration bits (y = 0..15)"] pub type PUPD15_R = crate::FieldReader; #[doc = "Field `PUPD15` writer - Port x configuration bits (y = 0..15)"] pub type PUPD15_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd0(&self) -> PUPD0_R { PUPD0_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd1(&self) -> PUPD1_R { PUPD1_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd2(&self) -> PUPD2_R { PUPD2_R::new(((self.bits >> 4) & 3) as u8) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd3(&self) -> PUPD3_R { PUPD3_R::new(((self.bits >> 6) & 3) as u8) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd4(&self) -> PUPD4_R { PUPD4_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd5(&self) -> PUPD5_R { PUPD5_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd6(&self) -> PUPD6_R { PUPD6_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd7(&self) -> PUPD7_R { PUPD7_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd8(&self) -> PUPD8_R { PUPD8_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd9(&self) -> PUPD9_R { PUPD9_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd10(&self) -> PUPD10_R { PUPD10_R::new(((self.bits >> 20) & 3) as u8) } #[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd11(&self) -> PUPD11_R { PUPD11_R::new(((self.bits >> 22) & 3) as u8) } #[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd12(&self) -> PUPD12_R { PUPD12_R::new(((self.bits >> 24) & 3) as u8) } #[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd13(&self) -> PUPD13_R { PUPD13_R::new(((self.bits >> 26) & 3) as u8) } #[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd14(&self) -> PUPD14_R { PUPD14_R::new(((self.bits >> 28) & 3) as u8) } #[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd15(&self) -> PUPD15_R { PUPD15_R::new(((self.bits >> 30) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd0(&mut self) -> PUPD0_W<0> { PUPD0_W::new(self) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd1(&mut self) -> PUPD1_W<2> { PUPD1_W::new(self) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd2(&mut self) -> PUPD2_W<4> { PUPD2_W::new(self) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd3(&mut self) -> PUPD3_W<6> { PUPD3_W::new(self) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd4(&mut self) -> PUPD4_W<8> { PUPD4_W::new(self) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd5(&mut self) -> PUPD5_W<10> { PUPD5_W::new(self) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd6(&mut self) -> PUPD6_W<12> { PUPD6_W::new(self) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd7(&mut self) -> PUPD7_W<14> { PUPD7_W::new(self) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd8(&mut self) -> PUPD8_W<16> { PUPD8_W::new(self) } #[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd9(&mut self) -> PUPD9_W<18> { PUPD9_W::new(self) } #[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd10(&mut self) -> PUPD10_W<20> { PUPD10_W::new(self) } #[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd11(&mut self) -> PUPD11_W<22> { PUPD11_W::new(self) } #[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd12(&mut self) -> PUPD12_W<24> { PUPD12_W::new(self) } #[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd13(&mut self) -> PUPD13_W<26> { PUPD13_W::new(self) } #[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd14(&mut self) -> PUPD14_W<28> { PUPD14_W::new(self) } #[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd15(&mut self) -> PUPD15_W<30> { PUPD15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port pull-up/pull-down register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pupdr](index.html) module"] pub struct PUPDR_SPEC; impl crate::RegisterSpec for PUPDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pupdr::R](R) reader structure"] impl crate::Readable for PUPDR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pupdr::W](W) writer structure"] impl crate::Writable for PUPDR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PUPDR to value 0x2400_0000"] impl crate::Resettable for PUPDR_SPEC { const RESET_VALUE: Self::Ux = 0x2400_0000; } } #[doc = "IDR (r) register accessor: an alias for `Reg`"] pub type IDR = crate::Reg; #[doc = "GPIO port input data register"] pub mod idr { #[doc = "Register `IDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `ID0` reader - Port input data (y = 0..15)"] pub type ID0_R = crate::BitReader; #[doc = "Field `ID1` reader - Port input data (y = 0..15)"] pub type ID1_R = crate::BitReader; #[doc = "Field `ID2` reader - Port input data (y = 0..15)"] pub type ID2_R = crate::BitReader; #[doc = "Field `ID3` reader - Port input data (y = 0..15)"] pub type ID3_R = crate::BitReader; #[doc = "Field `ID4` reader - Port input data (y = 0..15)"] pub type ID4_R = crate::BitReader; #[doc = "Field `ID5` reader - Port input data (y = 0..15)"] pub type ID5_R = crate::BitReader; #[doc = "Field `ID6` reader - Port input data (y = 0..15)"] pub type ID6_R = crate::BitReader; #[doc = "Field `ID7` reader - Port input data (y = 0..15)"] pub type ID7_R = crate::BitReader; #[doc = "Field `ID8` reader - Port input data (y = 0..15)"] pub type ID8_R = crate::BitReader; #[doc = "Field `ID9` reader - Port input data (y = 0..15)"] pub type ID9_R = crate::BitReader; #[doc = "Field `ID10` reader - Port input data (y = 0..15)"] pub type ID10_R = crate::BitReader; #[doc = "Field `ID11` reader - Port input data (y = 0..15)"] pub type ID11_R = crate::BitReader; #[doc = "Field `ID12` reader - Port input data (y = 0..15)"] pub type ID12_R = crate::BitReader; #[doc = "Field `ID13` reader - Port input data (y = 0..15)"] pub type ID13_R = crate::BitReader; #[doc = "Field `ID14` reader - Port input data (y = 0..15)"] pub type ID14_R = crate::BitReader; #[doc = "Field `ID15` reader - Port input data (y = 0..15)"] pub type ID15_R = crate::BitReader; impl R { #[doc = "Bit 0 - Port input data (y = 0..15)"] #[inline(always)] pub fn id0(&self) -> ID0_R { ID0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port input data (y = 0..15)"] #[inline(always)] pub fn id1(&self) -> ID1_R { ID1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port input data (y = 0..15)"] #[inline(always)] pub fn id2(&self) -> ID2_R { ID2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port input data (y = 0..15)"] #[inline(always)] pub fn id3(&self) -> ID3_R { ID3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port input data (y = 0..15)"] #[inline(always)] pub fn id4(&self) -> ID4_R { ID4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port input data (y = 0..15)"] #[inline(always)] pub fn id5(&self) -> ID5_R { ID5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port input data (y = 0..15)"] #[inline(always)] pub fn id6(&self) -> ID6_R { ID6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port input data (y = 0..15)"] #[inline(always)] pub fn id7(&self) -> ID7_R { ID7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port input data (y = 0..15)"] #[inline(always)] pub fn id8(&self) -> ID8_R { ID8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Port input data (y = 0..15)"] #[inline(always)] pub fn id9(&self) -> ID9_R { ID9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Port input data (y = 0..15)"] #[inline(always)] pub fn id10(&self) -> ID10_R { ID10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Port input data (y = 0..15)"] #[inline(always)] pub fn id11(&self) -> ID11_R { ID11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Port input data (y = 0..15)"] #[inline(always)] pub fn id12(&self) -> ID12_R { ID12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Port input data (y = 0..15)"] #[inline(always)] pub fn id13(&self) -> ID13_R { ID13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Port input data (y = 0..15)"] #[inline(always)] pub fn id14(&self) -> ID14_R { ID14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Port input data (y = 0..15)"] #[inline(always)] pub fn id15(&self) -> ID15_R { ID15_R::new(((self.bits >> 15) & 1) != 0) } } #[doc = "GPIO port input data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [idr::R](R) reader structure"] impl crate::Readable for IDR_SPEC { type Reader = R; } #[doc = "`reset()` method sets IDR to value 0"] impl crate::Resettable for IDR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ODR (rw) register accessor: an alias for `Reg`"] pub type ODR = crate::Reg; #[doc = "GPIO port output data register"] pub mod odr { #[doc = "Register `ODR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ODR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OD0` reader - Port output data (y = 0..15)"] pub type OD0_R = crate::BitReader; #[doc = "Field `OD0` writer - Port output data (y = 0..15)"] pub type OD0_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD1` reader - Port output data (y = 0..15)"] pub type OD1_R = crate::BitReader; #[doc = "Field `OD1` writer - Port output data (y = 0..15)"] pub type OD1_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD2` reader - Port output data (y = 0..15)"] pub type OD2_R = crate::BitReader; #[doc = "Field `OD2` writer - Port output data (y = 0..15)"] pub type OD2_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD3` reader - Port output data (y = 0..15)"] pub type OD3_R = crate::BitReader; #[doc = "Field `OD3` writer - Port output data (y = 0..15)"] pub type OD3_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD4` reader - Port output data (y = 0..15)"] pub type OD4_R = crate::BitReader; #[doc = "Field `OD4` writer - Port output data (y = 0..15)"] pub type OD4_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD5` reader - Port output data (y = 0..15)"] pub type OD5_R = crate::BitReader; #[doc = "Field `OD5` writer - Port output data (y = 0..15)"] pub type OD5_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD6` reader - Port output data (y = 0..15)"] pub type OD6_R = crate::BitReader; #[doc = "Field `OD6` writer - Port output data (y = 0..15)"] pub type OD6_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD7` reader - Port output data (y = 0..15)"] pub type OD7_R = crate::BitReader; #[doc = "Field `OD7` writer - Port output data (y = 0..15)"] pub type OD7_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD8` reader - Port output data (y = 0..15)"] pub type OD8_R = crate::BitReader; #[doc = "Field `OD8` writer - Port output data (y = 0..15)"] pub type OD8_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD9` reader - Port output data (y = 0..15)"] pub type OD9_R = crate::BitReader; #[doc = "Field `OD9` writer - Port output data (y = 0..15)"] pub type OD9_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD10` reader - Port output data (y = 0..15)"] pub type OD10_R = crate::BitReader; #[doc = "Field `OD10` writer - Port output data (y = 0..15)"] pub type OD10_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD11` reader - Port output data (y = 0..15)"] pub type OD11_R = crate::BitReader; #[doc = "Field `OD11` writer - Port output data (y = 0..15)"] pub type OD11_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD12` reader - Port output data (y = 0..15)"] pub type OD12_R = crate::BitReader; #[doc = "Field `OD12` writer - Port output data (y = 0..15)"] pub type OD12_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD13` reader - Port output data (y = 0..15)"] pub type OD13_R = crate::BitReader; #[doc = "Field `OD13` writer - Port output data (y = 0..15)"] pub type OD13_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD14` reader - Port output data (y = 0..15)"] pub type OD14_R = crate::BitReader; #[doc = "Field `OD14` writer - Port output data (y = 0..15)"] pub type OD14_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD15` reader - Port output data (y = 0..15)"] pub type OD15_R = crate::BitReader; #[doc = "Field `OD15` writer - Port output data (y = 0..15)"] pub type OD15_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; impl R { #[doc = "Bit 0 - Port output data (y = 0..15)"] #[inline(always)] pub fn od0(&self) -> OD0_R { OD0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port output data (y = 0..15)"] #[inline(always)] pub fn od1(&self) -> OD1_R { OD1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port output data (y = 0..15)"] #[inline(always)] pub fn od2(&self) -> OD2_R { OD2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port output data (y = 0..15)"] #[inline(always)] pub fn od3(&self) -> OD3_R { OD3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port output data (y = 0..15)"] #[inline(always)] pub fn od4(&self) -> OD4_R { OD4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port output data (y = 0..15)"] #[inline(always)] pub fn od5(&self) -> OD5_R { OD5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port output data (y = 0..15)"] #[inline(always)] pub fn od6(&self) -> OD6_R { OD6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port output data (y = 0..15)"] #[inline(always)] pub fn od7(&self) -> OD7_R { OD7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port output data (y = 0..15)"] #[inline(always)] pub fn od8(&self) -> OD8_R { OD8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Port output data (y = 0..15)"] #[inline(always)] pub fn od9(&self) -> OD9_R { OD9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Port output data (y = 0..15)"] #[inline(always)] pub fn od10(&self) -> OD10_R { OD10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Port output data (y = 0..15)"] #[inline(always)] pub fn od11(&self) -> OD11_R { OD11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Port output data (y = 0..15)"] #[inline(always)] pub fn od12(&self) -> OD12_R { OD12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Port output data (y = 0..15)"] #[inline(always)] pub fn od13(&self) -> OD13_R { OD13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Port output data (y = 0..15)"] #[inline(always)] pub fn od14(&self) -> OD14_R { OD14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Port output data (y = 0..15)"] #[inline(always)] pub fn od15(&self) -> OD15_R { OD15_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bit 0 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od0(&mut self) -> OD0_W<0> { OD0_W::new(self) } #[doc = "Bit 1 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od1(&mut self) -> OD1_W<1> { OD1_W::new(self) } #[doc = "Bit 2 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od2(&mut self) -> OD2_W<2> { OD2_W::new(self) } #[doc = "Bit 3 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od3(&mut self) -> OD3_W<3> { OD3_W::new(self) } #[doc = "Bit 4 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od4(&mut self) -> OD4_W<4> { OD4_W::new(self) } #[doc = "Bit 5 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od5(&mut self) -> OD5_W<5> { OD5_W::new(self) } #[doc = "Bit 6 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od6(&mut self) -> OD6_W<6> { OD6_W::new(self) } #[doc = "Bit 7 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od7(&mut self) -> OD7_W<7> { OD7_W::new(self) } #[doc = "Bit 8 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od8(&mut self) -> OD8_W<8> { OD8_W::new(self) } #[doc = "Bit 9 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od9(&mut self) -> OD9_W<9> { OD9_W::new(self) } #[doc = "Bit 10 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od10(&mut self) -> OD10_W<10> { OD10_W::new(self) } #[doc = "Bit 11 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od11(&mut self) -> OD11_W<11> { OD11_W::new(self) } #[doc = "Bit 12 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od12(&mut self) -> OD12_W<12> { OD12_W::new(self) } #[doc = "Bit 13 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od13(&mut self) -> OD13_W<13> { OD13_W::new(self) } #[doc = "Bit 14 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od14(&mut self) -> OD14_W<14> { OD14_W::new(self) } #[doc = "Bit 15 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od15(&mut self) -> OD15_W<15> { OD15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port output data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odr](index.html) module"] pub struct ODR_SPEC; impl crate::RegisterSpec for ODR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [odr::R](R) reader structure"] impl crate::Readable for ODR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [odr::W](W) writer structure"] impl crate::Writable for ODR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ODR to value 0"] impl crate::Resettable for ODR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BSRR (w) register accessor: an alias for `Reg`"] pub type BSRR = crate::Reg; #[doc = "GPIO port bit set/reset register"] pub mod bsrr { #[doc = "Register `BSRR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `BS0` writer - Port x set bit y (y= 0..15)"] pub type BS0_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS1` writer - Port x set bit y (y= 0..15)"] pub type BS1_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS2` writer - Port x set bit y (y= 0..15)"] pub type BS2_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS3` writer - Port x set bit y (y= 0..15)"] pub type BS3_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS4` writer - Port x set bit y (y= 0..15)"] pub type BS4_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS5` writer - Port x set bit y (y= 0..15)"] pub type BS5_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS6` writer - Port x set bit y (y= 0..15)"] pub type BS6_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS7` writer - Port x set bit y (y= 0..15)"] pub type BS7_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS8` writer - Port x set bit y (y= 0..15)"] pub type BS8_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS9` writer - Port x set bit y (y= 0..15)"] pub type BS9_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS10` writer - Port x set bit y (y= 0..15)"] pub type BS10_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS11` writer - Port x set bit y (y= 0..15)"] pub type BS11_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS12` writer - Port x set bit y (y= 0..15)"] pub type BS12_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS13` writer - Port x set bit y (y= 0..15)"] pub type BS13_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS14` writer - Port x set bit y (y= 0..15)"] pub type BS14_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS15` writer - Port x set bit y (y= 0..15)"] pub type BS15_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR0` writer - Port x set bit y (y= 0..15)"] pub type BR0_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR1` writer - Port x reset bit y (y = 0..15)"] pub type BR1_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR2` writer - Port x reset bit y (y = 0..15)"] pub type BR2_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR3` writer - Port x reset bit y (y = 0..15)"] pub type BR3_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR4` writer - Port x reset bit y (y = 0..15)"] pub type BR4_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR5` writer - Port x reset bit y (y = 0..15)"] pub type BR5_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR6` writer - Port x reset bit y (y = 0..15)"] pub type BR6_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR7` writer - Port x reset bit y (y = 0..15)"] pub type BR7_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR8` writer - Port x reset bit y (y = 0..15)"] pub type BR8_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR9` writer - Port x reset bit y (y = 0..15)"] pub type BR9_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR10` writer - Port x reset bit y (y = 0..15)"] pub type BR10_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR11` writer - Port x reset bit y (y = 0..15)"] pub type BR11_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR12` writer - Port x reset bit y (y = 0..15)"] pub type BR12_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR13` writer - Port x reset bit y (y = 0..15)"] pub type BR13_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR14` writer - Port x reset bit y (y = 0..15)"] pub type BR14_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR15` writer - Port x reset bit y (y = 0..15)"] pub type BR15_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; impl W { #[doc = "Bit 0 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs0(&mut self) -> BS0_W<0> { BS0_W::new(self) } #[doc = "Bit 1 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs1(&mut self) -> BS1_W<1> { BS1_W::new(self) } #[doc = "Bit 2 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs2(&mut self) -> BS2_W<2> { BS2_W::new(self) } #[doc = "Bit 3 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs3(&mut self) -> BS3_W<3> { BS3_W::new(self) } #[doc = "Bit 4 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs4(&mut self) -> BS4_W<4> { BS4_W::new(self) } #[doc = "Bit 5 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs5(&mut self) -> BS5_W<5> { BS5_W::new(self) } #[doc = "Bit 6 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs6(&mut self) -> BS6_W<6> { BS6_W::new(self) } #[doc = "Bit 7 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs7(&mut self) -> BS7_W<7> { BS7_W::new(self) } #[doc = "Bit 8 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs8(&mut self) -> BS8_W<8> { BS8_W::new(self) } #[doc = "Bit 9 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs9(&mut self) -> BS9_W<9> { BS9_W::new(self) } #[doc = "Bit 10 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs10(&mut self) -> BS10_W<10> { BS10_W::new(self) } #[doc = "Bit 11 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs11(&mut self) -> BS11_W<11> { BS11_W::new(self) } #[doc = "Bit 12 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs12(&mut self) -> BS12_W<12> { BS12_W::new(self) } #[doc = "Bit 13 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs13(&mut self) -> BS13_W<13> { BS13_W::new(self) } #[doc = "Bit 14 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs14(&mut self) -> BS14_W<14> { BS14_W::new(self) } #[doc = "Bit 15 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs15(&mut self) -> BS15_W<15> { BS15_W::new(self) } #[doc = "Bit 16 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn br0(&mut self) -> BR0_W<16> { BR0_W::new(self) } #[doc = "Bit 17 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br1(&mut self) -> BR1_W<17> { BR1_W::new(self) } #[doc = "Bit 18 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br2(&mut self) -> BR2_W<18> { BR2_W::new(self) } #[doc = "Bit 19 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br3(&mut self) -> BR3_W<19> { BR3_W::new(self) } #[doc = "Bit 20 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br4(&mut self) -> BR4_W<20> { BR4_W::new(self) } #[doc = "Bit 21 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br5(&mut self) -> BR5_W<21> { BR5_W::new(self) } #[doc = "Bit 22 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br6(&mut self) -> BR6_W<22> { BR6_W::new(self) } #[doc = "Bit 23 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br7(&mut self) -> BR7_W<23> { BR7_W::new(self) } #[doc = "Bit 24 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br8(&mut self) -> BR8_W<24> { BR8_W::new(self) } #[doc = "Bit 25 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br9(&mut self) -> BR9_W<25> { BR9_W::new(self) } #[doc = "Bit 26 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br10(&mut self) -> BR10_W<26> { BR10_W::new(self) } #[doc = "Bit 27 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br11(&mut self) -> BR11_W<27> { BR11_W::new(self) } #[doc = "Bit 28 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br12(&mut self) -> BR12_W<28> { BR12_W::new(self) } #[doc = "Bit 29 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br13(&mut self) -> BR13_W<29> { BR13_W::new(self) } #[doc = "Bit 30 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br14(&mut self) -> BR14_W<30> { BR14_W::new(self) } #[doc = "Bit 31 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br15(&mut self) -> BR15_W<31> { BR15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port bit set/reset register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bsrr](index.html) module"] pub struct BSRR_SPEC; impl crate::RegisterSpec for BSRR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [bsrr::W](W) writer structure"] impl crate::Writable for BSRR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BSRR to value 0"] impl crate::Resettable for BSRR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "LCKR (rw) register accessor: an alias for `Reg`"] pub type LCKR = crate::Reg; #[doc = "GPIO port configuration lock register"] pub mod lckr { #[doc = "Register `LCKR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `LCKR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LCK0` reader - Port x lock bit y (y= 0..15)"] pub type LCK0_R = crate::BitReader; #[doc = "Field `LCK0` writer - Port x lock bit y (y= 0..15)"] pub type LCK0_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK1` reader - Port x lock bit y (y= 0..15)"] pub type LCK1_R = crate::BitReader; #[doc = "Field `LCK1` writer - Port x lock bit y (y= 0..15)"] pub type LCK1_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK2` reader - Port x lock bit y (y= 0..15)"] pub type LCK2_R = crate::BitReader; #[doc = "Field `LCK2` writer - Port x lock bit y (y= 0..15)"] pub type LCK2_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK3` reader - Port x lock bit y (y= 0..15)"] pub type LCK3_R = crate::BitReader; #[doc = "Field `LCK3` writer - Port x lock bit y (y= 0..15)"] pub type LCK3_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK4` reader - Port x lock bit y (y= 0..15)"] pub type LCK4_R = crate::BitReader; #[doc = "Field `LCK4` writer - Port x lock bit y (y= 0..15)"] pub type LCK4_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK5` reader - Port x lock bit y (y= 0..15)"] pub type LCK5_R = crate::BitReader; #[doc = "Field `LCK5` writer - Port x lock bit y (y= 0..15)"] pub type LCK5_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK6` reader - Port x lock bit y (y= 0..15)"] pub type LCK6_R = crate::BitReader; #[doc = "Field `LCK6` writer - Port x lock bit y (y= 0..15)"] pub type LCK6_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK7` reader - Port x lock bit y (y= 0..15)"] pub type LCK7_R = crate::BitReader; #[doc = "Field `LCK7` writer - Port x lock bit y (y= 0..15)"] pub type LCK7_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK8` reader - Port x lock bit y (y= 0..15)"] pub type LCK8_R = crate::BitReader; #[doc = "Field `LCK8` writer - Port x lock bit y (y= 0..15)"] pub type LCK8_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK9` reader - Port x lock bit y (y= 0..15)"] pub type LCK9_R = crate::BitReader; #[doc = "Field `LCK9` writer - Port x lock bit y (y= 0..15)"] pub type LCK9_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK10` reader - Port x lock bit y (y= 0..15)"] pub type LCK10_R = crate::BitReader; #[doc = "Field `LCK10` writer - Port x lock bit y (y= 0..15)"] pub type LCK10_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK11` reader - Port x lock bit y (y= 0..15)"] pub type LCK11_R = crate::BitReader; #[doc = "Field `LCK11` writer - Port x lock bit y (y= 0..15)"] pub type LCK11_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK12` reader - Port x lock bit y (y= 0..15)"] pub type LCK12_R = crate::BitReader; #[doc = "Field `LCK12` writer - Port x lock bit y (y= 0..15)"] pub type LCK12_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK13` reader - Port x lock bit y (y= 0..15)"] pub type LCK13_R = crate::BitReader; #[doc = "Field `LCK13` writer - Port x lock bit y (y= 0..15)"] pub type LCK13_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK14` reader - Port x lock bit y (y= 0..15)"] pub type LCK14_R = crate::BitReader; #[doc = "Field `LCK14` writer - Port x lock bit y (y= 0..15)"] pub type LCK14_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK15` reader - Port x lock bit y (y= 0..15)"] pub type LCK15_R = crate::BitReader; #[doc = "Field `LCK15` writer - Port x lock bit y (y= 0..15)"] pub type LCK15_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCKK` reader - Port x lock bit y (y= 0..15)"] pub type LCKK_R = crate::BitReader; #[doc = "Field `LCKK` writer - Port x lock bit y (y= 0..15)"] pub type LCKK_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; impl R { #[doc = "Bit 0 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck0(&self) -> LCK0_R { LCK0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck1(&self) -> LCK1_R { LCK1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck2(&self) -> LCK2_R { LCK2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck3(&self) -> LCK3_R { LCK3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck4(&self) -> LCK4_R { LCK4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck5(&self) -> LCK5_R { LCK5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck6(&self) -> LCK6_R { LCK6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck7(&self) -> LCK7_R { LCK7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck8(&self) -> LCK8_R { LCK8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck9(&self) -> LCK9_R { LCK9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck10(&self) -> LCK10_R { LCK10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck11(&self) -> LCK11_R { LCK11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck12(&self) -> LCK12_R { LCK12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck13(&self) -> LCK13_R { LCK13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck14(&self) -> LCK14_R { LCK14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck15(&self) -> LCK15_R { LCK15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lckk(&self) -> LCKK_R { LCKK_R::new(((self.bits >> 16) & 1) != 0) } } impl W { #[doc = "Bit 0 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck0(&mut self) -> LCK0_W<0> { LCK0_W::new(self) } #[doc = "Bit 1 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck1(&mut self) -> LCK1_W<1> { LCK1_W::new(self) } #[doc = "Bit 2 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck2(&mut self) -> LCK2_W<2> { LCK2_W::new(self) } #[doc = "Bit 3 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck3(&mut self) -> LCK3_W<3> { LCK3_W::new(self) } #[doc = "Bit 4 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck4(&mut self) -> LCK4_W<4> { LCK4_W::new(self) } #[doc = "Bit 5 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck5(&mut self) -> LCK5_W<5> { LCK5_W::new(self) } #[doc = "Bit 6 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck6(&mut self) -> LCK6_W<6> { LCK6_W::new(self) } #[doc = "Bit 7 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck7(&mut self) -> LCK7_W<7> { LCK7_W::new(self) } #[doc = "Bit 8 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck8(&mut self) -> LCK8_W<8> { LCK8_W::new(self) } #[doc = "Bit 9 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck9(&mut self) -> LCK9_W<9> { LCK9_W::new(self) } #[doc = "Bit 10 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck10(&mut self) -> LCK10_W<10> { LCK10_W::new(self) } #[doc = "Bit 11 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck11(&mut self) -> LCK11_W<11> { LCK11_W::new(self) } #[doc = "Bit 12 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck12(&mut self) -> LCK12_W<12> { LCK12_W::new(self) } #[doc = "Bit 13 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck13(&mut self) -> LCK13_W<13> { LCK13_W::new(self) } #[doc = "Bit 14 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck14(&mut self) -> LCK14_W<14> { LCK14_W::new(self) } #[doc = "Bit 15 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck15(&mut self) -> LCK15_W<15> { LCK15_W::new(self) } #[doc = "Bit 16 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lckk(&mut self) -> LCKK_W<16> { LCKK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port configuration lock register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lckr](index.html) module"] pub struct LCKR_SPEC; impl crate::RegisterSpec for LCKR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [lckr::R](R) reader structure"] impl crate::Readable for LCKR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [lckr::W](W) writer structure"] impl crate::Writable for LCKR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets LCKR to value 0"] impl crate::Resettable for LCKR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "AFRL (rw) register accessor: an alias for `Reg`"] pub type AFRL = crate::Reg; #[doc = "GPIO alternate function low register"] pub mod afrl { #[doc = "Register `AFRL` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `AFRL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `AFSEL0` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL0_R = crate::FieldReader; #[doc = "Field `AFSEL0` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL0_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL1` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL1_R = crate::FieldReader; #[doc = "Field `AFSEL1` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL2` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL2_R = crate::FieldReader; #[doc = "Field `AFSEL2` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL2_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL3` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL3_R = crate::FieldReader; #[doc = "Field `AFSEL3` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL3_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL4` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL4_R = crate::FieldReader; #[doc = "Field `AFSEL4` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL4_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL5` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL5_R = crate::FieldReader; #[doc = "Field `AFSEL5` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL5_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL6` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL6_R = crate::FieldReader; #[doc = "Field `AFSEL6` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL6_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL7` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL7_R = crate::FieldReader; #[doc = "Field `AFSEL7` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL7_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; impl R { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel0(&self) -> AFSEL0_R { AFSEL0_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel1(&self) -> AFSEL1_R { AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel2(&self) -> AFSEL2_R { AFSEL2_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel3(&self) -> AFSEL3_R { AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel4(&self) -> AFSEL4_R { AFSEL4_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel5(&self) -> AFSEL5_R { AFSEL5_R::new(((self.bits >> 20) & 0x0f) as u8) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel6(&self) -> AFSEL6_R { AFSEL6_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel7(&self) -> AFSEL7_R { AFSEL7_R::new(((self.bits >> 28) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel0(&mut self) -> AFSEL0_W<0> { AFSEL0_W::new(self) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel1(&mut self) -> AFSEL1_W<4> { AFSEL1_W::new(self) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel2(&mut self) -> AFSEL2_W<8> { AFSEL2_W::new(self) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel3(&mut self) -> AFSEL3_W<12> { AFSEL3_W::new(self) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel4(&mut self) -> AFSEL4_W<16> { AFSEL4_W::new(self) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel5(&mut self) -> AFSEL5_W<20> { AFSEL5_W::new(self) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel6(&mut self) -> AFSEL6_W<24> { AFSEL6_W::new(self) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel7(&mut self) -> AFSEL7_W<28> { AFSEL7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO alternate function low register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [afrl](index.html) module"] pub struct AFRL_SPEC; impl crate::RegisterSpec for AFRL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [afrl::R](R) reader structure"] impl crate::Readable for AFRL_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [afrl::W](W) writer structure"] impl crate::Writable for AFRL_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets AFRL to value 0"] impl crate::Resettable for AFRL_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "AFRH (rw) register accessor: an alias for `Reg`"] pub type AFRH = crate::Reg; #[doc = "GPIO alternate function high register"] pub mod afrh { #[doc = "Register `AFRH` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `AFRH` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `AFSEL8` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL8_R = crate::FieldReader; #[doc = "Field `AFSEL8` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL8_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL9` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL9_R = crate::FieldReader; #[doc = "Field `AFSEL9` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL9_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL10` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL10_R = crate::FieldReader; #[doc = "Field `AFSEL10` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL10_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL11` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL11_R = crate::FieldReader; #[doc = "Field `AFSEL11` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL11_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL12` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL12_R = crate::FieldReader; #[doc = "Field `AFSEL12` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL12_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL13` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL13_R = crate::FieldReader; #[doc = "Field `AFSEL13` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL13_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL14` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL14_R = crate::FieldReader; #[doc = "Field `AFSEL14` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL14_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL15` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL15_R = crate::FieldReader; #[doc = "Field `AFSEL15` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL15_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; impl R { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel8(&self) -> AFSEL8_R { AFSEL8_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel9(&self) -> AFSEL9_R { AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel10(&self) -> AFSEL10_R { AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel11(&self) -> AFSEL11_R { AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel12(&self) -> AFSEL12_R { AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel13(&self) -> AFSEL13_R { AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel14(&self) -> AFSEL14_R { AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel15(&self) -> AFSEL15_R { AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel8(&mut self) -> AFSEL8_W<0> { AFSEL8_W::new(self) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel9(&mut self) -> AFSEL9_W<4> { AFSEL9_W::new(self) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel10(&mut self) -> AFSEL10_W<8> { AFSEL10_W::new(self) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel11(&mut self) -> AFSEL11_W<12> { AFSEL11_W::new(self) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel12(&mut self) -> AFSEL12_W<16> { AFSEL12_W::new(self) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel13(&mut self) -> AFSEL13_W<20> { AFSEL13_W::new(self) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel14(&mut self) -> AFSEL14_W<24> { AFSEL14_W::new(self) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel15(&mut self) -> AFSEL15_W<28> { AFSEL15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO alternate function high register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [afrh](index.html) module"] pub struct AFRH_SPEC; impl crate::RegisterSpec for AFRH_SPEC { type Ux = u32; } #[doc = "`read()` method returns [afrh::R](R) reader structure"] impl crate::Readable for AFRH_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [afrh::W](W) writer structure"] impl crate::Writable for AFRH_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets AFRH to value 0"] impl crate::Resettable for AFRH_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BRR (w) register accessor: an alias for `Reg`"] pub type BRR = crate::Reg; #[doc = "port bit reset register"] pub mod brr { #[doc = "Register `BRR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `BR0` writer - Port Reset bit"] pub type BR0_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR1` writer - Port Reset bit"] pub type BR1_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR2` writer - Port Reset bit"] pub type BR2_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR3` writer - Port Reset bit"] pub type BR3_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR4` writer - Port Reset bit"] pub type BR4_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR5` writer - Port Reset bit"] pub type BR5_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR6` writer - Port Reset bit"] pub type BR6_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR7` writer - Port Reset bit"] pub type BR7_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR8` writer - Port Reset bit"] pub type BR8_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR9` writer - Port Reset bit"] pub type BR9_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR10` writer - Port Reset bit"] pub type BR10_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR11` writer - Port Reset bit"] pub type BR11_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR12` writer - Port Reset bit"] pub type BR12_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR13` writer - Port Reset bit"] pub type BR13_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR14` writer - Port Reset bit"] pub type BR14_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR15` writer - Port Reset bit"] pub type BR15_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; impl W { #[doc = "Bit 0 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br0(&mut self) -> BR0_W<0> { BR0_W::new(self) } #[doc = "Bit 1 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br1(&mut self) -> BR1_W<1> { BR1_W::new(self) } #[doc = "Bit 2 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br2(&mut self) -> BR2_W<2> { BR2_W::new(self) } #[doc = "Bit 3 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br3(&mut self) -> BR3_W<3> { BR3_W::new(self) } #[doc = "Bit 4 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br4(&mut self) -> BR4_W<4> { BR4_W::new(self) } #[doc = "Bit 5 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br5(&mut self) -> BR5_W<5> { BR5_W::new(self) } #[doc = "Bit 6 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br6(&mut self) -> BR6_W<6> { BR6_W::new(self) } #[doc = "Bit 7 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br7(&mut self) -> BR7_W<7> { BR7_W::new(self) } #[doc = "Bit 8 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br8(&mut self) -> BR8_W<8> { BR8_W::new(self) } #[doc = "Bit 9 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br9(&mut self) -> BR9_W<9> { BR9_W::new(self) } #[doc = "Bit 10 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br10(&mut self) -> BR10_W<10> { BR10_W::new(self) } #[doc = "Bit 11 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br11(&mut self) -> BR11_W<11> { BR11_W::new(self) } #[doc = "Bit 12 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br12(&mut self) -> BR12_W<12> { BR12_W::new(self) } #[doc = "Bit 13 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br13(&mut self) -> BR13_W<13> { BR13_W::new(self) } #[doc = "Bit 14 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br14(&mut self) -> BR14_W<14> { BR14_W::new(self) } #[doc = "Bit 15 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br15(&mut self) -> BR15_W<15> { BR15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "port bit reset register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [brr](index.html) module"] pub struct BRR_SPEC; impl crate::RegisterSpec for BRR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [brr::W](W) writer structure"] impl crate::Writable for BRR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BRR to value 0"] impl crate::Resettable for BRR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General-purpose I/Os"] pub struct GPIOB { _marker: PhantomData<*const ()>, } unsafe impl Send for GPIOB {} impl GPIOB { #[doc = r"Pointer to the register block"] pub const PTR: *const gpiob::RegisterBlock = 0x5000_0400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const gpiob::RegisterBlock { Self::PTR } } impl Deref for GPIOB { type Target = gpiob::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for GPIOB { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GPIOB").finish() } } #[doc = "General-purpose I/Os"] pub mod gpiob { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - GPIO port mode register"] pub moder: MODER, #[doc = "0x04 - GPIO port output type register"] pub otyper: OTYPER, #[doc = "0x08 - GPIO port output speed register"] pub ospeedr: OSPEEDR, #[doc = "0x0c - GPIO port pull-up/pull-down register"] pub pupdr: PUPDR, #[doc = "0x10 - GPIO port input data register"] pub idr: IDR, #[doc = "0x14 - GPIO port output data register"] pub odr: ODR, #[doc = "0x18 - GPIO port bit set/reset register"] pub bsrr: BSRR, #[doc = "0x1c - GPIO port configuration lock register"] pub lckr: LCKR, #[doc = "0x20 - GPIO alternate function low register"] pub afrl: AFRL, #[doc = "0x24 - GPIO alternate function high register"] pub afrh: AFRH, #[doc = "0x28 - port bit reset register"] pub brr: BRR, } #[doc = "MODER (rw) register accessor: an alias for `Reg`"] pub type MODER = crate::Reg; #[doc = "GPIO port mode register"] pub mod moder { #[doc = "Register `MODER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `MODER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `MODE0` reader - Port x configuration bits (y = 0..15)"] pub type MODE0_R = crate::FieldReader; #[doc = "Field `MODE0` writer - Port x configuration bits (y = 0..15)"] pub type MODE0_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE1` reader - Port x configuration bits (y = 0..15)"] pub type MODE1_R = crate::FieldReader; #[doc = "Field `MODE1` writer - Port x configuration bits (y = 0..15)"] pub type MODE1_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE2` reader - Port x configuration bits (y = 0..15)"] pub type MODE2_R = crate::FieldReader; #[doc = "Field `MODE2` writer - Port x configuration bits (y = 0..15)"] pub type MODE2_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE3` reader - Port x configuration bits (y = 0..15)"] pub type MODE3_R = crate::FieldReader; #[doc = "Field `MODE3` writer - Port x configuration bits (y = 0..15)"] pub type MODE3_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE4` reader - Port x configuration bits (y = 0..15)"] pub type MODE4_R = crate::FieldReader; #[doc = "Field `MODE4` writer - Port x configuration bits (y = 0..15)"] pub type MODE4_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE5` reader - Port x configuration bits (y = 0..15)"] pub type MODE5_R = crate::FieldReader; #[doc = "Field `MODE5` writer - Port x configuration bits (y = 0..15)"] pub type MODE5_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE6` reader - Port x configuration bits (y = 0..15)"] pub type MODE6_R = crate::FieldReader; #[doc = "Field `MODE6` writer - Port x configuration bits (y = 0..15)"] pub type MODE6_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE7` reader - Port x configuration bits (y = 0..15)"] pub type MODE7_R = crate::FieldReader; #[doc = "Field `MODE7` writer - Port x configuration bits (y = 0..15)"] pub type MODE7_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; #[doc = "Field `MODE8` reader - Port x configuration bits (y = 0..15)"] pub type MODE8_R = crate::FieldReader; #[doc = "Field `MODE8` writer - Port x configuration bits (y = 0..15)"] pub type MODE8_W<'a, const O: u8> = crate::FieldWriter<'a, MODER_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode0(&self) -> MODE0_R { MODE0_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode1(&self) -> MODE1_R { MODE1_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode2(&self) -> MODE2_R { MODE2_R::new(((self.bits >> 4) & 3) as u8) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode3(&self) -> MODE3_R { MODE3_R::new(((self.bits >> 6) & 3) as u8) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode4(&self) -> MODE4_R { MODE4_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode5(&self) -> MODE5_R { MODE5_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode6(&self) -> MODE6_R { MODE6_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode7(&self) -> MODE7_R { MODE7_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn mode8(&self) -> MODE8_R { MODE8_R::new(((self.bits >> 16) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode0(&mut self) -> MODE0_W<0> { MODE0_W::new(self) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode1(&mut self) -> MODE1_W<2> { MODE1_W::new(self) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode2(&mut self) -> MODE2_W<4> { MODE2_W::new(self) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode3(&mut self) -> MODE3_W<6> { MODE3_W::new(self) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode4(&mut self) -> MODE4_W<8> { MODE4_W::new(self) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode5(&mut self) -> MODE5_W<10> { MODE5_W::new(self) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode6(&mut self) -> MODE6_W<12> { MODE6_W::new(self) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode7(&mut self) -> MODE7_W<14> { MODE7_W::new(self) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn mode8(&mut self) -> MODE8_W<16> { MODE8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port mode register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [moder](index.html) module"] pub struct MODER_SPEC; impl crate::RegisterSpec for MODER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [moder::R](R) reader structure"] impl crate::Readable for MODER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [moder::W](W) writer structure"] impl crate::Writable for MODER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets MODER to value 0xffff_ffff"] impl crate::Resettable for MODER_SPEC { const RESET_VALUE: Self::Ux = 0xffff_ffff; } } #[doc = "OTYPER (rw) register accessor: an alias for `Reg`"] pub type OTYPER = crate::Reg; #[doc = "GPIO port output type register"] pub mod otyper { #[doc = "Register `OTYPER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OTYPER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OT0` reader - Port x configuration bits (y = 0..15)"] pub type OT0_R = crate::BitReader; #[doc = "Field `OT0` writer - Port x configuration bits (y = 0..15)"] pub type OT0_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT1` reader - Port x configuration bits (y = 0..15)"] pub type OT1_R = crate::BitReader; #[doc = "Field `OT1` writer - Port x configuration bits (y = 0..15)"] pub type OT1_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT2` reader - Port x configuration bits (y = 0..15)"] pub type OT2_R = crate::BitReader; #[doc = "Field `OT2` writer - Port x configuration bits (y = 0..15)"] pub type OT2_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT3` reader - Port x configuration bits (y = 0..15)"] pub type OT3_R = crate::BitReader; #[doc = "Field `OT3` writer - Port x configuration bits (y = 0..15)"] pub type OT3_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT4` reader - Port x configuration bits (y = 0..15)"] pub type OT4_R = crate::BitReader; #[doc = "Field `OT4` writer - Port x configuration bits (y = 0..15)"] pub type OT4_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT5` reader - Port x configuration bits (y = 0..15)"] pub type OT5_R = crate::BitReader; #[doc = "Field `OT5` writer - Port x configuration bits (y = 0..15)"] pub type OT5_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT6` reader - Port x configuration bits (y = 0..15)"] pub type OT6_R = crate::BitReader; #[doc = "Field `OT6` writer - Port x configuration bits (y = 0..15)"] pub type OT6_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT7` reader - Port x configuration bits (y = 0..15)"] pub type OT7_R = crate::BitReader; #[doc = "Field `OT7` writer - Port x configuration bits (y = 0..15)"] pub type OT7_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; #[doc = "Field `OT8` reader - Port x configuration bits (y = 0..15)"] pub type OT8_R = crate::BitReader; #[doc = "Field `OT8` writer - Port x configuration bits (y = 0..15)"] pub type OT8_W<'a, const O: u8> = crate::BitWriter<'a, OTYPER_SPEC, O>; impl R { #[doc = "Bit 0 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot0(&self) -> OT0_R { OT0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot1(&self) -> OT1_R { OT1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot2(&self) -> OT2_R { OT2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot3(&self) -> OT3_R { OT3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot4(&self) -> OT4_R { OT4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot5(&self) -> OT5_R { OT5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot6(&self) -> OT6_R { OT6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot7(&self) -> OT7_R { OT7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ot8(&self) -> OT8_R { OT8_R::new(((self.bits >> 8) & 1) != 0) } } impl W { #[doc = "Bit 0 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot0(&mut self) -> OT0_W<0> { OT0_W::new(self) } #[doc = "Bit 1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot1(&mut self) -> OT1_W<1> { OT1_W::new(self) } #[doc = "Bit 2 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot2(&mut self) -> OT2_W<2> { OT2_W::new(self) } #[doc = "Bit 3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot3(&mut self) -> OT3_W<3> { OT3_W::new(self) } #[doc = "Bit 4 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot4(&mut self) -> OT4_W<4> { OT4_W::new(self) } #[doc = "Bit 5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot5(&mut self) -> OT5_W<5> { OT5_W::new(self) } #[doc = "Bit 6 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot6(&mut self) -> OT6_W<6> { OT6_W::new(self) } #[doc = "Bit 7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot7(&mut self) -> OT7_W<7> { OT7_W::new(self) } #[doc = "Bit 8 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ot8(&mut self) -> OT8_W<8> { OT8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port output type register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [otyper](index.html) module"] pub struct OTYPER_SPEC; impl crate::RegisterSpec for OTYPER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [otyper::R](R) reader structure"] impl crate::Readable for OTYPER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [otyper::W](W) writer structure"] impl crate::Writable for OTYPER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OTYPER to value 0"] impl crate::Resettable for OTYPER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "OSPEEDR (rw) register accessor: an alias for `Reg`"] pub type OSPEEDR = crate::Reg; #[doc = "GPIO port output speed register"] pub mod ospeedr { #[doc = "Register `OSPEEDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OSPEEDR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OSPEED0` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED0_R = crate::FieldReader; #[doc = "Field `OSPEED0` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED0_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED1` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED1_R = crate::FieldReader; #[doc = "Field `OSPEED1` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED1_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED2` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED2_R = crate::FieldReader; #[doc = "Field `OSPEED2` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED2_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED3` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED3_R = crate::FieldReader; #[doc = "Field `OSPEED3` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED3_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED4` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED4_R = crate::FieldReader; #[doc = "Field `OSPEED4` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED4_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED5` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED5_R = crate::FieldReader; #[doc = "Field `OSPEED5` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED5_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED6` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED6_R = crate::FieldReader; #[doc = "Field `OSPEED6` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED6_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED7` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED7_R = crate::FieldReader; #[doc = "Field `OSPEED7` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED7_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; #[doc = "Field `OSPEED8` reader - Port x configuration bits (y = 0..15)"] pub type OSPEED8_R = crate::FieldReader; #[doc = "Field `OSPEED8` writer - Port x configuration bits (y = 0..15)"] pub type OSPEED8_W<'a, const O: u8> = crate::FieldWriter<'a, OSPEEDR_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed0(&self) -> OSPEED0_R { OSPEED0_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed1(&self) -> OSPEED1_R { OSPEED1_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed2(&self) -> OSPEED2_R { OSPEED2_R::new(((self.bits >> 4) & 3) as u8) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed3(&self) -> OSPEED3_R { OSPEED3_R::new(((self.bits >> 6) & 3) as u8) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed4(&self) -> OSPEED4_R { OSPEED4_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed5(&self) -> OSPEED5_R { OSPEED5_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed6(&self) -> OSPEED6_R { OSPEED6_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed7(&self) -> OSPEED7_R { OSPEED7_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn ospeed8(&self) -> OSPEED8_R { OSPEED8_R::new(((self.bits >> 16) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed0(&mut self) -> OSPEED0_W<0> { OSPEED0_W::new(self) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed1(&mut self) -> OSPEED1_W<2> { OSPEED1_W::new(self) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed2(&mut self) -> OSPEED2_W<4> { OSPEED2_W::new(self) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed3(&mut self) -> OSPEED3_W<6> { OSPEED3_W::new(self) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed4(&mut self) -> OSPEED4_W<8> { OSPEED4_W::new(self) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed5(&mut self) -> OSPEED5_W<10> { OSPEED5_W::new(self) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed6(&mut self) -> OSPEED6_W<12> { OSPEED6_W::new(self) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed7(&mut self) -> OSPEED7_W<14> { OSPEED7_W::new(self) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn ospeed8(&mut self) -> OSPEED8_W<16> { OSPEED8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port output speed register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ospeedr](index.html) module"] pub struct OSPEEDR_SPEC; impl crate::RegisterSpec for OSPEEDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ospeedr::R](R) reader structure"] impl crate::Readable for OSPEEDR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ospeedr::W](W) writer structure"] impl crate::Writable for OSPEEDR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OSPEEDR to value 0"] impl crate::Resettable for OSPEEDR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PUPDR (rw) register accessor: an alias for `Reg`"] pub type PUPDR = crate::Reg; #[doc = "GPIO port pull-up/pull-down register"] pub mod pupdr { #[doc = "Register `PUPDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PUPDR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PUPD0` reader - Port x configuration bits (y = 0..15)"] pub type PUPD0_R = crate::FieldReader; #[doc = "Field `PUPD0` writer - Port x configuration bits (y = 0..15)"] pub type PUPD0_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD1` reader - Port x configuration bits (y = 0..15)"] pub type PUPD1_R = crate::FieldReader; #[doc = "Field `PUPD1` writer - Port x configuration bits (y = 0..15)"] pub type PUPD1_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD2` reader - Port x configuration bits (y = 0..15)"] pub type PUPD2_R = crate::FieldReader; #[doc = "Field `PUPD2` writer - Port x configuration bits (y = 0..15)"] pub type PUPD2_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD3` reader - Port x configuration bits (y = 0..15)"] pub type PUPD3_R = crate::FieldReader; #[doc = "Field `PUPD3` writer - Port x configuration bits (y = 0..15)"] pub type PUPD3_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD4` reader - Port x configuration bits (y = 0..15)"] pub type PUPD4_R = crate::FieldReader; #[doc = "Field `PUPD4` writer - Port x configuration bits (y = 0..15)"] pub type PUPD4_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD5` reader - Port x configuration bits (y = 0..15)"] pub type PUPD5_R = crate::FieldReader; #[doc = "Field `PUPD5` writer - Port x configuration bits (y = 0..15)"] pub type PUPD5_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD6` reader - Port x configuration bits (y = 0..15)"] pub type PUPD6_R = crate::FieldReader; #[doc = "Field `PUPD6` writer - Port x configuration bits (y = 0..15)"] pub type PUPD6_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD7` reader - Port x configuration bits (y = 0..15)"] pub type PUPD7_R = crate::FieldReader; #[doc = "Field `PUPD7` writer - Port x configuration bits (y = 0..15)"] pub type PUPD7_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; #[doc = "Field `PUPD8` reader - Port x configuration bits (y = 0..15)"] pub type PUPD8_R = crate::FieldReader; #[doc = "Field `PUPD8` writer - Port x configuration bits (y = 0..15)"] pub type PUPD8_W<'a, const O: u8> = crate::FieldWriter<'a, PUPDR_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd0(&self) -> PUPD0_R { PUPD0_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd1(&self) -> PUPD1_R { PUPD1_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd2(&self) -> PUPD2_R { PUPD2_R::new(((self.bits >> 4) & 3) as u8) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd3(&self) -> PUPD3_R { PUPD3_R::new(((self.bits >> 6) & 3) as u8) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd4(&self) -> PUPD4_R { PUPD4_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd5(&self) -> PUPD5_R { PUPD5_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd6(&self) -> PUPD6_R { PUPD6_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd7(&self) -> PUPD7_R { PUPD7_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] pub fn pupd8(&self) -> PUPD8_R { PUPD8_R::new(((self.bits >> 16) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd0(&mut self) -> PUPD0_W<0> { PUPD0_W::new(self) } #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd1(&mut self) -> PUPD1_W<2> { PUPD1_W::new(self) } #[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd2(&mut self) -> PUPD2_W<4> { PUPD2_W::new(self) } #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd3(&mut self) -> PUPD3_W<6> { PUPD3_W::new(self) } #[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd4(&mut self) -> PUPD4_W<8> { PUPD4_W::new(self) } #[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd5(&mut self) -> PUPD5_W<10> { PUPD5_W::new(self) } #[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd6(&mut self) -> PUPD6_W<12> { PUPD6_W::new(self) } #[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd7(&mut self) -> PUPD7_W<14> { PUPD7_W::new(self) } #[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"] #[inline(always)] #[must_use] pub fn pupd8(&mut self) -> PUPD8_W<16> { PUPD8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port pull-up/pull-down register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pupdr](index.html) module"] pub struct PUPDR_SPEC; impl crate::RegisterSpec for PUPDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pupdr::R](R) reader structure"] impl crate::Readable for PUPDR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pupdr::W](W) writer structure"] impl crate::Writable for PUPDR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PUPDR to value 0"] impl crate::Resettable for PUPDR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IDR (r) register accessor: an alias for `Reg`"] pub type IDR = crate::Reg; #[doc = "GPIO port input data register"] pub mod idr { #[doc = "Register `IDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `ID0` reader - Port input data (y = 0..15)"] pub type ID0_R = crate::BitReader; #[doc = "Field `ID1` reader - Port input data (y = 0..15)"] pub type ID1_R = crate::BitReader; #[doc = "Field `ID2` reader - Port input data (y = 0..15)"] pub type ID2_R = crate::BitReader; #[doc = "Field `ID3` reader - Port input data (y = 0..15)"] pub type ID3_R = crate::BitReader; #[doc = "Field `ID4` reader - Port input data (y = 0..15)"] pub type ID4_R = crate::BitReader; #[doc = "Field `ID5` reader - Port input data (y = 0..15)"] pub type ID5_R = crate::BitReader; #[doc = "Field `ID6` reader - Port input data (y = 0..15)"] pub type ID6_R = crate::BitReader; #[doc = "Field `ID7` reader - Port input data (y = 0..15)"] pub type ID7_R = crate::BitReader; #[doc = "Field `ID8` reader - Port input data (y = 0..15)"] pub type ID8_R = crate::BitReader; impl R { #[doc = "Bit 0 - Port input data (y = 0..15)"] #[inline(always)] pub fn id0(&self) -> ID0_R { ID0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port input data (y = 0..15)"] #[inline(always)] pub fn id1(&self) -> ID1_R { ID1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port input data (y = 0..15)"] #[inline(always)] pub fn id2(&self) -> ID2_R { ID2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port input data (y = 0..15)"] #[inline(always)] pub fn id3(&self) -> ID3_R { ID3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port input data (y = 0..15)"] #[inline(always)] pub fn id4(&self) -> ID4_R { ID4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port input data (y = 0..15)"] #[inline(always)] pub fn id5(&self) -> ID5_R { ID5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port input data (y = 0..15)"] #[inline(always)] pub fn id6(&self) -> ID6_R { ID6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port input data (y = 0..15)"] #[inline(always)] pub fn id7(&self) -> ID7_R { ID7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port input data (y = 0..15)"] #[inline(always)] pub fn id8(&self) -> ID8_R { ID8_R::new(((self.bits >> 8) & 1) != 0) } } #[doc = "GPIO port input data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [idr::R](R) reader structure"] impl crate::Readable for IDR_SPEC { type Reader = R; } #[doc = "`reset()` method sets IDR to value 0"] impl crate::Resettable for IDR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ODR (rw) register accessor: an alias for `Reg`"] pub type ODR = crate::Reg; #[doc = "GPIO port output data register"] pub mod odr { #[doc = "Register `ODR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ODR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OD0` reader - Port output data (y = 0..15)"] pub type OD0_R = crate::BitReader; #[doc = "Field `OD0` writer - Port output data (y = 0..15)"] pub type OD0_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD1` reader - Port output data (y = 0..15)"] pub type OD1_R = crate::BitReader; #[doc = "Field `OD1` writer - Port output data (y = 0..15)"] pub type OD1_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD2` reader - Port output data (y = 0..15)"] pub type OD2_R = crate::BitReader; #[doc = "Field `OD2` writer - Port output data (y = 0..15)"] pub type OD2_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD3` reader - Port output data (y = 0..15)"] pub type OD3_R = crate::BitReader; #[doc = "Field `OD3` writer - Port output data (y = 0..15)"] pub type OD3_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD4` reader - Port output data (y = 0..15)"] pub type OD4_R = crate::BitReader; #[doc = "Field `OD4` writer - Port output data (y = 0..15)"] pub type OD4_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD5` reader - Port output data (y = 0..15)"] pub type OD5_R = crate::BitReader; #[doc = "Field `OD5` writer - Port output data (y = 0..15)"] pub type OD5_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD6` reader - Port output data (y = 0..15)"] pub type OD6_R = crate::BitReader; #[doc = "Field `OD6` writer - Port output data (y = 0..15)"] pub type OD6_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD7` reader - Port output data (y = 0..15)"] pub type OD7_R = crate::BitReader; #[doc = "Field `OD7` writer - Port output data (y = 0..15)"] pub type OD7_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; #[doc = "Field `OD8` reader - Port output data (y = 0..15)"] pub type OD8_R = crate::BitReader; #[doc = "Field `OD8` writer - Port output data (y = 0..15)"] pub type OD8_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; impl R { #[doc = "Bit 0 - Port output data (y = 0..15)"] #[inline(always)] pub fn od0(&self) -> OD0_R { OD0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port output data (y = 0..15)"] #[inline(always)] pub fn od1(&self) -> OD1_R { OD1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port output data (y = 0..15)"] #[inline(always)] pub fn od2(&self) -> OD2_R { OD2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port output data (y = 0..15)"] #[inline(always)] pub fn od3(&self) -> OD3_R { OD3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port output data (y = 0..15)"] #[inline(always)] pub fn od4(&self) -> OD4_R { OD4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port output data (y = 0..15)"] #[inline(always)] pub fn od5(&self) -> OD5_R { OD5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port output data (y = 0..15)"] #[inline(always)] pub fn od6(&self) -> OD6_R { OD6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port output data (y = 0..15)"] #[inline(always)] pub fn od7(&self) -> OD7_R { OD7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port output data (y = 0..15)"] #[inline(always)] pub fn od8(&self) -> OD8_R { OD8_R::new(((self.bits >> 8) & 1) != 0) } } impl W { #[doc = "Bit 0 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od0(&mut self) -> OD0_W<0> { OD0_W::new(self) } #[doc = "Bit 1 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od1(&mut self) -> OD1_W<1> { OD1_W::new(self) } #[doc = "Bit 2 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od2(&mut self) -> OD2_W<2> { OD2_W::new(self) } #[doc = "Bit 3 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od3(&mut self) -> OD3_W<3> { OD3_W::new(self) } #[doc = "Bit 4 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od4(&mut self) -> OD4_W<4> { OD4_W::new(self) } #[doc = "Bit 5 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od5(&mut self) -> OD5_W<5> { OD5_W::new(self) } #[doc = "Bit 6 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od6(&mut self) -> OD6_W<6> { OD6_W::new(self) } #[doc = "Bit 7 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od7(&mut self) -> OD7_W<7> { OD7_W::new(self) } #[doc = "Bit 8 - Port output data (y = 0..15)"] #[inline(always)] #[must_use] pub fn od8(&mut self) -> OD8_W<8> { OD8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port output data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odr](index.html) module"] pub struct ODR_SPEC; impl crate::RegisterSpec for ODR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [odr::R](R) reader structure"] impl crate::Readable for ODR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [odr::W](W) writer structure"] impl crate::Writable for ODR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ODR to value 0"] impl crate::Resettable for ODR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BSRR (w) register accessor: an alias for `Reg`"] pub type BSRR = crate::Reg; #[doc = "GPIO port bit set/reset register"] pub mod bsrr { #[doc = "Register `BSRR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `BS0` writer - Port x set bit y (y= 0..15)"] pub type BS0_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS1` writer - Port x set bit y (y= 0..15)"] pub type BS1_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS2` writer - Port x set bit y (y= 0..15)"] pub type BS2_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS3` writer - Port x set bit y (y= 0..15)"] pub type BS3_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS4` writer - Port x set bit y (y= 0..15)"] pub type BS4_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS5` writer - Port x set bit y (y= 0..15)"] pub type BS5_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS6` writer - Port x set bit y (y= 0..15)"] pub type BS6_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS7` writer - Port x set bit y (y= 0..15)"] pub type BS7_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BS8` writer - Port x set bit y (y= 0..15)"] pub type BS8_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR0` writer - Port x set bit y (y= 0..15)"] pub type BR0_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR1` writer - Port x reset bit y (y = 0..15)"] pub type BR1_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR2` writer - Port x reset bit y (y = 0..15)"] pub type BR2_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR3` writer - Port x reset bit y (y = 0..15)"] pub type BR3_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR4` writer - Port x reset bit y (y = 0..15)"] pub type BR4_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR5` writer - Port x reset bit y (y = 0..15)"] pub type BR5_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR6` writer - Port x reset bit y (y = 0..15)"] pub type BR6_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR7` writer - Port x reset bit y (y = 0..15)"] pub type BR7_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; #[doc = "Field `BR8` writer - Port x reset bit y (y = 0..15)"] pub type BR8_W<'a, const O: u8> = crate::BitWriter<'a, BSRR_SPEC, O>; impl W { #[doc = "Bit 0 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs0(&mut self) -> BS0_W<0> { BS0_W::new(self) } #[doc = "Bit 1 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs1(&mut self) -> BS1_W<1> { BS1_W::new(self) } #[doc = "Bit 2 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs2(&mut self) -> BS2_W<2> { BS2_W::new(self) } #[doc = "Bit 3 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs3(&mut self) -> BS3_W<3> { BS3_W::new(self) } #[doc = "Bit 4 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs4(&mut self) -> BS4_W<4> { BS4_W::new(self) } #[doc = "Bit 5 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs5(&mut self) -> BS5_W<5> { BS5_W::new(self) } #[doc = "Bit 6 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs6(&mut self) -> BS6_W<6> { BS6_W::new(self) } #[doc = "Bit 7 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs7(&mut self) -> BS7_W<7> { BS7_W::new(self) } #[doc = "Bit 8 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn bs8(&mut self) -> BS8_W<8> { BS8_W::new(self) } #[doc = "Bit 16 - Port x set bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn br0(&mut self) -> BR0_W<16> { BR0_W::new(self) } #[doc = "Bit 17 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br1(&mut self) -> BR1_W<17> { BR1_W::new(self) } #[doc = "Bit 18 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br2(&mut self) -> BR2_W<18> { BR2_W::new(self) } #[doc = "Bit 19 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br3(&mut self) -> BR3_W<19> { BR3_W::new(self) } #[doc = "Bit 20 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br4(&mut self) -> BR4_W<20> { BR4_W::new(self) } #[doc = "Bit 21 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br5(&mut self) -> BR5_W<21> { BR5_W::new(self) } #[doc = "Bit 22 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br6(&mut self) -> BR6_W<22> { BR6_W::new(self) } #[doc = "Bit 23 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br7(&mut self) -> BR7_W<23> { BR7_W::new(self) } #[doc = "Bit 24 - Port x reset bit y (y = 0..15)"] #[inline(always)] #[must_use] pub fn br8(&mut self) -> BR8_W<24> { BR8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port bit set/reset register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bsrr](index.html) module"] pub struct BSRR_SPEC; impl crate::RegisterSpec for BSRR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [bsrr::W](W) writer structure"] impl crate::Writable for BSRR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BSRR to value 0"] impl crate::Resettable for BSRR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "LCKR (rw) register accessor: an alias for `Reg`"] pub type LCKR = crate::Reg; #[doc = "GPIO port configuration lock register"] pub mod lckr { #[doc = "Register `LCKR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `LCKR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LCK0` reader - Port x lock bit y (y= 0..15)"] pub type LCK0_R = crate::BitReader; #[doc = "Field `LCK0` writer - Port x lock bit y (y= 0..15)"] pub type LCK0_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK1` reader - Port x lock bit y (y= 0..15)"] pub type LCK1_R = crate::BitReader; #[doc = "Field `LCK1` writer - Port x lock bit y (y= 0..15)"] pub type LCK1_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK2` reader - Port x lock bit y (y= 0..15)"] pub type LCK2_R = crate::BitReader; #[doc = "Field `LCK2` writer - Port x lock bit y (y= 0..15)"] pub type LCK2_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK3` reader - Port x lock bit y (y= 0..15)"] pub type LCK3_R = crate::BitReader; #[doc = "Field `LCK3` writer - Port x lock bit y (y= 0..15)"] pub type LCK3_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK4` reader - Port x lock bit y (y= 0..15)"] pub type LCK4_R = crate::BitReader; #[doc = "Field `LCK4` writer - Port x lock bit y (y= 0..15)"] pub type LCK4_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK5` reader - Port x lock bit y (y= 0..15)"] pub type LCK5_R = crate::BitReader; #[doc = "Field `LCK5` writer - Port x lock bit y (y= 0..15)"] pub type LCK5_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK6` reader - Port x lock bit y (y= 0..15)"] pub type LCK6_R = crate::BitReader; #[doc = "Field `LCK6` writer - Port x lock bit y (y= 0..15)"] pub type LCK6_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK7` reader - Port x lock bit y (y= 0..15)"] pub type LCK7_R = crate::BitReader; #[doc = "Field `LCK7` writer - Port x lock bit y (y= 0..15)"] pub type LCK7_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCK8` reader - Port x lock bit y (y= 0..15)"] pub type LCK8_R = crate::BitReader; #[doc = "Field `LCK8` writer - Port x lock bit y (y= 0..15)"] pub type LCK8_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; #[doc = "Field `LCKK` reader - Port x lock bit y (y= 0..15)"] pub type LCKK_R = crate::BitReader; #[doc = "Field `LCKK` writer - Port x lock bit y (y= 0..15)"] pub type LCKK_W<'a, const O: u8> = crate::BitWriter<'a, LCKR_SPEC, O>; impl R { #[doc = "Bit 0 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck0(&self) -> LCK0_R { LCK0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck1(&self) -> LCK1_R { LCK1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck2(&self) -> LCK2_R { LCK2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck3(&self) -> LCK3_R { LCK3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck4(&self) -> LCK4_R { LCK4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck5(&self) -> LCK5_R { LCK5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck6(&self) -> LCK6_R { LCK6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck7(&self) -> LCK7_R { LCK7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lck8(&self) -> LCK8_R { LCK8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 16 - Port x lock bit y (y= 0..15)"] #[inline(always)] pub fn lckk(&self) -> LCKK_R { LCKK_R::new(((self.bits >> 16) & 1) != 0) } } impl W { #[doc = "Bit 0 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck0(&mut self) -> LCK0_W<0> { LCK0_W::new(self) } #[doc = "Bit 1 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck1(&mut self) -> LCK1_W<1> { LCK1_W::new(self) } #[doc = "Bit 2 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck2(&mut self) -> LCK2_W<2> { LCK2_W::new(self) } #[doc = "Bit 3 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck3(&mut self) -> LCK3_W<3> { LCK3_W::new(self) } #[doc = "Bit 4 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck4(&mut self) -> LCK4_W<4> { LCK4_W::new(self) } #[doc = "Bit 5 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck5(&mut self) -> LCK5_W<5> { LCK5_W::new(self) } #[doc = "Bit 6 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck6(&mut self) -> LCK6_W<6> { LCK6_W::new(self) } #[doc = "Bit 7 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck7(&mut self) -> LCK7_W<7> { LCK7_W::new(self) } #[doc = "Bit 8 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lck8(&mut self) -> LCK8_W<8> { LCK8_W::new(self) } #[doc = "Bit 16 - Port x lock bit y (y= 0..15)"] #[inline(always)] #[must_use] pub fn lckk(&mut self) -> LCKK_W<16> { LCKK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO port configuration lock register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lckr](index.html) module"] pub struct LCKR_SPEC; impl crate::RegisterSpec for LCKR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [lckr::R](R) reader structure"] impl crate::Readable for LCKR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [lckr::W](W) writer structure"] impl crate::Writable for LCKR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets LCKR to value 0"] impl crate::Resettable for LCKR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "AFRL (rw) register accessor: an alias for `Reg`"] pub type AFRL = crate::Reg; #[doc = "GPIO alternate function low register"] pub mod afrl { #[doc = "Register `AFRL` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `AFRL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `AFSEL0` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL0_R = crate::FieldReader; #[doc = "Field `AFSEL0` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL0_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL1` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL1_R = crate::FieldReader; #[doc = "Field `AFSEL1` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL2` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL2_R = crate::FieldReader; #[doc = "Field `AFSEL2` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL2_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL3` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL3_R = crate::FieldReader; #[doc = "Field `AFSEL3` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL3_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL4` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL4_R = crate::FieldReader; #[doc = "Field `AFSEL4` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL4_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL5` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL5_R = crate::FieldReader; #[doc = "Field `AFSEL5` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL5_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL6` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL6_R = crate::FieldReader; #[doc = "Field `AFSEL6` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL6_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; #[doc = "Field `AFSEL7` reader - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL7_R = crate::FieldReader; #[doc = "Field `AFSEL7` writer - Alternate function selection for port x bit y (y = 0..7)"] pub type AFSEL7_W<'a, const O: u8> = crate::FieldWriter<'a, AFRL_SPEC, 4, O>; impl R { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel0(&self) -> AFSEL0_R { AFSEL0_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel1(&self) -> AFSEL1_R { AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel2(&self) -> AFSEL2_R { AFSEL2_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel3(&self) -> AFSEL3_R { AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel4(&self) -> AFSEL4_R { AFSEL4_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel5(&self) -> AFSEL5_R { AFSEL5_R::new(((self.bits >> 20) & 0x0f) as u8) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel6(&self) -> AFSEL6_R { AFSEL6_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] pub fn afsel7(&self) -> AFSEL7_R { AFSEL7_R::new(((self.bits >> 28) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel0(&mut self) -> AFSEL0_W<0> { AFSEL0_W::new(self) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel1(&mut self) -> AFSEL1_W<4> { AFSEL1_W::new(self) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel2(&mut self) -> AFSEL2_W<8> { AFSEL2_W::new(self) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel3(&mut self) -> AFSEL3_W<12> { AFSEL3_W::new(self) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel4(&mut self) -> AFSEL4_W<16> { AFSEL4_W::new(self) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel5(&mut self) -> AFSEL5_W<20> { AFSEL5_W::new(self) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel6(&mut self) -> AFSEL6_W<24> { AFSEL6_W::new(self) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"] #[inline(always)] #[must_use] pub fn afsel7(&mut self) -> AFSEL7_W<28> { AFSEL7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO alternate function low register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [afrl](index.html) module"] pub struct AFRL_SPEC; impl crate::RegisterSpec for AFRL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [afrl::R](R) reader structure"] impl crate::Readable for AFRL_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [afrl::W](W) writer structure"] impl crate::Writable for AFRL_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets AFRL to value 0"] impl crate::Resettable for AFRL_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "AFRH (rw) register accessor: an alias for `Reg`"] pub type AFRH = crate::Reg; #[doc = "GPIO alternate function high register"] pub mod afrh { #[doc = "Register `AFRH` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `AFRH` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `AFSEL8` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL8_R = crate::FieldReader; #[doc = "Field `AFSEL8` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL8_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL9` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL9_R = crate::FieldReader; #[doc = "Field `AFSEL9` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL9_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL10` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL10_R = crate::FieldReader; #[doc = "Field `AFSEL10` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL10_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL11` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL11_R = crate::FieldReader; #[doc = "Field `AFSEL11` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL11_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL12` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL12_R = crate::FieldReader; #[doc = "Field `AFSEL12` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL12_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL13` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL13_R = crate::FieldReader; #[doc = "Field `AFSEL13` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL13_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL14` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL14_R = crate::FieldReader; #[doc = "Field `AFSEL14` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL14_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; #[doc = "Field `AFSEL15` reader - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL15_R = crate::FieldReader; #[doc = "Field `AFSEL15` writer - Alternate function selection for port x bit y (y = 8..15)"] pub type AFSEL15_W<'a, const O: u8> = crate::FieldWriter<'a, AFRH_SPEC, 4, O>; impl R { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel8(&self) -> AFSEL8_R { AFSEL8_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel9(&self) -> AFSEL9_R { AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel10(&self) -> AFSEL10_R { AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel11(&self) -> AFSEL11_R { AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel12(&self) -> AFSEL12_R { AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel13(&self) -> AFSEL13_R { AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel14(&self) -> AFSEL14_R { AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] pub fn afsel15(&self) -> AFSEL15_R { AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel8(&mut self) -> AFSEL8_W<0> { AFSEL8_W::new(self) } #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel9(&mut self) -> AFSEL9_W<4> { AFSEL9_W::new(self) } #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel10(&mut self) -> AFSEL10_W<8> { AFSEL10_W::new(self) } #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel11(&mut self) -> AFSEL11_W<12> { AFSEL11_W::new(self) } #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel12(&mut self) -> AFSEL12_W<16> { AFSEL12_W::new(self) } #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel13(&mut self) -> AFSEL13_W<20> { AFSEL13_W::new(self) } #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel14(&mut self) -> AFSEL14_W<24> { AFSEL14_W::new(self) } #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"] #[inline(always)] #[must_use] pub fn afsel15(&mut self) -> AFSEL15_W<28> { AFSEL15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "GPIO alternate function high register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [afrh](index.html) module"] pub struct AFRH_SPEC; impl crate::RegisterSpec for AFRH_SPEC { type Ux = u32; } #[doc = "`read()` method returns [afrh::R](R) reader structure"] impl crate::Readable for AFRH_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [afrh::W](W) writer structure"] impl crate::Writable for AFRH_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets AFRH to value 0"] impl crate::Resettable for AFRH_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BRR (w) register accessor: an alias for `Reg`"] pub type BRR = crate::Reg; #[doc = "port bit reset register"] pub mod brr { #[doc = "Register `BRR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `BR0` writer - Port Reset bit"] pub type BR0_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR1` writer - Port Reset bit"] pub type BR1_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR2` writer - Port Reset bit"] pub type BR2_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR3` writer - Port Reset bit"] pub type BR3_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR4` writer - Port Reset bit"] pub type BR4_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR5` writer - Port Reset bit"] pub type BR5_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR6` writer - Port Reset bit"] pub type BR6_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR7` writer - Port Reset bit"] pub type BR7_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; #[doc = "Field `BR8` writer - Port Reset bit"] pub type BR8_W<'a, const O: u8> = crate::BitWriter<'a, BRR_SPEC, O>; impl W { #[doc = "Bit 0 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br0(&mut self) -> BR0_W<0> { BR0_W::new(self) } #[doc = "Bit 1 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br1(&mut self) -> BR1_W<1> { BR1_W::new(self) } #[doc = "Bit 2 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br2(&mut self) -> BR2_W<2> { BR2_W::new(self) } #[doc = "Bit 3 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br3(&mut self) -> BR3_W<3> { BR3_W::new(self) } #[doc = "Bit 4 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br4(&mut self) -> BR4_W<4> { BR4_W::new(self) } #[doc = "Bit 5 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br5(&mut self) -> BR5_W<5> { BR5_W::new(self) } #[doc = "Bit 6 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br6(&mut self) -> BR6_W<6> { BR6_W::new(self) } #[doc = "Bit 7 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br7(&mut self) -> BR7_W<7> { BR7_W::new(self) } #[doc = "Bit 8 - Port Reset bit"] #[inline(always)] #[must_use] pub fn br8(&mut self) -> BR8_W<8> { BR8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "port bit reset register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [brr](index.html) module"] pub struct BRR_SPEC; impl crate::RegisterSpec for BRR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [brr::W](W) writer structure"] impl crate::Writable for BRR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BRR to value 0"] impl crate::Resettable for BRR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General-purpose I/Os"] pub struct GPIOF { _marker: PhantomData<*const ()>, } unsafe impl Send for GPIOF {} impl GPIOF { #[doc = r"Pointer to the register block"] pub const PTR: *const gpiob::RegisterBlock = 0x5000_1400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const gpiob::RegisterBlock { Self::PTR } } impl Deref for GPIOF { type Target = gpiob::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for GPIOF { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GPIOF").finish() } } #[doc = "General-purpose I/Os"] pub use self::gpiob as gpiof; #[doc = "External interrupt/event controller"] pub struct EXTI { _marker: PhantomData<*const ()>, } unsafe impl Send for EXTI {} impl EXTI { #[doc = r"Pointer to the register block"] pub const PTR: *const exti::RegisterBlock = 0x4002_1800 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const exti::RegisterBlock { Self::PTR } } impl Deref for EXTI { type Target = exti::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for EXTI { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("EXTI").finish() } } #[doc = "External interrupt/event controller"] pub mod exti { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - EXTI rising trigger selection register"] pub rtsr: RTSR, #[doc = "0x04 - EXTI falling trigger selection register"] pub ftsr: FTSR, #[doc = "0x08 - EXTI software interrupt event register"] pub swier: SWIER, #[doc = "0x0c - EXTI pending register"] pub pr: PR, _reserved4: [u8; 0x50], #[doc = "0x60 - EXTI external interrupt selection register"] pub exticr1: EXTICR1, #[doc = "0x64 - EXTI external interrupt selection register"] pub exticr2: EXTICR2, #[doc = "0x68 - EXTI external interrupt selection register"] pub exticr3: EXTICR3, _reserved7: [u8; 0x14], #[doc = "0x80 - EXTI CPU wakeup with interrupt mask register"] pub imr: IMR, #[doc = "0x84 - EXTI CPU wakeup with event mask register"] pub emr: EMR, } #[doc = "RTSR (rw) register accessor: an alias for `Reg`"] pub type RTSR = crate::Reg; #[doc = "EXTI rising trigger selection register"] pub mod rtsr { #[doc = "Register `RTSR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `RTSR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RT0` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT0_R = crate::BitReader; #[doc = "Field `RT0` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT0_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT1` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT1_R = crate::BitReader; #[doc = "Field `RT1` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT1_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT2` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT2_R = crate::BitReader; #[doc = "Field `RT2` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT2_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT3` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT3_R = crate::BitReader; #[doc = "Field `RT3` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT3_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT4` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT4_R = crate::BitReader; #[doc = "Field `RT4` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT4_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT5` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT5_R = crate::BitReader; #[doc = "Field `RT5` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT5_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT6` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT6_R = crate::BitReader; #[doc = "Field `RT6` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT6_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT7` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT7_R = crate::BitReader; #[doc = "Field `RT7` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT7_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT8` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT8_R = crate::BitReader; #[doc = "Field `RT8` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT8_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT9` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT9_R = crate::BitReader; #[doc = "Field `RT9` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT9_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT10` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT10_R = crate::BitReader; #[doc = "Field `RT10` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT10_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT11` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT11_R = crate::BitReader; #[doc = "Field `RT11` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT11_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT12` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT12_R = crate::BitReader; #[doc = "Field `RT12` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT12_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT13` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT13_R = crate::BitReader; #[doc = "Field `RT13` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT13_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT14` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT14_R = crate::BitReader; #[doc = "Field `RT14` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT14_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT15` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT15_R = crate::BitReader; #[doc = "Field `RT15` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT15_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT16` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT16_R = crate::BitReader; #[doc = "Field `RT16` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT16_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT17` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT17_R = crate::BitReader; #[doc = "Field `RT17` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT17_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; #[doc = "Field `RT18` reader - Rising trigger event configuration bit of Configurable Event input"] pub type RT18_R = crate::BitReader; #[doc = "Field `RT18` writer - Rising trigger event configuration bit of Configurable Event input"] pub type RT18_W<'a, const O: u8> = crate::BitWriter<'a, RTSR_SPEC, O>; impl R { #[doc = "Bit 0 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt0(&self) -> RT0_R { RT0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt1(&self) -> RT1_R { RT1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt2(&self) -> RT2_R { RT2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt3(&self) -> RT3_R { RT3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt4(&self) -> RT4_R { RT4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt5(&self) -> RT5_R { RT5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt6(&self) -> RT6_R { RT6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt7(&self) -> RT7_R { RT7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt8(&self) -> RT8_R { RT8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt9(&self) -> RT9_R { RT9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt10(&self) -> RT10_R { RT10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt11(&self) -> RT11_R { RT11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt12(&self) -> RT12_R { RT12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt13(&self) -> RT13_R { RT13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt14(&self) -> RT14_R { RT14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt15(&self) -> RT15_R { RT15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt16(&self) -> RT16_R { RT16_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt17(&self) -> RT17_R { RT17_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn rt18(&self) -> RT18_R { RT18_R::new(((self.bits >> 18) & 1) != 0) } } impl W { #[doc = "Bit 0 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt0(&mut self) -> RT0_W<0> { RT0_W::new(self) } #[doc = "Bit 1 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt1(&mut self) -> RT1_W<1> { RT1_W::new(self) } #[doc = "Bit 2 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt2(&mut self) -> RT2_W<2> { RT2_W::new(self) } #[doc = "Bit 3 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt3(&mut self) -> RT3_W<3> { RT3_W::new(self) } #[doc = "Bit 4 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt4(&mut self) -> RT4_W<4> { RT4_W::new(self) } #[doc = "Bit 5 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt5(&mut self) -> RT5_W<5> { RT5_W::new(self) } #[doc = "Bit 6 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt6(&mut self) -> RT6_W<6> { RT6_W::new(self) } #[doc = "Bit 7 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt7(&mut self) -> RT7_W<7> { RT7_W::new(self) } #[doc = "Bit 8 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt8(&mut self) -> RT8_W<8> { RT8_W::new(self) } #[doc = "Bit 9 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt9(&mut self) -> RT9_W<9> { RT9_W::new(self) } #[doc = "Bit 10 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt10(&mut self) -> RT10_W<10> { RT10_W::new(self) } #[doc = "Bit 11 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt11(&mut self) -> RT11_W<11> { RT11_W::new(self) } #[doc = "Bit 12 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt12(&mut self) -> RT12_W<12> { RT12_W::new(self) } #[doc = "Bit 13 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt13(&mut self) -> RT13_W<13> { RT13_W::new(self) } #[doc = "Bit 14 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt14(&mut self) -> RT14_W<14> { RT14_W::new(self) } #[doc = "Bit 15 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt15(&mut self) -> RT15_W<15> { RT15_W::new(self) } #[doc = "Bit 16 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt16(&mut self) -> RT16_W<16> { RT16_W::new(self) } #[doc = "Bit 17 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt17(&mut self) -> RT17_W<17> { RT17_W::new(self) } #[doc = "Bit 18 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn rt18(&mut self) -> RT18_W<18> { RT18_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI rising trigger selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtsr](index.html) module"] pub struct RTSR_SPEC; impl crate::RegisterSpec for RTSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [rtsr::R](R) reader structure"] impl crate::Readable for RTSR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [rtsr::W](W) writer structure"] impl crate::Writable for RTSR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets RTSR to value 0"] impl crate::Resettable for RTSR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "FTSR (rw) register accessor: an alias for `Reg`"] pub type FTSR = crate::Reg; #[doc = "EXTI falling trigger selection register"] pub mod ftsr { #[doc = "Register `FTSR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `FTSR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `FT0` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT0_R = crate::BitReader; #[doc = "Field `FT0` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT0_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT1` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT1_R = crate::BitReader; #[doc = "Field `FT1` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT1_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT2` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT2_R = crate::BitReader; #[doc = "Field `FT2` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT2_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT3` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT3_R = crate::BitReader; #[doc = "Field `FT3` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT3_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT4` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT4_R = crate::BitReader; #[doc = "Field `FT4` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT4_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT5` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT5_R = crate::BitReader; #[doc = "Field `FT5` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT5_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT6` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT6_R = crate::BitReader; #[doc = "Field `FT6` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT6_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT7` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT7_R = crate::BitReader; #[doc = "Field `FT7` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT7_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT8` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT8_R = crate::BitReader; #[doc = "Field `FT8` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT8_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT9` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT9_R = crate::BitReader; #[doc = "Field `FT9` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT9_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT10` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT10_R = crate::BitReader; #[doc = "Field `FT10` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT10_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT11` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT11_R = crate::BitReader; #[doc = "Field `FT11` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT11_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT12` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT12_R = crate::BitReader; #[doc = "Field `FT12` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT12_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT13` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT13_R = crate::BitReader; #[doc = "Field `FT13` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT13_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT14` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT14_R = crate::BitReader; #[doc = "Field `FT14` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT14_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT15` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT15_R = crate::BitReader; #[doc = "Field `FT15` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT15_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT16` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT16_R = crate::BitReader; #[doc = "Field `FT16` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT16_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT17` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT17_R = crate::BitReader; #[doc = "Field `FT17` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT17_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; #[doc = "Field `FT18` reader - Falling trigger event configuration bit of Configurable Event input"] pub type FT18_R = crate::BitReader; #[doc = "Field `FT18` writer - Falling trigger event configuration bit of Configurable Event input"] pub type FT18_W<'a, const O: u8> = crate::BitWriter<'a, FTSR_SPEC, O>; impl R { #[doc = "Bit 0 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft0(&self) -> FT0_R { FT0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft1(&self) -> FT1_R { FT1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft2(&self) -> FT2_R { FT2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft3(&self) -> FT3_R { FT3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft4(&self) -> FT4_R { FT4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft5(&self) -> FT5_R { FT5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft6(&self) -> FT6_R { FT6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft7(&self) -> FT7_R { FT7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft8(&self) -> FT8_R { FT8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft9(&self) -> FT9_R { FT9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft10(&self) -> FT10_R { FT10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft11(&self) -> FT11_R { FT11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft12(&self) -> FT12_R { FT12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft13(&self) -> FT13_R { FT13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft14(&self) -> FT14_R { FT14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft15(&self) -> FT15_R { FT15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft16(&self) -> FT16_R { FT16_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft17(&self) -> FT17_R { FT17_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn ft18(&self) -> FT18_R { FT18_R::new(((self.bits >> 18) & 1) != 0) } } impl W { #[doc = "Bit 0 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft0(&mut self) -> FT0_W<0> { FT0_W::new(self) } #[doc = "Bit 1 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft1(&mut self) -> FT1_W<1> { FT1_W::new(self) } #[doc = "Bit 2 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft2(&mut self) -> FT2_W<2> { FT2_W::new(self) } #[doc = "Bit 3 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft3(&mut self) -> FT3_W<3> { FT3_W::new(self) } #[doc = "Bit 4 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft4(&mut self) -> FT4_W<4> { FT4_W::new(self) } #[doc = "Bit 5 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft5(&mut self) -> FT5_W<5> { FT5_W::new(self) } #[doc = "Bit 6 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft6(&mut self) -> FT6_W<6> { FT6_W::new(self) } #[doc = "Bit 7 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft7(&mut self) -> FT7_W<7> { FT7_W::new(self) } #[doc = "Bit 8 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft8(&mut self) -> FT8_W<8> { FT8_W::new(self) } #[doc = "Bit 9 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft9(&mut self) -> FT9_W<9> { FT9_W::new(self) } #[doc = "Bit 10 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft10(&mut self) -> FT10_W<10> { FT10_W::new(self) } #[doc = "Bit 11 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft11(&mut self) -> FT11_W<11> { FT11_W::new(self) } #[doc = "Bit 12 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft12(&mut self) -> FT12_W<12> { FT12_W::new(self) } #[doc = "Bit 13 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft13(&mut self) -> FT13_W<13> { FT13_W::new(self) } #[doc = "Bit 14 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft14(&mut self) -> FT14_W<14> { FT14_W::new(self) } #[doc = "Bit 15 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft15(&mut self) -> FT15_W<15> { FT15_W::new(self) } #[doc = "Bit 16 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft16(&mut self) -> FT16_W<16> { FT16_W::new(self) } #[doc = "Bit 17 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft17(&mut self) -> FT17_W<17> { FT17_W::new(self) } #[doc = "Bit 18 - Falling trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn ft18(&mut self) -> FT18_W<18> { FT18_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI falling trigger selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ftsr](index.html) module"] pub struct FTSR_SPEC; impl crate::RegisterSpec for FTSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ftsr::R](R) reader structure"] impl crate::Readable for FTSR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ftsr::W](W) writer structure"] impl crate::Writable for FTSR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets FTSR to value 0"] impl crate::Resettable for FTSR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SWIER (rw) register accessor: an alias for `Reg`"] pub type SWIER = crate::Reg; #[doc = "EXTI software interrupt event register"] pub mod swier { #[doc = "Register `SWIER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SWIER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SWI0` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI1` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI2` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI3` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI4` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI5` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI6` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI7` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI8` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI8_R = crate::BitReader; #[doc = "Field `SWI8` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI8_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI9` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI9_R = crate::BitReader; #[doc = "Field `SWI9` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI9_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI10` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI10_R = crate::BitReader; #[doc = "Field `SWI10` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI10_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI11` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI11_R = crate::BitReader; #[doc = "Field `SWI11` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI11_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI12` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI12_R = crate::BitReader; #[doc = "Field `SWI12` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI12_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI13` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI13_R = crate::BitReader; #[doc = "Field `SWI13` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI13_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI14` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI14_R = crate::BitReader; #[doc = "Field `SWI14` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI14_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI15` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI15_R = crate::BitReader; #[doc = "Field `SWI15` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI15_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI16` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI16_R = crate::BitReader; #[doc = "Field `SWI16` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI16_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI17` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI17_R = crate::BitReader; #[doc = "Field `SWI17` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI17_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; #[doc = "Field `SWI18` reader - Rising trigger event configuration bit of Configurable Event input"] pub type SWI18_R = crate::BitReader; #[doc = "Field `SWI18` writer - Rising trigger event configuration bit of Configurable Event input"] pub type SWI18_W<'a, const O: u8> = crate::BitWriter<'a, SWIER_SPEC, O>; impl R { #[doc = "Bit 0 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi0(&self) -> SWI0_R { SWI0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi1(&self) -> SWI1_R { SWI1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi2(&self) -> SWI2_R { SWI2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi3(&self) -> SWI3_R { SWI3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi4(&self) -> SWI4_R { SWI4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi5(&self) -> SWI5_R { SWI5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi6(&self) -> SWI6_R { SWI6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi7(&self) -> SWI7_R { SWI7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi8(&self) -> SWI8_R { SWI8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi9(&self) -> SWI9_R { SWI9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi10(&self) -> SWI10_R { SWI10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi11(&self) -> SWI11_R { SWI11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi12(&self) -> SWI12_R { SWI12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi13(&self) -> SWI13_R { SWI13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi14(&self) -> SWI14_R { SWI14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi15(&self) -> SWI15_R { SWI15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi16(&self) -> SWI16_R { SWI16_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi17(&self) -> SWI17_R { SWI17_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] pub fn swi18(&self) -> SWI18_R { SWI18_R::new(((self.bits >> 18) & 1) != 0) } } impl W { #[doc = "Bit 0 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi0(&mut self) -> SWI0_W<0> { SWI0_W::new(self) } #[doc = "Bit 1 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi1(&mut self) -> SWI1_W<1> { SWI1_W::new(self) } #[doc = "Bit 2 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi2(&mut self) -> SWI2_W<2> { SWI2_W::new(self) } #[doc = "Bit 3 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi3(&mut self) -> SWI3_W<3> { SWI3_W::new(self) } #[doc = "Bit 4 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi4(&mut self) -> SWI4_W<4> { SWI4_W::new(self) } #[doc = "Bit 5 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi5(&mut self) -> SWI5_W<5> { SWI5_W::new(self) } #[doc = "Bit 6 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi6(&mut self) -> SWI6_W<6> { SWI6_W::new(self) } #[doc = "Bit 7 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi7(&mut self) -> SWI7_W<7> { SWI7_W::new(self) } #[doc = "Bit 8 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi8(&mut self) -> SWI8_W<8> { SWI8_W::new(self) } #[doc = "Bit 9 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi9(&mut self) -> SWI9_W<9> { SWI9_W::new(self) } #[doc = "Bit 10 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi10(&mut self) -> SWI10_W<10> { SWI10_W::new(self) } #[doc = "Bit 11 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi11(&mut self) -> SWI11_W<11> { SWI11_W::new(self) } #[doc = "Bit 12 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi12(&mut self) -> SWI12_W<12> { SWI12_W::new(self) } #[doc = "Bit 13 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi13(&mut self) -> SWI13_W<13> { SWI13_W::new(self) } #[doc = "Bit 14 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi14(&mut self) -> SWI14_W<14> { SWI14_W::new(self) } #[doc = "Bit 15 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi15(&mut self) -> SWI15_W<15> { SWI15_W::new(self) } #[doc = "Bit 16 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi16(&mut self) -> SWI16_W<16> { SWI16_W::new(self) } #[doc = "Bit 17 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi17(&mut self) -> SWI17_W<17> { SWI17_W::new(self) } #[doc = "Bit 18 - Rising trigger event configuration bit of Configurable Event input"] #[inline(always)] #[must_use] pub fn swi18(&mut self) -> SWI18_W<18> { SWI18_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI software interrupt event register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swier](index.html) module"] pub struct SWIER_SPEC; impl crate::RegisterSpec for SWIER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [swier::R](R) reader structure"] impl crate::Readable for SWIER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [swier::W](W) writer structure"] impl crate::Writable for SWIER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SWIER to value 0"] impl crate::Resettable for SWIER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PR (rw) register accessor: an alias for `Reg`"] pub type PR = crate::Reg; #[doc = "EXTI pending register"] pub mod pr { #[doc = "Register `PR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PR0` reader - configurable event inputs x rising edge Pending bit."] pub type PR0_R = crate::BitReader; #[doc = "Field `PR0` writer - configurable event inputs x rising edge Pending bit."] pub type PR0_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR1` reader - configurable event inputs x rising edge Pending bit."] pub type PR1_R = crate::BitReader; #[doc = "Field `PR1` writer - configurable event inputs x rising edge Pending bit."] pub type PR1_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR2` reader - configurable event inputs x rising edge Pending bit."] pub type PR2_R = crate::BitReader; #[doc = "Field `PR2` writer - configurable event inputs x rising edge Pending bit."] pub type PR2_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR3` reader - configurable event inputs x rising edge Pending bit."] pub type PR3_R = crate::BitReader; #[doc = "Field `PR3` writer - configurable event inputs x rising edge Pending bit."] pub type PR3_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR4` reader - configurable event inputs x rising edge Pending bit."] pub type PR4_R = crate::BitReader; #[doc = "Field `PR4` writer - configurable event inputs x rising edge Pending bit."] pub type PR4_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR5` reader - configurable event inputs x rising edge Pending bit."] pub type PR5_R = crate::BitReader; #[doc = "Field `PR5` writer - configurable event inputs x rising edge Pending bit."] pub type PR5_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR6` reader - configurable event inputs x rising edge Pending bit."] pub type PR6_R = crate::BitReader; #[doc = "Field `PR6` writer - configurable event inputs x rising edge Pending bit."] pub type PR6_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR7` reader - configurable event inputs x rising edge Pending bit."] pub type PR7_R = crate::BitReader; #[doc = "Field `PR7` writer - configurable event inputs x rising edge Pending bit."] pub type PR7_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR8` reader - configurable event inputs x rising edge Pending bit."] pub type PR8_R = crate::BitReader; #[doc = "Field `PR8` writer - configurable event inputs x rising edge Pending bit."] pub type PR8_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR9` reader - configurable event inputs x rising edge Pending bit."] pub type PR9_R = crate::BitReader; #[doc = "Field `PR9` writer - configurable event inputs x rising edge Pending bit."] pub type PR9_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR10` reader - configurable event inputs x rising edge Pending bit."] pub type PR10_R = crate::BitReader; #[doc = "Field `PR10` writer - configurable event inputs x rising edge Pending bit."] pub type PR10_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR11` reader - configurable event inputs x rising edge Pending bit."] pub type PR11_R = crate::BitReader; #[doc = "Field `PR11` writer - configurable event inputs x rising edge Pending bit."] pub type PR11_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR12` reader - configurable event inputs x rising edge Pending bit."] pub type PR12_R = crate::BitReader; #[doc = "Field `PR12` writer - configurable event inputs x rising edge Pending bit."] pub type PR12_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR13` reader - configurable event inputs x rising edge Pending bit"] pub type PR13_R = crate::BitReader; #[doc = "Field `PR13` writer - configurable event inputs x rising edge Pending bit"] pub type PR13_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR14` reader - configurable event inputs x rising edge Pending bit."] pub type PR14_R = crate::BitReader; #[doc = "Field `PR14` writer - configurable event inputs x rising edge Pending bit."] pub type PR14_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR15` reader - configurable event inputs x rising edge Pending bit."] pub type PR15_R = crate::BitReader; #[doc = "Field `PR15` writer - configurable event inputs x rising edge Pending bit."] pub type PR15_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR16` reader - configurable event inputs x rising edge Pending bit."] pub type PR16_R = crate::BitReader; #[doc = "Field `PR16` writer - configurable event inputs x rising edge Pending bit."] pub type PR16_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR17` reader - configurable event inputs x rising edge Pending bit."] pub type PR17_R = crate::BitReader; #[doc = "Field `PR17` writer - configurable event inputs x rising edge Pending bit."] pub type PR17_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; #[doc = "Field `PR18` reader - configurable event inputs x rising edge Pending bit."] pub type PR18_R = crate::BitReader; #[doc = "Field `PR18` writer - configurable event inputs x rising edge Pending bit."] pub type PR18_W<'a, const O: u8> = crate::BitWriter<'a, PR_SPEC, O>; impl R { #[doc = "Bit 0 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr0(&self) -> PR0_R { PR0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr1(&self) -> PR1_R { PR1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr2(&self) -> PR2_R { PR2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr3(&self) -> PR3_R { PR3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr4(&self) -> PR4_R { PR4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr5(&self) -> PR5_R { PR5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr6(&self) -> PR6_R { PR6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr7(&self) -> PR7_R { PR7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr8(&self) -> PR8_R { PR8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr9(&self) -> PR9_R { PR9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr10(&self) -> PR10_R { PR10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr11(&self) -> PR11_R { PR11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr12(&self) -> PR12_R { PR12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - configurable event inputs x rising edge Pending bit"] #[inline(always)] pub fn pr13(&self) -> PR13_R { PR13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr14(&self) -> PR14_R { PR14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr15(&self) -> PR15_R { PR15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr16(&self) -> PR16_R { PR16_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr17(&self) -> PR17_R { PR17_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - configurable event inputs x rising edge Pending bit."] #[inline(always)] pub fn pr18(&self) -> PR18_R { PR18_R::new(((self.bits >> 18) & 1) != 0) } } impl W { #[doc = "Bit 0 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr0(&mut self) -> PR0_W<0> { PR0_W::new(self) } #[doc = "Bit 1 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr1(&mut self) -> PR1_W<1> { PR1_W::new(self) } #[doc = "Bit 2 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr2(&mut self) -> PR2_W<2> { PR2_W::new(self) } #[doc = "Bit 3 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr3(&mut self) -> PR3_W<3> { PR3_W::new(self) } #[doc = "Bit 4 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr4(&mut self) -> PR4_W<4> { PR4_W::new(self) } #[doc = "Bit 5 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr5(&mut self) -> PR5_W<5> { PR5_W::new(self) } #[doc = "Bit 6 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr6(&mut self) -> PR6_W<6> { PR6_W::new(self) } #[doc = "Bit 7 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr7(&mut self) -> PR7_W<7> { PR7_W::new(self) } #[doc = "Bit 8 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr8(&mut self) -> PR8_W<8> { PR8_W::new(self) } #[doc = "Bit 9 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr9(&mut self) -> PR9_W<9> { PR9_W::new(self) } #[doc = "Bit 10 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr10(&mut self) -> PR10_W<10> { PR10_W::new(self) } #[doc = "Bit 11 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr11(&mut self) -> PR11_W<11> { PR11_W::new(self) } #[doc = "Bit 12 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr12(&mut self) -> PR12_W<12> { PR12_W::new(self) } #[doc = "Bit 13 - configurable event inputs x rising edge Pending bit"] #[inline(always)] #[must_use] pub fn pr13(&mut self) -> PR13_W<13> { PR13_W::new(self) } #[doc = "Bit 14 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr14(&mut self) -> PR14_W<14> { PR14_W::new(self) } #[doc = "Bit 15 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr15(&mut self) -> PR15_W<15> { PR15_W::new(self) } #[doc = "Bit 16 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr16(&mut self) -> PR16_W<16> { PR16_W::new(self) } #[doc = "Bit 17 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr17(&mut self) -> PR17_W<17> { PR17_W::new(self) } #[doc = "Bit 18 - configurable event inputs x rising edge Pending bit."] #[inline(always)] #[must_use] pub fn pr18(&mut self) -> PR18_W<18> { PR18_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI pending register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](index.html) module"] pub struct PR_SPEC; impl crate::RegisterSpec for PR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pr::R](R) reader structure"] impl crate::Readable for PR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pr::W](W) writer structure"] impl crate::Writable for PR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PR to value 0"] impl crate::Resettable for PR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EXTICR1 (rw) register accessor: an alias for `Reg`"] pub type EXTICR1 = crate::Reg; #[doc = "EXTI external interrupt selection register"] pub mod exticr1 { #[doc = "Register `EXTICR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `EXTICR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EXTI0` reader - GPIO port selection"] pub type EXTI0_R = crate::FieldReader; #[doc = "Field `EXTI0` writer - GPIO port selection"] pub type EXTI0_W<'a, const O: u8> = crate::FieldWriter<'a, EXTICR1_SPEC, 2, O>; #[doc = "Field `EXTI1` reader - GPIO port selection"] pub type EXTI1_R = crate::FieldReader; #[doc = "Field `EXTI1` writer - GPIO port selection"] pub type EXTI1_W<'a, const O: u8> = crate::FieldWriter<'a, EXTICR1_SPEC, 2, O>; #[doc = "Field `EXTI2` reader - GPIO port selection"] pub type EXTI2_R = crate::FieldReader; #[doc = "Field `EXTI2` writer - GPIO port selection"] pub type EXTI2_W<'a, const O: u8> = crate::FieldWriter<'a, EXTICR1_SPEC, 2, O>; #[doc = "Field `EXTI3` reader - GPIO port selection"] pub type EXTI3_R = crate::FieldReader; #[doc = "Field `EXTI3` writer - GPIO port selection"] pub type EXTI3_W<'a, const O: u8> = crate::FieldWriter<'a, EXTICR1_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - GPIO port selection"] #[inline(always)] pub fn exti0(&self) -> EXTI0_R { EXTI0_R::new((self.bits & 3) as u8) } #[doc = "Bits 8:9 - GPIO port selection"] #[inline(always)] pub fn exti1(&self) -> EXTI1_R { EXTI1_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 16:17 - GPIO port selection"] #[inline(always)] pub fn exti2(&self) -> EXTI2_R { EXTI2_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 24:25 - GPIO port selection"] #[inline(always)] pub fn exti3(&self) -> EXTI3_R { EXTI3_R::new(((self.bits >> 24) & 3) as u8) } } impl W { #[doc = "Bits 0:1 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti0(&mut self) -> EXTI0_W<0> { EXTI0_W::new(self) } #[doc = "Bits 8:9 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti1(&mut self) -> EXTI1_W<8> { EXTI1_W::new(self) } #[doc = "Bits 16:17 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti2(&mut self) -> EXTI2_W<16> { EXTI2_W::new(self) } #[doc = "Bits 24:25 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti3(&mut self) -> EXTI3_W<24> { EXTI3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI external interrupt selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr1](index.html) module"] pub struct EXTICR1_SPEC; impl crate::RegisterSpec for EXTICR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [exticr1::R](R) reader structure"] impl crate::Readable for EXTICR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [exticr1::W](W) writer structure"] impl crate::Writable for EXTICR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EXTICR1 to value 0"] impl crate::Resettable for EXTICR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EXTICR2 (rw) register accessor: an alias for `Reg`"] pub type EXTICR2 = crate::Reg; #[doc = "EXTI external interrupt selection register"] pub mod exticr2 { #[doc = "Register `EXTICR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `EXTICR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EXTI4` reader - GPIO port selection"] pub type EXTI4_R = crate::FieldReader; #[doc = "Field `EXTI4` writer - GPIO port selection"] pub type EXTI4_W<'a, const O: u8> = crate::FieldWriter<'a, EXTICR2_SPEC, 2, O>; #[doc = "Field `EXTI5` reader - GPIO port selection"] pub type EXTI5_R = crate::BitReader; #[doc = "Field `EXTI5` writer - GPIO port selection"] pub type EXTI5_W<'a, const O: u8> = crate::BitWriter<'a, EXTICR2_SPEC, O>; #[doc = "Field `EXTI6` reader - GPIO port selection"] pub type EXTI6_R = crate::BitReader; #[doc = "Field `EXTI6` writer - GPIO port selection"] pub type EXTI6_W<'a, const O: u8> = crate::BitWriter<'a, EXTICR2_SPEC, O>; #[doc = "Field `EXTI7` reader - GPIO port selection"] pub type EXTI7_R = crate::BitReader; #[doc = "Field `EXTI7` writer - GPIO port selection"] pub type EXTI7_W<'a, const O: u8> = crate::BitWriter<'a, EXTICR2_SPEC, O>; impl R { #[doc = "Bits 0:1 - GPIO port selection"] #[inline(always)] pub fn exti4(&self) -> EXTI4_R { EXTI4_R::new((self.bits & 3) as u8) } #[doc = "Bit 8 - GPIO port selection"] #[inline(always)] pub fn exti5(&self) -> EXTI5_R { EXTI5_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 16 - GPIO port selection"] #[inline(always)] pub fn exti6(&self) -> EXTI6_R { EXTI6_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 24 - GPIO port selection"] #[inline(always)] pub fn exti7(&self) -> EXTI7_R { EXTI7_R::new(((self.bits >> 24) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti4(&mut self) -> EXTI4_W<0> { EXTI4_W::new(self) } #[doc = "Bit 8 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti5(&mut self) -> EXTI5_W<8> { EXTI5_W::new(self) } #[doc = "Bit 16 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti6(&mut self) -> EXTI6_W<16> { EXTI6_W::new(self) } #[doc = "Bit 24 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti7(&mut self) -> EXTI7_W<24> { EXTI7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI external interrupt selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr2](index.html) module"] pub struct EXTICR2_SPEC; impl crate::RegisterSpec for EXTICR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [exticr2::R](R) reader structure"] impl crate::Readable for EXTICR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [exticr2::W](W) writer structure"] impl crate::Writable for EXTICR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EXTICR2 to value 0"] impl crate::Resettable for EXTICR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EXTICR3 (rw) register accessor: an alias for `Reg`"] pub type EXTICR3 = crate::Reg; #[doc = "EXTI external interrupt selection register"] pub mod exticr3 { #[doc = "Register `EXTICR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `EXTICR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EXTI8` reader - GPIO port selection"] pub type EXTI8_R = crate::BitReader; #[doc = "Field `EXTI8` writer - GPIO port selection"] pub type EXTI8_W<'a, const O: u8> = crate::BitWriter<'a, EXTICR3_SPEC, O>; impl R { #[doc = "Bit 0 - GPIO port selection"] #[inline(always)] pub fn exti8(&self) -> EXTI8_R { EXTI8_R::new((self.bits & 1) != 0) } } impl W { #[doc = "Bit 0 - GPIO port selection"] #[inline(always)] #[must_use] pub fn exti8(&mut self) -> EXTI8_W<0> { EXTI8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI external interrupt selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr3](index.html) module"] pub struct EXTICR3_SPEC; impl crate::RegisterSpec for EXTICR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [exticr3::R](R) reader structure"] impl crate::Readable for EXTICR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [exticr3::W](W) writer structure"] impl crate::Writable for EXTICR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EXTICR3 to value 0"] impl crate::Resettable for EXTICR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IMR (rw) register accessor: an alias for `Reg`"] pub type IMR = crate::Reg; #[doc = "EXTI CPU wakeup with interrupt mask register"] pub mod imr { #[doc = "Register `IMR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IMR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `IM0` reader - CPU wakeup with interrupt mask on event input"] pub type IM0_R = crate::BitReader; #[doc = "Field `IM0` writer - CPU wakeup with interrupt mask on event input"] pub type IM0_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM1` reader - CPU wakeup with interrupt mask on event input"] pub type IM1_R = crate::BitReader; #[doc = "Field `IM1` writer - CPU wakeup with interrupt mask on event input"] pub type IM1_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM2` reader - CPU wakeup with interrupt mask on event input"] pub type IM2_R = crate::BitReader; #[doc = "Field `IM2` writer - CPU wakeup with interrupt mask on event input"] pub type IM2_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM3` reader - CPU wakeup with interrupt mask on event input"] pub type IM3_R = crate::BitReader; #[doc = "Field `IM3` writer - CPU wakeup with interrupt mask on event input"] pub type IM3_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM4` reader - CPU wakeup with interrupt mask on event input"] pub type IM4_R = crate::BitReader; #[doc = "Field `IM4` writer - CPU wakeup with interrupt mask on event input"] pub type IM4_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM5` reader - CPU wakeup with interrupt mask on event input"] pub type IM5_R = crate::BitReader; #[doc = "Field `IM5` writer - CPU wakeup with interrupt mask on event input"] pub type IM5_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM6` reader - CPU wakeup with interrupt mask on event input"] pub type IM6_R = crate::BitReader; #[doc = "Field `IM6` writer - CPU wakeup with interrupt mask on event input"] pub type IM6_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM7` reader - CPU wakeup with interrupt mask on event input"] pub type IM7_R = crate::BitReader; #[doc = "Field `IM7` writer - CPU wakeup with interrupt mask on event input"] pub type IM7_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM8` reader - CPU wakeup with interrupt mask on event input"] pub type IM8_R = crate::BitReader; #[doc = "Field `IM8` writer - CPU wakeup with interrupt mask on event input"] pub type IM8_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM9` reader - CPU wakeup with interrupt mask on event input"] pub type IM9_R = crate::BitReader; #[doc = "Field `IM9` writer - CPU wakeup with interrupt mask on event input"] pub type IM9_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM10` reader - CPU wakeup with interrupt mask on event input"] pub type IM10_R = crate::BitReader; #[doc = "Field `IM10` writer - CPU wakeup with interrupt mask on event input"] pub type IM10_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM11` reader - CPU wakeup with interrupt mask on event input"] pub type IM11_R = crate::BitReader; #[doc = "Field `IM11` writer - CPU wakeup with interrupt mask on event input"] pub type IM11_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM12` reader - CPU wakeup with interrupt mask on event input"] pub type IM12_R = crate::BitReader; #[doc = "Field `IM12` writer - CPU wakeup with interrupt mask on event input"] pub type IM12_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM13` reader - CPU wakeup with interrupt mask on event input"] pub type IM13_R = crate::BitReader; #[doc = "Field `IM13` writer - CPU wakeup with interrupt mask on event input"] pub type IM13_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM14` reader - CPU wakeup with interrupt mask on event input"] pub type IM14_R = crate::BitReader; #[doc = "Field `IM14` writer - CPU wakeup with interrupt mask on event input"] pub type IM14_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM15` reader - CPU wakeup with interrupt mask on event input"] pub type IM15_R = crate::BitReader; #[doc = "Field `IM15` writer - CPU wakeup with interrupt mask on event input"] pub type IM15_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM16` reader - CPU wakeup with interrupt mask on event input"] pub type IM16_R = crate::BitReader; #[doc = "Field `IM16` writer - CPU wakeup with interrupt mask on event input"] pub type IM16_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM17` reader - CPU wakeup with interrupt mask on event input"] pub type IM17_R = crate::BitReader; #[doc = "Field `IM17` writer - CPU wakeup with interrupt mask on event input"] pub type IM17_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM18` reader - CPU wakeup with interrupt mask on event input"] pub type IM18_R = crate::BitReader; #[doc = "Field `IM18` writer - CPU wakeup with interrupt mask on event input"] pub type IM18_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM19` reader - CPU wakeup with interrupt mask on event input"] pub type IM19_R = crate::BitReader; #[doc = "Field `IM19` writer - CPU wakeup with interrupt mask on event input"] pub type IM19_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; #[doc = "Field `IM29` reader - CPU wakeup with interrupt mask on event input"] pub type IM29_R = crate::BitReader; #[doc = "Field `IM29` writer - CPU wakeup with interrupt mask on event input"] pub type IM29_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; impl R { #[doc = "Bit 0 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im0(&self) -> IM0_R { IM0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im1(&self) -> IM1_R { IM1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im2(&self) -> IM2_R { IM2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im3(&self) -> IM3_R { IM3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im4(&self) -> IM4_R { IM4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im5(&self) -> IM5_R { IM5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im6(&self) -> IM6_R { IM6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im7(&self) -> IM7_R { IM7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im8(&self) -> IM8_R { IM8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im9(&self) -> IM9_R { IM9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im10(&self) -> IM10_R { IM10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im11(&self) -> IM11_R { IM11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im12(&self) -> IM12_R { IM12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im13(&self) -> IM13_R { IM13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im14(&self) -> IM14_R { IM14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im15(&self) -> IM15_R { IM15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im16(&self) -> IM16_R { IM16_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im17(&self) -> IM17_R { IM17_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im18(&self) -> IM18_R { IM18_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im19(&self) -> IM19_R { IM19_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 29 - CPU wakeup with interrupt mask on event input"] #[inline(always)] pub fn im29(&self) -> IM29_R { IM29_R::new(((self.bits >> 29) & 1) != 0) } } impl W { #[doc = "Bit 0 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im0(&mut self) -> IM0_W<0> { IM0_W::new(self) } #[doc = "Bit 1 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im1(&mut self) -> IM1_W<1> { IM1_W::new(self) } #[doc = "Bit 2 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im2(&mut self) -> IM2_W<2> { IM2_W::new(self) } #[doc = "Bit 3 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im3(&mut self) -> IM3_W<3> { IM3_W::new(self) } #[doc = "Bit 4 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im4(&mut self) -> IM4_W<4> { IM4_W::new(self) } #[doc = "Bit 5 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im5(&mut self) -> IM5_W<5> { IM5_W::new(self) } #[doc = "Bit 6 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im6(&mut self) -> IM6_W<6> { IM6_W::new(self) } #[doc = "Bit 7 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im7(&mut self) -> IM7_W<7> { IM7_W::new(self) } #[doc = "Bit 8 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im8(&mut self) -> IM8_W<8> { IM8_W::new(self) } #[doc = "Bit 9 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im9(&mut self) -> IM9_W<9> { IM9_W::new(self) } #[doc = "Bit 10 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im10(&mut self) -> IM10_W<10> { IM10_W::new(self) } #[doc = "Bit 11 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im11(&mut self) -> IM11_W<11> { IM11_W::new(self) } #[doc = "Bit 12 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im12(&mut self) -> IM12_W<12> { IM12_W::new(self) } #[doc = "Bit 13 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im13(&mut self) -> IM13_W<13> { IM13_W::new(self) } #[doc = "Bit 14 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im14(&mut self) -> IM14_W<14> { IM14_W::new(self) } #[doc = "Bit 15 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im15(&mut self) -> IM15_W<15> { IM15_W::new(self) } #[doc = "Bit 16 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im16(&mut self) -> IM16_W<16> { IM16_W::new(self) } #[doc = "Bit 17 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im17(&mut self) -> IM17_W<17> { IM17_W::new(self) } #[doc = "Bit 18 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im18(&mut self) -> IM18_W<18> { IM18_W::new(self) } #[doc = "Bit 19 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im19(&mut self) -> IM19_W<19> { IM19_W::new(self) } #[doc = "Bit 29 - CPU wakeup with interrupt mask on event input"] #[inline(always)] #[must_use] pub fn im29(&mut self) -> IM29_W<29> { IM29_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI CPU wakeup with interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [imr::R](R) reader structure"] impl crate::Readable for IMR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [imr::W](W) writer structure"] impl crate::Writable for IMR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IMR to value 0xfff8_0000"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0xfff8_0000; } } #[doc = "EMR (rw) register accessor: an alias for `Reg`"] pub type EMR = crate::Reg; #[doc = "EXTI CPU wakeup with event mask register"] pub mod emr { #[doc = "Register `EMR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `EMR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EM0` reader - CPU wakeup with event mask on event input"] pub type EM0_R = crate::BitReader; #[doc = "Field `EM0` writer - CPU wakeup with event mask on event input"] pub type EM0_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM1` reader - CPU wakeup with event mask on event input"] pub type EM1_R = crate::BitReader; #[doc = "Field `EM1` writer - CPU wakeup with event mask on event input"] pub type EM1_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM2` reader - CPU wakeup with event mask on event input"] pub type EM2_R = crate::BitReader; #[doc = "Field `EM2` writer - CPU wakeup with event mask on event input"] pub type EM2_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM3` reader - CPU wakeup with event mask on event input"] pub type EM3_R = crate::BitReader; #[doc = "Field `EM3` writer - CPU wakeup with event mask on event input"] pub type EM3_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM4` reader - CPU wakeup with event mask on event input"] pub type EM4_R = crate::BitReader; #[doc = "Field `EM4` writer - CPU wakeup with event mask on event input"] pub type EM4_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM5` reader - CPU wakeup with event mask on event input"] pub type EM5_R = crate::BitReader; #[doc = "Field `EM5` writer - CPU wakeup with event mask on event input"] pub type EM5_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM6` reader - CPU wakeup with event mask on event input"] pub type EM6_R = crate::BitReader; #[doc = "Field `EM6` writer - CPU wakeup with event mask on event input"] pub type EM6_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM7` reader - CPU wakeup with event mask on event input"] pub type EM7_R = crate::BitReader; #[doc = "Field `EM7` writer - CPU wakeup with event mask on event input"] pub type EM7_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM8` reader - CPU wakeup with event mask on event input"] pub type EM8_R = crate::BitReader; #[doc = "Field `EM8` writer - CPU wakeup with event mask on event input"] pub type EM8_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM9` reader - CPU wakeup with event mask on event input"] pub type EM9_R = crate::BitReader; #[doc = "Field `EM9` writer - CPU wakeup with event mask on event input"] pub type EM9_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM10` reader - CPU wakeup with event mask on event input"] pub type EM10_R = crate::BitReader; #[doc = "Field `EM10` writer - CPU wakeup with event mask on event input"] pub type EM10_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM11` reader - CPU wakeup with event mask on event input"] pub type EM11_R = crate::BitReader; #[doc = "Field `EM11` writer - CPU wakeup with event mask on event input"] pub type EM11_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM12` reader - CPU wakeup with event mask on event input"] pub type EM12_R = crate::BitReader; #[doc = "Field `EM12` writer - CPU wakeup with event mask on event input"] pub type EM12_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM13` reader - CPU wakeup with event mask on event input"] pub type EM13_R = crate::BitReader; #[doc = "Field `EM13` writer - CPU wakeup with event mask on event input"] pub type EM13_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM14` reader - CPU wakeup with event mask on event input"] pub type EM14_R = crate::BitReader; #[doc = "Field `EM14` writer - CPU wakeup with event mask on event input"] pub type EM14_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM15` reader - CPU wakeup with event mask on event input"] pub type EM15_R = crate::BitReader; #[doc = "Field `EM15` writer - CPU wakeup with event mask on event input"] pub type EM15_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM16` reader - CPU wakeup with event mask on event input"] pub type EM16_R = crate::BitReader; #[doc = "Field `EM16` writer - CPU wakeup with event mask on event input"] pub type EM16_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM17` reader - CPU wakeup with event mask on event input"] pub type EM17_R = crate::BitReader; #[doc = "Field `EM17` writer - CPU wakeup with event mask on event input"] pub type EM17_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM18` reader - CPU wakeup with event mask on event input"] pub type EM18_R = crate::BitReader; #[doc = "Field `EM18` writer - CPU wakeup with event mask on event input"] pub type EM18_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM19` reader - CPU wakeup with event mask on event input"] pub type EM19_R = crate::BitReader; #[doc = "Field `EM19` writer - CPU wakeup with event mask on event input"] pub type EM19_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; #[doc = "Field `EM29` reader - CPU wakeup with event mask on event input"] pub type EM29_R = crate::BitReader; #[doc = "Field `EM29` writer - CPU wakeup with event mask on event input"] pub type EM29_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; impl R { #[doc = "Bit 0 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em0(&self) -> EM0_R { EM0_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em1(&self) -> EM1_R { EM1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em2(&self) -> EM2_R { EM2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em3(&self) -> EM3_R { EM3_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em4(&self) -> EM4_R { EM4_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em5(&self) -> EM5_R { EM5_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em6(&self) -> EM6_R { EM6_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em7(&self) -> EM7_R { EM7_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em8(&self) -> EM8_R { EM8_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em9(&self) -> EM9_R { EM9_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em10(&self) -> EM10_R { EM10_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em11(&self) -> EM11_R { EM11_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em12(&self) -> EM12_R { EM12_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em13(&self) -> EM13_R { EM13_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em14(&self) -> EM14_R { EM14_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em15(&self) -> EM15_R { EM15_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em16(&self) -> EM16_R { EM16_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em17(&self) -> EM17_R { EM17_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em18(&self) -> EM18_R { EM18_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em19(&self) -> EM19_R { EM19_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 29 - CPU wakeup with event mask on event input"] #[inline(always)] pub fn em29(&self) -> EM29_R { EM29_R::new(((self.bits >> 29) & 1) != 0) } } impl W { #[doc = "Bit 0 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em0(&mut self) -> EM0_W<0> { EM0_W::new(self) } #[doc = "Bit 1 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em1(&mut self) -> EM1_W<1> { EM1_W::new(self) } #[doc = "Bit 2 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em2(&mut self) -> EM2_W<2> { EM2_W::new(self) } #[doc = "Bit 3 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em3(&mut self) -> EM3_W<3> { EM3_W::new(self) } #[doc = "Bit 4 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em4(&mut self) -> EM4_W<4> { EM4_W::new(self) } #[doc = "Bit 5 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em5(&mut self) -> EM5_W<5> { EM5_W::new(self) } #[doc = "Bit 6 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em6(&mut self) -> EM6_W<6> { EM6_W::new(self) } #[doc = "Bit 7 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em7(&mut self) -> EM7_W<7> { EM7_W::new(self) } #[doc = "Bit 8 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em8(&mut self) -> EM8_W<8> { EM8_W::new(self) } #[doc = "Bit 9 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em9(&mut self) -> EM9_W<9> { EM9_W::new(self) } #[doc = "Bit 10 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em10(&mut self) -> EM10_W<10> { EM10_W::new(self) } #[doc = "Bit 11 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em11(&mut self) -> EM11_W<11> { EM11_W::new(self) } #[doc = "Bit 12 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em12(&mut self) -> EM12_W<12> { EM12_W::new(self) } #[doc = "Bit 13 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em13(&mut self) -> EM13_W<13> { EM13_W::new(self) } #[doc = "Bit 14 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em14(&mut self) -> EM14_W<14> { EM14_W::new(self) } #[doc = "Bit 15 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em15(&mut self) -> EM15_W<15> { EM15_W::new(self) } #[doc = "Bit 16 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em16(&mut self) -> EM16_W<16> { EM16_W::new(self) } #[doc = "Bit 17 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em17(&mut self) -> EM17_W<17> { EM17_W::new(self) } #[doc = "Bit 18 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em18(&mut self) -> EM18_W<18> { EM18_W::new(self) } #[doc = "Bit 19 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em19(&mut self) -> EM19_W<19> { EM19_W::new(self) } #[doc = "Bit 29 - CPU wakeup with event mask on event input"] #[inline(always)] #[must_use] pub fn em29(&mut self) -> EM29_W<29> { EM29_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "EXTI CPU wakeup with event mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emr](index.html) module"] pub struct EMR_SPEC; impl crate::RegisterSpec for EMR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [emr::R](R) reader structure"] impl crate::Readable for EMR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [emr::W](W) writer structure"] impl crate::Writable for EMR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EMR to value 0"] impl crate::Resettable for EMR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Low power timer"] pub struct LPTIM { _marker: PhantomData<*const ()>, } unsafe impl Send for LPTIM {} impl LPTIM { #[doc = r"Pointer to the register block"] pub const PTR: *const lptim::RegisterBlock = 0x4000_7c00 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const lptim::RegisterBlock { Self::PTR } } impl Deref for LPTIM { type Target = lptim::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for LPTIM { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("LPTIM").finish() } } #[doc = "Low power timer"] pub mod lptim { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Interrupt and Status Register"] pub isr: ISR, #[doc = "0x04 - Interrupt Clear Register"] pub icr: ICR, #[doc = "0x08 - Interrupt Enable Register"] pub ier: IER, #[doc = "0x0c - Configuration Register"] pub cfgr: CFGR, #[doc = "0x10 - Control Register"] pub cr: CR, _reserved5: [u8; 0x04], #[doc = "0x18 - Autoreload Register"] pub arr: ARR, #[doc = "0x1c - Counter Register"] pub cnt: CNT, } #[doc = "ISR (r) register accessor: an alias for `Reg`"] pub type ISR = crate::Reg; #[doc = "Interrupt and Status Register"] pub mod isr { #[doc = "Register `ISR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `ARRM` reader - Autoreload match"] pub type ARRM_R = crate::BitReader; impl R { #[doc = "Bit 1 - Autoreload match"] #[inline(always)] pub fn arrm(&self) -> ARRM_R { ARRM_R::new(((self.bits >> 1) & 1) != 0) } } #[doc = "Interrupt and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [isr::R](R) reader structure"] impl crate::Readable for ISR_SPEC { type Reader = R; } #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ICR (w) register accessor: an alias for `Reg`"] pub type ICR = crate::Reg; #[doc = "Interrupt Clear Register"] pub mod icr { #[doc = "Register `ICR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARRMCF` writer - Autoreload match Clear Flag"] pub type ARRMCF_W<'a, const O: u8> = crate::BitWriter<'a, ICR_SPEC, O>; impl W { #[doc = "Bit 1 - Autoreload match Clear Flag"] #[inline(always)] #[must_use] pub fn arrmcf(&mut self) -> ARRMCF_W<1> { ARRMCF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] impl crate::Writable for ICR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ICR to value 0"] impl crate::Resettable for ICR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IER (rw) register accessor: an alias for `Reg`"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier { #[doc = "Register `IER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARRMIE` reader - Autoreload match Interrupt Enable"] pub type ARRMIE_R = crate::BitReader; #[doc = "Field `ARRMIE` writer - Autoreload match Interrupt Enable"] pub type ARRMIE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; impl R { #[doc = "Bit 1 - Autoreload match Interrupt Enable"] #[inline(always)] pub fn arrmie(&self) -> ARRMIE_R { ARRMIE_R::new(((self.bits >> 1) & 1) != 0) } } impl W { #[doc = "Bit 1 - Autoreload match Interrupt Enable"] #[inline(always)] #[must_use] pub fn arrmie(&mut self) -> ARRMIE_W<1> { ARRMIE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ier::R](R) reader structure"] impl crate::Readable for IER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] impl crate::Writable for IER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IER to value 0"] impl crate::Resettable for IER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CFGR (rw) register accessor: an alias for `Reg`"] pub type CFGR = crate::Reg; #[doc = "Configuration Register"] pub mod cfgr { #[doc = "Register `CFGR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PRESC` reader - Clock prescaler"] pub type PRESC_R = crate::FieldReader; #[doc = "Field `PRESC` writer - Clock prescaler"] pub type PRESC_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR_SPEC, 3, O>; #[doc = "Field `PRELOAD` reader - Registers update mode"] pub type PRELOAD_R = crate::BitReader; #[doc = "Field `PRELOAD` writer - Registers update mode"] pub type PRELOAD_W<'a, const O: u8> = crate::BitWriter<'a, CFGR_SPEC, O>; impl R { #[doc = "Bits 9:11 - Clock prescaler"] #[inline(always)] pub fn presc(&self) -> PRESC_R { PRESC_R::new(((self.bits >> 9) & 7) as u8) } #[doc = "Bit 22 - Registers update mode"] #[inline(always)] pub fn preload(&self) -> PRELOAD_R { PRELOAD_R::new(((self.bits >> 22) & 1) != 0) } } impl W { #[doc = "Bits 9:11 - Clock prescaler"] #[inline(always)] #[must_use] pub fn presc(&mut self) -> PRESC_W<9> { PRESC_W::new(self) } #[doc = "Bit 22 - Registers update mode"] #[inline(always)] #[must_use] pub fn preload(&mut self) -> PRELOAD_W<22> { PRELOAD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"] pub struct CFGR_SPEC; impl crate::RegisterSpec for CFGR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr::R](R) reader structure"] impl crate::Readable for CFGR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"] impl crate::Writable for CFGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR to value 0"] impl crate::Resettable for CFGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ENABLE` reader - LPTIM Enable"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - LPTIM Enable"] pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `SNGSTRT` reader - LPTIM start in single mode"] pub type SNGSTRT_R = crate::BitReader; #[doc = "Field `SNGSTRT` writer - LPTIM start in single mode"] pub type SNGSTRT_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `RSTARE` reader - Reset after read enable"] pub type RSTARE_R = crate::BitReader; #[doc = "Field `RSTARE` writer - Reset after read enable"] pub type RSTARE_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl R { #[doc = "Bit 0 - LPTIM Enable"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - LPTIM start in single mode"] #[inline(always)] pub fn sngstrt(&self) -> SNGSTRT_R { SNGSTRT_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 4 - Reset after read enable"] #[inline(always)] pub fn rstare(&self) -> RSTARE_R { RSTARE_R::new(((self.bits >> 4) & 1) != 0) } } impl W { #[doc = "Bit 0 - LPTIM Enable"] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W<0> { ENABLE_W::new(self) } #[doc = "Bit 1 - LPTIM start in single mode"] #[inline(always)] #[must_use] pub fn sngstrt(&mut self) -> SNGSTRT_W<1> { SNGSTRT_W::new(self) } #[doc = "Bit 4 - Reset after read enable"] #[inline(always)] #[must_use] pub fn rstare(&mut self) -> RSTARE_W<4> { RSTARE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ARR (rw) register accessor: an alias for `Reg`"] pub type ARR = crate::Reg; #[doc = "Autoreload Register"] pub mod arr { #[doc = "Register `ARR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ARR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARR` reader - Auto reload value"] pub type ARR_R = crate::FieldReader; #[doc = "Field `ARR` writer - Auto reload value"] pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, ARR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Auto reload value"] #[inline(always)] pub fn arr(&self) -> ARR_R { ARR_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Auto reload value"] #[inline(always)] #[must_use] pub fn arr(&mut self) -> ARR_W<0> { ARR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Autoreload Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"] pub struct ARR_SPEC; impl crate::RegisterSpec for ARR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [arr::R](R) reader structure"] impl crate::Readable for ARR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"] impl crate::Writable for ARR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ARR to value 0x01"] impl crate::Resettable for ARR_SPEC { const RESET_VALUE: Self::Ux = 0x01; } } #[doc = "CNT (r) register accessor: an alias for `Reg`"] pub type CNT = crate::Reg; #[doc = "Counter Register"] pub mod cnt { #[doc = "Register `CNT` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `CNT` reader - Counter value"] pub type CNT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Counter value"] #[inline(always)] pub fn cnt(&self) -> CNT_R { CNT_R::new((self.bits & 0xffff) as u16) } } #[doc = "Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"] pub struct CNT_SPEC; impl crate::RegisterSpec for CNT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cnt::R](R) reader structure"] impl crate::Readable for CNT_SPEC { type Reader = R; } #[doc = "`reset()` method sets CNT to value 0"] impl crate::Resettable for CNT_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Universal synchronous asynchronous receiver transmitter"] pub struct USART1 { _marker: PhantomData<*const ()>, } unsafe impl Send for USART1 {} impl USART1 { #[doc = r"Pointer to the register block"] pub const PTR: *const usart1::RegisterBlock = 0x4001_3800 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const usart1::RegisterBlock { Self::PTR } } impl Deref for USART1 { type Target = usart1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for USART1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("USART1").finish() } } #[doc = "Universal synchronous asynchronous receiver transmitter"] pub mod usart1 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Status register"] pub sr: SR, #[doc = "0x04 - Data register"] pub dr: DR, #[doc = "0x08 - Baud rate register"] pub brr: BRR, #[doc = "0x0c - Control register 1"] pub cr1: CR1, #[doc = "0x10 - Control register 2"] pub cr2: CR2, #[doc = "0x14 - Control register 3"] pub cr3: CR3, } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "Status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PE` reader - Parity error"] pub type PE_R = crate::BitReader; #[doc = "Field `FE` reader - Framing error"] pub type FE_R = crate::BitReader; #[doc = "Field `NE` reader - Noise error flag"] pub type NE_R = crate::BitReader; #[doc = "Field `ORE` reader - Overrun error"] pub type ORE_R = crate::BitReader; #[doc = "Field `IDLE` reader - IDLE line detected"] pub type IDLE_R = crate::BitReader; #[doc = "Field `RXNE` reader - Read data register not empty"] pub type RXNE_R = crate::BitReader; #[doc = "Field `RXNE` writer - Read data register not empty"] pub type RXNE_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `TC` reader - Transmission complete"] pub type TC_R = crate::BitReader; #[doc = "Field `TC` writer - Transmission complete"] pub type TC_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `TXE` reader - Transmit data register empty"] pub type TXE_R = crate::BitReader; #[doc = "Field `CTS` reader - CTS flag"] pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS flag"] pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `ABRF` reader - Automate baudrate detection flag"] pub type ABRF_R = crate::BitReader; #[doc = "Field `ABRE` reader - Automate baudrate detection error flag"] pub type ABRE_R = crate::BitReader; #[doc = "Field `ABRRQ` writer - Automate baudrate detection requeset"] pub type ABRRQ_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - Parity error"] #[inline(always)] pub fn pe(&self) -> PE_R { PE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Framing error"] #[inline(always)] pub fn fe(&self) -> FE_R { FE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Noise error flag"] #[inline(always)] pub fn ne(&self) -> NE_R { NE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Overrun error"] #[inline(always)] pub fn ore(&self) -> ORE_R { ORE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - IDLE line detected"] #[inline(always)] pub fn idle(&self) -> IDLE_R { IDLE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Read data register not empty"] #[inline(always)] pub fn rxne(&self) -> RXNE_R { RXNE_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Transmission complete"] #[inline(always)] pub fn tc(&self) -> TC_R { TC_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Transmit data register empty"] #[inline(always)] pub fn txe(&self) -> TXE_R { TXE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 9 - CTS flag"] #[inline(always)] pub fn cts(&self) -> CTS_R { CTS_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Automate baudrate detection flag"] #[inline(always)] pub fn abrf(&self) -> ABRF_R { ABRF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Automate baudrate detection error flag"] #[inline(always)] pub fn abre(&self) -> ABRE_R { ABRE_R::new(((self.bits >> 11) & 1) != 0) } } impl W { #[doc = "Bit 5 - Read data register not empty"] #[inline(always)] #[must_use] pub fn rxne(&mut self) -> RXNE_W<5> { RXNE_W::new(self) } #[doc = "Bit 6 - Transmission complete"] #[inline(always)] #[must_use] pub fn tc(&mut self) -> TC_W<6> { TC_W::new(self) } #[doc = "Bit 9 - CTS flag"] #[inline(always)] #[must_use] pub fn cts(&mut self) -> CTS_W<9> { CTS_W::new(self) } #[doc = "Bit 12 - Automate baudrate detection requeset"] #[inline(always)] #[must_use] pub fn abrrq(&mut self) -> ABRRQ_W<12> { ABRRQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0xc0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0xc0; } } #[doc = "DR (rw) register accessor: an alias for `Reg`"] pub type DR = crate::Reg; #[doc = "Data register"] pub mod dr { #[doc = "Register `DR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DR` reader - Data value"] pub type DR_R = crate::FieldReader; #[doc = "Field `DR` writer - Data value"] pub type DR_W<'a, const O: u8> = crate::FieldWriter<'a, DR_SPEC, 9, O, u16>; impl R { #[doc = "Bits 0:8 - Data value"] #[inline(always)] pub fn dr(&self) -> DR_R { DR_R::new((self.bits & 0x01ff) as u16) } } impl W { #[doc = "Bits 0:8 - Data value"] #[inline(always)] #[must_use] pub fn dr(&mut self) -> DR_W<0> { DR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr::R](R) reader structure"] impl crate::Readable for DR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] impl crate::Writable for DR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR to value 0"] impl crate::Resettable for DR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BRR (rw) register accessor: an alias for `Reg`"] pub type BRR = crate::Reg; #[doc = "Baud rate register"] pub mod brr { #[doc = "Register `BRR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `BRR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DIV_Fraction` reader - fraction of USARTDIV"] pub type DIV_FRACTION_R = crate::FieldReader; #[doc = "Field `DIV_Fraction` writer - fraction of USARTDIV"] pub type DIV_FRACTION_W<'a, const O: u8> = crate::FieldWriter<'a, BRR_SPEC, 4, O>; #[doc = "Field `DIV_Mantissa` reader - mantissa of USARTDIV"] pub type DIV_MANTISSA_R = crate::FieldReader; #[doc = "Field `DIV_Mantissa` writer - mantissa of USARTDIV"] pub type DIV_MANTISSA_W<'a, const O: u8> = crate::FieldWriter<'a, BRR_SPEC, 12, O, u16>; impl R { #[doc = "Bits 0:3 - fraction of USARTDIV"] #[inline(always)] pub fn div_fraction(&self) -> DIV_FRACTION_R { DIV_FRACTION_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:15 - mantissa of USARTDIV"] #[inline(always)] pub fn div_mantissa(&self) -> DIV_MANTISSA_R { DIV_MANTISSA_R::new(((self.bits >> 4) & 0x0fff) as u16) } } impl W { #[doc = "Bits 0:3 - fraction of USARTDIV"] #[inline(always)] #[must_use] pub fn div_fraction(&mut self) -> DIV_FRACTION_W<0> { DIV_FRACTION_W::new(self) } #[doc = "Bits 4:15 - mantissa of USARTDIV"] #[inline(always)] #[must_use] pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<4> { DIV_MANTISSA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Baud rate register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [brr](index.html) module"] pub struct BRR_SPEC; impl crate::RegisterSpec for BRR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [brr::R](R) reader structure"] impl crate::Readable for BRR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [brr::W](W) writer structure"] impl crate::Writable for BRR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BRR to value 0"] impl crate::Resettable for BRR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "Control register 1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SBK` reader - Send break"] pub type SBK_R = crate::BitReader; #[doc = "Field `SBK` writer - Send break"] pub type SBK_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `RWU` reader - Receiver wakeup"] pub type RWU_R = crate::BitReader; #[doc = "Field `RWU` writer - Receiver wakeup"] pub type RWU_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `RE` reader - Receiver enable"] pub type RE_R = crate::BitReader; #[doc = "Field `RE` writer - Receiver enable"] pub type RE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `TE` reader - Transmitter enable"] pub type TE_R = crate::BitReader; #[doc = "Field `TE` writer - Transmitter enable"] pub type TE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `IDLEIE` reader - IDLE interrupt enable"] pub type IDLEIE_R = crate::BitReader; #[doc = "Field `IDLEIE` writer - IDLE interrupt enable"] pub type IDLEIE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `RXNEIE` reader - RXNE interrupt enable"] pub type RXNEIE_R = crate::BitReader; #[doc = "Field `RXNEIE` writer - RXNE interrupt enable"] pub type RXNEIE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `TCIE` reader - Transmission complete interrupt enable"] pub type TCIE_R = crate::BitReader; #[doc = "Field `TCIE` writer - Transmission complete interrupt enable"] pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `TXEIE` reader - TXE interrupt enable"] pub type TXEIE_R = crate::BitReader; #[doc = "Field `TXEIE` writer - TXE interrupt enable"] pub type TXEIE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `PEIE` reader - PE interrupt enable"] pub type PEIE_R = crate::BitReader; #[doc = "Field `PEIE` writer - PE interrupt enable"] pub type PEIE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `PS` reader - Parity selection"] pub type PS_R = crate::BitReader; #[doc = "Field `PS` writer - Parity selection"] pub type PS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `PCE` reader - Parity control enable"] pub type PCE_R = crate::BitReader; #[doc = "Field `PCE` writer - Parity control enable"] pub type PCE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `WAKE` reader - Wakeup method"] pub type WAKE_R = crate::BitReader; #[doc = "Field `WAKE` writer - Wakeup method"] pub type WAKE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `M` reader - Word length"] pub type M_R = crate::BitReader; #[doc = "Field `M` writer - Word length"] pub type M_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `UE` reader - USART enable"] pub type UE_R = crate::BitReader; #[doc = "Field `UE` writer - USART enable"] pub type UE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; impl R { #[doc = "Bit 0 - Send break"] #[inline(always)] pub fn sbk(&self) -> SBK_R { SBK_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Receiver wakeup"] #[inline(always)] pub fn rwu(&self) -> RWU_R { RWU_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Receiver enable"] #[inline(always)] pub fn re(&self) -> RE_R { RE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Transmitter enable"] #[inline(always)] pub fn te(&self) -> TE_R { TE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - IDLE interrupt enable"] #[inline(always)] pub fn idleie(&self) -> IDLEIE_R { IDLEIE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - RXNE interrupt enable"] #[inline(always)] pub fn rxneie(&self) -> RXNEIE_R { RXNEIE_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Transmission complete interrupt enable"] #[inline(always)] pub fn tcie(&self) -> TCIE_R { TCIE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - TXE interrupt enable"] #[inline(always)] pub fn txeie(&self) -> TXEIE_R { TXEIE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - PE interrupt enable"] #[inline(always)] pub fn peie(&self) -> PEIE_R { PEIE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Parity selection"] #[inline(always)] pub fn ps(&self) -> PS_R { PS_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Parity control enable"] #[inline(always)] pub fn pce(&self) -> PCE_R { PCE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Wakeup method"] #[inline(always)] pub fn wake(&self) -> WAKE_R { WAKE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Word length"] #[inline(always)] pub fn m(&self) -> M_R { M_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - USART enable"] #[inline(always)] pub fn ue(&self) -> UE_R { UE_R::new(((self.bits >> 13) & 1) != 0) } } impl W { #[doc = "Bit 0 - Send break"] #[inline(always)] #[must_use] pub fn sbk(&mut self) -> SBK_W<0> { SBK_W::new(self) } #[doc = "Bit 1 - Receiver wakeup"] #[inline(always)] #[must_use] pub fn rwu(&mut self) -> RWU_W<1> { RWU_W::new(self) } #[doc = "Bit 2 - Receiver enable"] #[inline(always)] #[must_use] pub fn re(&mut self) -> RE_W<2> { RE_W::new(self) } #[doc = "Bit 3 - Transmitter enable"] #[inline(always)] #[must_use] pub fn te(&mut self) -> TE_W<3> { TE_W::new(self) } #[doc = "Bit 4 - IDLE interrupt enable"] #[inline(always)] #[must_use] pub fn idleie(&mut self) -> IDLEIE_W<4> { IDLEIE_W::new(self) } #[doc = "Bit 5 - RXNE interrupt enable"] #[inline(always)] #[must_use] pub fn rxneie(&mut self) -> RXNEIE_W<5> { RXNEIE_W::new(self) } #[doc = "Bit 6 - Transmission complete interrupt enable"] #[inline(always)] #[must_use] pub fn tcie(&mut self) -> TCIE_W<6> { TCIE_W::new(self) } #[doc = "Bit 7 - TXE interrupt enable"] #[inline(always)] #[must_use] pub fn txeie(&mut self) -> TXEIE_W<7> { TXEIE_W::new(self) } #[doc = "Bit 8 - PE interrupt enable"] #[inline(always)] #[must_use] pub fn peie(&mut self) -> PEIE_W<8> { PEIE_W::new(self) } #[doc = "Bit 9 - Parity selection"] #[inline(always)] #[must_use] pub fn ps(&mut self) -> PS_W<9> { PS_W::new(self) } #[doc = "Bit 10 - Parity control enable"] #[inline(always)] #[must_use] pub fn pce(&mut self) -> PCE_W<10> { PCE_W::new(self) } #[doc = "Bit 11 - Wakeup method"] #[inline(always)] #[must_use] pub fn wake(&mut self) -> WAKE_W<11> { WAKE_W::new(self) } #[doc = "Bit 12 - Word length"] #[inline(always)] #[must_use] pub fn m(&mut self) -> M_W<12> { M_W::new(self) } #[doc = "Bit 13 - USART enable"] #[inline(always)] #[must_use] pub fn ue(&mut self) -> UE_W<13> { UE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "Control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ADD` reader - Address of the USART node"] pub type ADD_R = crate::FieldReader; #[doc = "Field `ADD` writer - Address of the USART node"] pub type ADD_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 4, O>; #[doc = "Field `LBCL` reader - Last bit clock pulse"] pub type LBCL_R = crate::BitReader; #[doc = "Field `LBCL` writer - Last bit clock pulse"] pub type LBCL_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `CPHA` reader - Clock phase"] pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - Clock phase"] pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `CPOL` reader - Clock polarity"] pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - Clock polarity"] pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `CLKEN` reader - Clock enable"] pub type CLKEN_R = crate::BitReader; #[doc = "Field `CLKEN` writer - Clock enable"] pub type CLKEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `STOP` reader - STOP bits"] pub type STOP_R = crate::FieldReader; #[doc = "Field `STOP` writer - STOP bits"] pub type STOP_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 2, O>; impl R { #[doc = "Bits 0:3 - Address of the USART node"] #[inline(always)] pub fn add(&self) -> ADD_R { ADD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bit 8 - Last bit clock pulse"] #[inline(always)] pub fn lbcl(&self) -> LBCL_R { LBCL_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Clock phase"] #[inline(always)] pub fn cpha(&self) -> CPHA_R { CPHA_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Clock polarity"] #[inline(always)] pub fn cpol(&self) -> CPOL_R { CPOL_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Clock enable"] #[inline(always)] pub fn clken(&self) -> CLKEN_R { CLKEN_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bits 12:13 - STOP bits"] #[inline(always)] pub fn stop(&self) -> STOP_R { STOP_R::new(((self.bits >> 12) & 3) as u8) } } impl W { #[doc = "Bits 0:3 - Address of the USART node"] #[inline(always)] #[must_use] pub fn add(&mut self) -> ADD_W<0> { ADD_W::new(self) } #[doc = "Bit 8 - Last bit clock pulse"] #[inline(always)] #[must_use] pub fn lbcl(&mut self) -> LBCL_W<8> { LBCL_W::new(self) } #[doc = "Bit 9 - Clock phase"] #[inline(always)] #[must_use] pub fn cpha(&mut self) -> CPHA_W<9> { CPHA_W::new(self) } #[doc = "Bit 10 - Clock polarity"] #[inline(always)] #[must_use] pub fn cpol(&mut self) -> CPOL_W<10> { CPOL_W::new(self) } #[doc = "Bit 11 - Clock enable"] #[inline(always)] #[must_use] pub fn clken(&mut self) -> CLKEN_W<11> { CLKEN_W::new(self) } #[doc = "Bits 12:13 - STOP bits"] #[inline(always)] #[must_use] pub fn stop(&mut self) -> STOP_W<12> { STOP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR3 (rw) register accessor: an alias for `Reg`"] pub type CR3 = crate::Reg; #[doc = "Control register 3"] pub mod cr3 { #[doc = "Register `CR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EIE` reader - Error interrupt enable"] pub type EIE_R = crate::BitReader; #[doc = "Field `EIE` writer - Error interrupt enable"] pub type EIE_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `IREN` reader - IrDA mode enable"] pub type IREN_R = crate::BitReader; #[doc = "Field `IREN` writer - IrDA mode enable"] pub type IREN_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `IRLP` reader - IrDA low-power"] pub type IRLP_R = crate::BitReader; #[doc = "Field `IRLP` writer - IrDA low-power"] pub type IRLP_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `HDSEL` reader - Half-duplex selection"] pub type HDSEL_R = crate::BitReader; #[doc = "Field `HDSEL` writer - Half-duplex selection"] pub type HDSEL_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `DMAR` reader - DMA enable receiver"] pub type DMAR_R = crate::BitReader; #[doc = "Field `DMAR` writer - DMA enable receiver"] pub type DMAR_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `DMAT` reader - DMA enable transmitter"] pub type DMAT_R = crate::BitReader; #[doc = "Field `DMAT` writer - DMA enable transmitter"] pub type DMAT_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `RTSE` reader - RTS enable"] pub type RTSE_R = crate::BitReader; #[doc = "Field `RTSE` writer - RTS enable"] pub type RTSE_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `CTSE` reader - CTS enable"] pub type CTSE_R = crate::BitReader; #[doc = "Field `CTSE` writer - CTS enable"] pub type CTSE_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `CTSIE` reader - CTS interrupt enable"] pub type CTSIE_R = crate::BitReader; #[doc = "Field `CTSIE` writer - CTS interrupt enable"] pub type CTSIE_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `OVER8` reader - Oversampling mode"] pub type OVER8_R = crate::BitReader; #[doc = "Field `OVER8` writer - Oversampling mode"] pub type OVER8_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `ABREN` reader - Auto baudrate enable"] pub type ABREN_R = crate::BitReader; #[doc = "Field `ABREN` writer - Auto baudrate enable"] pub type ABREN_W<'a, const O: u8> = crate::BitWriter<'a, CR3_SPEC, O>; #[doc = "Field `ABRMOD` reader - Auto baudrate mode"] pub type ABRMOD_R = crate::FieldReader; #[doc = "Field `ABRMOD` writer - Auto baudrate mode"] pub type ABRMOD_W<'a, const O: u8> = crate::FieldWriter<'a, CR3_SPEC, 2, O>; impl R { #[doc = "Bit 0 - Error interrupt enable"] #[inline(always)] pub fn eie(&self) -> EIE_R { EIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - IrDA mode enable"] #[inline(always)] pub fn iren(&self) -> IREN_R { IREN_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - IrDA low-power"] #[inline(always)] pub fn irlp(&self) -> IRLP_R { IRLP_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Half-duplex selection"] #[inline(always)] pub fn hdsel(&self) -> HDSEL_R { HDSEL_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 6 - DMA enable receiver"] #[inline(always)] pub fn dmar(&self) -> DMAR_R { DMAR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - DMA enable transmitter"] #[inline(always)] pub fn dmat(&self) -> DMAT_R { DMAT_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - RTS enable"] #[inline(always)] pub fn rtse(&self) -> RTSE_R { RTSE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - CTS enable"] #[inline(always)] pub fn ctse(&self) -> CTSE_R { CTSE_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - CTS interrupt enable"] #[inline(always)] pub fn ctsie(&self) -> CTSIE_R { CTSIE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Oversampling mode"] #[inline(always)] pub fn over8(&self) -> OVER8_R { OVER8_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Auto baudrate enable"] #[inline(always)] pub fn abren(&self) -> ABREN_R { ABREN_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bits 13:14 - Auto baudrate mode"] #[inline(always)] pub fn abrmod(&self) -> ABRMOD_R { ABRMOD_R::new(((self.bits >> 13) & 3) as u8) } } impl W { #[doc = "Bit 0 - Error interrupt enable"] #[inline(always)] #[must_use] pub fn eie(&mut self) -> EIE_W<0> { EIE_W::new(self) } #[doc = "Bit 1 - IrDA mode enable"] #[inline(always)] #[must_use] pub fn iren(&mut self) -> IREN_W<1> { IREN_W::new(self) } #[doc = "Bit 2 - IrDA low-power"] #[inline(always)] #[must_use] pub fn irlp(&mut self) -> IRLP_W<2> { IRLP_W::new(self) } #[doc = "Bit 3 - Half-duplex selection"] #[inline(always)] #[must_use] pub fn hdsel(&mut self) -> HDSEL_W<3> { HDSEL_W::new(self) } #[doc = "Bit 6 - DMA enable receiver"] #[inline(always)] #[must_use] pub fn dmar(&mut self) -> DMAR_W<6> { DMAR_W::new(self) } #[doc = "Bit 7 - DMA enable transmitter"] #[inline(always)] #[must_use] pub fn dmat(&mut self) -> DMAT_W<7> { DMAT_W::new(self) } #[doc = "Bit 8 - RTS enable"] #[inline(always)] #[must_use] pub fn rtse(&mut self) -> RTSE_W<8> { RTSE_W::new(self) } #[doc = "Bit 9 - CTS enable"] #[inline(always)] #[must_use] pub fn ctse(&mut self) -> CTSE_W<9> { CTSE_W::new(self) } #[doc = "Bit 10 - CTS interrupt enable"] #[inline(always)] #[must_use] pub fn ctsie(&mut self) -> CTSIE_W<10> { CTSIE_W::new(self) } #[doc = "Bit 11 - Oversampling mode"] #[inline(always)] #[must_use] pub fn over8(&mut self) -> OVER8_W<11> { OVER8_W::new(self) } #[doc = "Bit 12 - Auto baudrate enable"] #[inline(always)] #[must_use] pub fn abren(&mut self) -> ABREN_W<12> { ABREN_W::new(self) } #[doc = "Bits 13:14 - Auto baudrate mode"] #[inline(always)] #[must_use] pub fn abrmod(&mut self) -> ABRMOD_W<13> { ABRMOD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr3](index.html) module"] pub struct CR3_SPEC; impl crate::RegisterSpec for CR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr3::R](R) reader structure"] impl crate::Readable for CR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr3::W](W) writer structure"] impl crate::Writable for CR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR3 to value 0"] impl crate::Resettable for CR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Universal synchronous asynchronous receiver transmitter"] pub struct USART2 { _marker: PhantomData<*const ()>, } unsafe impl Send for USART2 {} impl USART2 { #[doc = r"Pointer to the register block"] pub const PTR: *const usart1::RegisterBlock = 0x4000_4400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const usart1::RegisterBlock { Self::PTR } } impl Deref for USART2 { type Target = usart1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for USART2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("USART2").finish() } } #[doc = "Universal synchronous asynchronous receiver transmitter"] pub use self::usart1 as usart2; #[doc = "Real time clock"] pub struct RTC { _marker: PhantomData<*const ()>, } unsafe impl Send for RTC {} impl RTC { #[doc = r"Pointer to the register block"] pub const PTR: *const rtc::RegisterBlock = 0x4000_2800 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const rtc::RegisterBlock { Self::PTR } } impl Deref for RTC { type Target = rtc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for RTC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("RTC").finish() } } #[doc = "Real time clock"] pub mod rtc { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - RTC Control Register High"] pub crh: CRH, #[doc = "0x04 - RTC Control Register Low"] pub crl: CRL, #[doc = "0x08 - RTC Prescaler Load Register High"] pub prlh: PRLH, #[doc = "0x0c - RTC Prescaler Load Register Low"] pub prll: PRLL, #[doc = "0x10 - RTC Prescaler Divider Register High"] pub divh: DIVH, #[doc = "0x14 - RTC Prescaler Divider Register Low"] pub divl: DIVL, #[doc = "0x18 - RTC Counter Register High"] pub cnth: CNTH, #[doc = "0x1c - RTC Counter Register Low"] pub cntl: CNTL, #[doc = "0x20 - RTC Alarm Register High"] pub alrh: ALRH, #[doc = "0x24 - RTC Alarm Register Low"] pub alrl: ALRL, _reserved10: [u8; 0x04], #[doc = "0x2c - RTC clock calibration"] pub rtccr: RTCCR, } #[doc = "CRH (rw) register accessor: an alias for `Reg`"] pub type CRH = crate::Reg; #[doc = "RTC Control Register High"] pub mod crh { #[doc = "Register `CRH` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CRH` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SECIE` reader - Second interrupt Enable"] pub type SECIE_R = crate::BitReader; #[doc = "Field `SECIE` writer - Second interrupt Enable"] pub type SECIE_W<'a, const O: u8> = crate::BitWriter<'a, CRH_SPEC, O>; #[doc = "Field `ALRIE` reader - Alarm interrupt Enable"] pub type ALRIE_R = crate::BitReader; #[doc = "Field `ALRIE` writer - Alarm interrupt Enable"] pub type ALRIE_W<'a, const O: u8> = crate::BitWriter<'a, CRH_SPEC, O>; #[doc = "Field `OWIE` reader - Overflow interrupt Enable"] pub type OWIE_R = crate::BitReader; #[doc = "Field `OWIE` writer - Overflow interrupt Enable"] pub type OWIE_W<'a, const O: u8> = crate::BitWriter<'a, CRH_SPEC, O>; impl R { #[doc = "Bit 0 - Second interrupt Enable"] #[inline(always)] pub fn secie(&self) -> SECIE_R { SECIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Alarm interrupt Enable"] #[inline(always)] pub fn alrie(&self) -> ALRIE_R { ALRIE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Overflow interrupt Enable"] #[inline(always)] pub fn owie(&self) -> OWIE_R { OWIE_R::new(((self.bits >> 2) & 1) != 0) } } impl W { #[doc = "Bit 0 - Second interrupt Enable"] #[inline(always)] #[must_use] pub fn secie(&mut self) -> SECIE_W<0> { SECIE_W::new(self) } #[doc = "Bit 1 - Alarm interrupt Enable"] #[inline(always)] #[must_use] pub fn alrie(&mut self) -> ALRIE_W<1> { ALRIE_W::new(self) } #[doc = "Bit 2 - Overflow interrupt Enable"] #[inline(always)] #[must_use] pub fn owie(&mut self) -> OWIE_W<2> { OWIE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Control Register High\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crh](index.html) module"] pub struct CRH_SPEC; impl crate::RegisterSpec for CRH_SPEC { type Ux = u32; } #[doc = "`read()` method returns [crh::R](R) reader structure"] impl crate::Readable for CRH_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [crh::W](W) writer structure"] impl crate::Writable for CRH_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CRH to value 0"] impl crate::Resettable for CRH_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CRL (rw) register accessor: an alias for `Reg`"] pub type CRL = crate::Reg; #[doc = "RTC Control Register Low"] pub mod crl { #[doc = "Register `CRL` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CRL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SECF` reader - Second Flag"] pub type SECF_R = crate::BitReader; #[doc = "Field `SECF` writer - Second Flag"] pub type SECF_W<'a, const O: u8> = crate::BitWriter<'a, CRL_SPEC, O>; #[doc = "Field `ALRF` reader - Alarm Flag"] pub type ALRF_R = crate::BitReader; #[doc = "Field `ALRF` writer - Alarm Flag"] pub type ALRF_W<'a, const O: u8> = crate::BitWriter<'a, CRL_SPEC, O>; #[doc = "Field `OWF` reader - Overflow Flag"] pub type OWF_R = crate::BitReader; #[doc = "Field `OWF` writer - Overflow Flag"] pub type OWF_W<'a, const O: u8> = crate::BitWriter<'a, CRL_SPEC, O>; #[doc = "Field `RSF` reader - Registers Synchronized Flag"] pub type RSF_R = crate::BitReader; #[doc = "Field `RSF` writer - Registers Synchronized Flag"] pub type RSF_W<'a, const O: u8> = crate::BitWriter<'a, CRL_SPEC, O>; #[doc = "Field `CNF` reader - Configuration Flag"] pub type CNF_R = crate::BitReader; #[doc = "Field `CNF` writer - Configuration Flag"] pub type CNF_W<'a, const O: u8> = crate::BitWriter<'a, CRL_SPEC, O>; #[doc = "Field `RTOFF` reader - RTC operation OFF"] pub type RTOFF_R = crate::BitReader; impl R { #[doc = "Bit 0 - Second Flag"] #[inline(always)] pub fn secf(&self) -> SECF_R { SECF_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Alarm Flag"] #[inline(always)] pub fn alrf(&self) -> ALRF_R { ALRF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Overflow Flag"] #[inline(always)] pub fn owf(&self) -> OWF_R { OWF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Registers Synchronized Flag"] #[inline(always)] pub fn rsf(&self) -> RSF_R { RSF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Configuration Flag"] #[inline(always)] pub fn cnf(&self) -> CNF_R { CNF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - RTC operation OFF"] #[inline(always)] pub fn rtoff(&self) -> RTOFF_R { RTOFF_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - Second Flag"] #[inline(always)] #[must_use] pub fn secf(&mut self) -> SECF_W<0> { SECF_W::new(self) } #[doc = "Bit 1 - Alarm Flag"] #[inline(always)] #[must_use] pub fn alrf(&mut self) -> ALRF_W<1> { ALRF_W::new(self) } #[doc = "Bit 2 - Overflow Flag"] #[inline(always)] #[must_use] pub fn owf(&mut self) -> OWF_W<2> { OWF_W::new(self) } #[doc = "Bit 3 - Registers Synchronized Flag"] #[inline(always)] #[must_use] pub fn rsf(&mut self) -> RSF_W<3> { RSF_W::new(self) } #[doc = "Bit 4 - Configuration Flag"] #[inline(always)] #[must_use] pub fn cnf(&mut self) -> CNF_W<4> { CNF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Control Register Low\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crl](index.html) module"] pub struct CRL_SPEC; impl crate::RegisterSpec for CRL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [crl::R](R) reader structure"] impl crate::Readable for CRL_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [crl::W](W) writer structure"] impl crate::Writable for CRL_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CRL to value 0x20"] impl crate::Resettable for CRL_SPEC { const RESET_VALUE: Self::Ux = 0x20; } } #[doc = "PRLH (w) register accessor: an alias for `Reg`"] pub type PRLH = crate::Reg; #[doc = "RTC Prescaler Load Register High"] pub mod prlh { #[doc = "Register `PRLH` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PRLH` writer - RTC Prescaler Load Register High"] pub type PRLH_W<'a, const O: u8> = crate::FieldWriter<'a, PRLH_SPEC, 4, O>; impl W { #[doc = "Bits 0:3 - RTC Prescaler Load Register High"] #[inline(always)] #[must_use] pub fn prlh(&mut self) -> PRLH_W<0> { PRLH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Prescaler Load Register High\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prlh](index.html) module"] pub struct PRLH_SPEC; impl crate::RegisterSpec for PRLH_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [prlh::W](W) writer structure"] impl crate::Writable for PRLH_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PRLH to value 0"] impl crate::Resettable for PRLH_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PRLL (w) register accessor: an alias for `Reg`"] pub type PRLL = crate::Reg; #[doc = "RTC Prescaler Load Register Low"] pub mod prll { #[doc = "Register `PRLL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PRLL` writer - RTC Prescaler Divider Register Low"] pub type PRLL_W<'a, const O: u8> = crate::FieldWriter<'a, PRLL_SPEC, 16, O, u16>; impl W { #[doc = "Bits 0:15 - RTC Prescaler Divider Register Low"] #[inline(always)] #[must_use] pub fn prll(&mut self) -> PRLL_W<0> { PRLL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Prescaler Load Register Low\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prll](index.html) module"] pub struct PRLL_SPEC; impl crate::RegisterSpec for PRLL_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [prll::W](W) writer structure"] impl crate::Writable for PRLL_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PRLL to value 0x8000"] impl crate::Resettable for PRLL_SPEC { const RESET_VALUE: Self::Ux = 0x8000; } } #[doc = "DIVH (r) register accessor: an alias for `Reg`"] pub type DIVH = crate::Reg; #[doc = "RTC Prescaler Divider Register High"] pub mod divh { #[doc = "Register `DIVH` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `DIVH` reader - RTC prescaler divider register high"] pub type DIVH_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - RTC prescaler divider register high"] #[inline(always)] pub fn divh(&self) -> DIVH_R { DIVH_R::new((self.bits & 0x0f) as u8) } } #[doc = "RTC Prescaler Divider Register High\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divh](index.html) module"] pub struct DIVH_SPEC; impl crate::RegisterSpec for DIVH_SPEC { type Ux = u32; } #[doc = "`read()` method returns [divh::R](R) reader structure"] impl crate::Readable for DIVH_SPEC { type Reader = R; } #[doc = "`reset()` method sets DIVH to value 0"] impl crate::Resettable for DIVH_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DIVL (r) register accessor: an alias for `Reg`"] pub type DIVL = crate::Reg; #[doc = "RTC Prescaler Divider Register Low"] pub mod divl { #[doc = "Register `DIVL` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `DIVL` reader - RTC prescaler divider register Low"] pub type DIVL_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - RTC prescaler divider register Low"] #[inline(always)] pub fn divl(&self) -> DIVL_R { DIVL_R::new((self.bits & 0xffff) as u16) } } #[doc = "RTC Prescaler Divider Register Low\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divl](index.html) module"] pub struct DIVL_SPEC; impl crate::RegisterSpec for DIVL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [divl::R](R) reader structure"] impl crate::Readable for DIVL_SPEC { type Reader = R; } #[doc = "`reset()` method sets DIVL to value 0x8000"] impl crate::Resettable for DIVL_SPEC { const RESET_VALUE: Self::Ux = 0x8000; } } #[doc = "CNTH (rw) register accessor: an alias for `Reg`"] pub type CNTH = crate::Reg; #[doc = "RTC Counter Register High"] pub mod cnth { #[doc = "Register `CNTH` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNTH` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CNTH` reader - RTC counter register high"] pub type CNTH_R = crate::FieldReader; #[doc = "Field `CNTH` writer - RTC counter register high"] pub type CNTH_W<'a, const O: u8> = crate::FieldWriter<'a, CNTH_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - RTC counter register high"] #[inline(always)] pub fn cnth(&self) -> CNTH_R { CNTH_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - RTC counter register high"] #[inline(always)] #[must_use] pub fn cnth(&mut self) -> CNTH_W<0> { CNTH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Counter Register High\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnth](index.html) module"] pub struct CNTH_SPEC; impl crate::RegisterSpec for CNTH_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cnth::R](R) reader structure"] impl crate::Readable for CNTH_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cnth::W](W) writer structure"] impl crate::Writable for CNTH_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNTH to value 0"] impl crate::Resettable for CNTH_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNTL (rw) register accessor: an alias for `Reg`"] pub type CNTL = crate::Reg; #[doc = "RTC Counter Register Low"] pub mod cntl { #[doc = "Register `CNTL` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNTL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CNTL` reader - RTC counter register Low"] pub type CNTL_R = crate::FieldReader; #[doc = "Field `CNTL` writer - RTC counter register Low"] pub type CNTL_W<'a, const O: u8> = crate::FieldWriter<'a, CNTL_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - RTC counter register Low"] #[inline(always)] pub fn cntl(&self) -> CNTL_R { CNTL_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - RTC counter register Low"] #[inline(always)] #[must_use] pub fn cntl(&mut self) -> CNTL_W<0> { CNTL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Counter Register Low\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] pub struct CNTL_SPEC; impl crate::RegisterSpec for CNTL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cntl::R](R) reader structure"] impl crate::Readable for CNTL_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] impl crate::Writable for CNTL_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNTL to value 0"] impl crate::Resettable for CNTL_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ALRH (w) register accessor: an alias for `Reg`"] pub type ALRH = crate::Reg; #[doc = "RTC Alarm Register High"] pub mod alrh { #[doc = "Register `ALRH` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ALRH` writer - RTC alarm register high"] pub type ALRH_W<'a, const O: u8> = crate::FieldWriter<'a, ALRH_SPEC, 16, O, u16>; impl W { #[doc = "Bits 0:15 - RTC alarm register high"] #[inline(always)] #[must_use] pub fn alrh(&mut self) -> ALRH_W<0> { ALRH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Alarm Register High\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alrh](index.html) module"] pub struct ALRH_SPEC; impl crate::RegisterSpec for ALRH_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [alrh::W](W) writer structure"] impl crate::Writable for ALRH_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ALRH to value 0xffff"] impl crate::Resettable for ALRH_SPEC { const RESET_VALUE: Self::Ux = 0xffff; } } #[doc = "ALRL (w) register accessor: an alias for `Reg`"] pub type ALRL = crate::Reg; #[doc = "RTC Alarm Register Low"] pub mod alrl { #[doc = "Register `ALRL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ALRL` writer - RTC alarm register low"] pub type ALRL_W<'a, const O: u8> = crate::FieldWriter<'a, ALRL_SPEC, 16, O, u16>; impl W { #[doc = "Bits 0:15 - RTC alarm register low"] #[inline(always)] #[must_use] pub fn alrl(&mut self) -> ALRL_W<0> { ALRL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC Alarm Register Low\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alrl](index.html) module"] pub struct ALRL_SPEC; impl crate::RegisterSpec for ALRL_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [alrl::W](W) writer structure"] impl crate::Writable for ALRL_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ALRL to value 0xffff"] impl crate::Resettable for ALRL_SPEC { const RESET_VALUE: Self::Ux = 0xffff; } } #[doc = "RTCCR (rw) register accessor: an alias for `Reg`"] pub type RTCCR = crate::Reg; #[doc = "RTC clock calibration"] pub mod rtccr { #[doc = "Register `RTCCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `RTCCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CAL` reader - Calibration value"] pub type CAL_R = crate::FieldReader; #[doc = "Field `CAL` writer - Calibration value"] pub type CAL_W<'a, const O: u8> = crate::FieldWriter<'a, RTCCR_SPEC, 7, O>; #[doc = "Field `CCO` reader - Calibration clock output"] pub type CCO_R = crate::BitReader; #[doc = "Field `CCO` writer - Calibration clock output"] pub type CCO_W<'a, const O: u8> = crate::BitWriter<'a, RTCCR_SPEC, O>; #[doc = "Field `ASOE` reader - Alarm or second output enable"] pub type ASOE_R = crate::BitReader; #[doc = "Field `ASOE` writer - Alarm or second output enable"] pub type ASOE_W<'a, const O: u8> = crate::BitWriter<'a, RTCCR_SPEC, O>; #[doc = "Field `ASOS` reader - Alarm or second output selection"] pub type ASOS_R = crate::BitReader; #[doc = "Field `ASOS` writer - Alarm or second output selection"] pub type ASOS_W<'a, const O: u8> = crate::BitWriter<'a, RTCCR_SPEC, O>; impl R { #[doc = "Bits 0:6 - Calibration value"] #[inline(always)] pub fn cal(&self) -> CAL_R { CAL_R::new((self.bits & 0x7f) as u8) } #[doc = "Bit 7 - Calibration clock output"] #[inline(always)] pub fn cco(&self) -> CCO_R { CCO_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Alarm or second output enable"] #[inline(always)] pub fn asoe(&self) -> ASOE_R { ASOE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Alarm or second output selection"] #[inline(always)] pub fn asos(&self) -> ASOS_R { ASOS_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:6 - Calibration value"] #[inline(always)] #[must_use] pub fn cal(&mut self) -> CAL_W<0> { CAL_W::new(self) } #[doc = "Bit 7 - Calibration clock output"] #[inline(always)] #[must_use] pub fn cco(&mut self) -> CCO_W<7> { CCO_W::new(self) } #[doc = "Bit 8 - Alarm or second output enable"] #[inline(always)] #[must_use] pub fn asoe(&mut self) -> ASOE_W<8> { ASOE_W::new(self) } #[doc = "Bit 9 - Alarm or second output selection"] #[inline(always)] #[must_use] pub fn asos(&mut self) -> ASOS_W<9> { ASOS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "RTC clock calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtccr](index.html) module"] pub struct RTCCR_SPEC; impl crate::RegisterSpec for RTCCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [rtccr::R](R) reader structure"] impl crate::Readable for RTCCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [rtccr::W](W) writer structure"] impl crate::Writable for RTCCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets RTCCR to value 0"] impl crate::Resettable for RTCCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Independent watchdog"] pub struct IWDG { _marker: PhantomData<*const ()>, } unsafe impl Send for IWDG {} impl IWDG { #[doc = r"Pointer to the register block"] pub const PTR: *const iwdg::RegisterBlock = 0x4000_3000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const iwdg::RegisterBlock { Self::PTR } } impl Deref for IWDG { type Target = iwdg::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for IWDG { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("IWDG").finish() } } #[doc = "Independent watchdog"] pub mod iwdg { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Key register (IWDG_KR)"] pub kr: KR, #[doc = "0x04 - Prescaler register (IWDG_PR)"] pub pr: PR, #[doc = "0x08 - Reload register (IWDG_RLR)"] pub rlr: RLR, #[doc = "0x0c - Status register (IWDG_SR)"] pub sr: SR, #[doc = "0x10 - Window register (IWDG_SR)"] pub winr: WINR, } #[doc = "KR (w) register accessor: an alias for `Reg`"] pub type KR = crate::Reg; #[doc = "Key register (IWDG_KR)"] pub mod kr { #[doc = "Register `KR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `KEY` writer - Key value"] pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, KR_SPEC, 16, O, u16>; impl W { #[doc = "Bits 0:15 - Key value"] #[inline(always)] #[must_use] pub fn key(&mut self) -> KEY_W<0> { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Key register (IWDG_KR)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [kr](index.html) module"] pub struct KR_SPEC; impl crate::RegisterSpec for KR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [kr::W](W) writer structure"] impl crate::Writable for KR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets KR to value 0"] impl crate::Resettable for KR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PR (rw) register accessor: an alias for `Reg`"] pub type PR = crate::Reg; #[doc = "Prescaler register (IWDG_PR)"] pub mod pr { #[doc = "Register `PR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PR` reader - Prescaler divider"] pub type PR_R = crate::FieldReader; #[doc = "Field `PR` writer - Prescaler divider"] pub type PR_W<'a, const O: u8> = crate::FieldWriter<'a, PR_SPEC, 3, O>; impl R { #[doc = "Bits 0:2 - Prescaler divider"] #[inline(always)] pub fn pr(&self) -> PR_R { PR_R::new((self.bits & 7) as u8) } } impl W { #[doc = "Bits 0:2 - Prescaler divider"] #[inline(always)] #[must_use] pub fn pr(&mut self) -> PR_W<0> { PR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Prescaler register (IWDG_PR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](index.html) module"] pub struct PR_SPEC; impl crate::RegisterSpec for PR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pr::R](R) reader structure"] impl crate::Readable for PR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pr::W](W) writer structure"] impl crate::Writable for PR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PR to value 0"] impl crate::Resettable for PR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "RLR (rw) register accessor: an alias for `Reg`"] pub type RLR = crate::Reg; #[doc = "Reload register (IWDG_RLR)"] pub mod rlr { #[doc = "Register `RLR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `RLR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RL` reader - Watchdog counter reload value"] pub type RL_R = crate::FieldReader; #[doc = "Field `RL` writer - Watchdog counter reload value"] pub type RL_W<'a, const O: u8> = crate::FieldWriter<'a, RLR_SPEC, 12, O, u16>; impl R { #[doc = "Bits 0:11 - Watchdog counter reload value"] #[inline(always)] pub fn rl(&self) -> RL_R { RL_R::new((self.bits & 0x0fff) as u16) } } impl W { #[doc = "Bits 0:11 - Watchdog counter reload value"] #[inline(always)] #[must_use] pub fn rl(&mut self) -> RL_W<0> { RL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Reload register (IWDG_RLR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rlr](index.html) module"] pub struct RLR_SPEC; impl crate::RegisterSpec for RLR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [rlr::R](R) reader structure"] impl crate::Readable for RLR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [rlr::W](W) writer structure"] impl crate::Writable for RLR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets RLR to value 0x0fff"] impl crate::Resettable for RLR_SPEC { const RESET_VALUE: Self::Ux = 0x0fff; } } #[doc = "SR (r) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "Status register (IWDG_SR)"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `PVU` reader - Watchdog prescaler value update"] pub type PVU_R = crate::BitReader; #[doc = "Field `RVU` reader - Watchdog counter reload value update"] pub type RVU_R = crate::BitReader; #[doc = "Field `WVU` reader - Watchdog counter window value update"] pub type WVU_R = crate::BitReader; impl R { #[doc = "Bit 0 - Watchdog prescaler value update"] #[inline(always)] pub fn pvu(&self) -> PVU_R { PVU_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Watchdog counter reload value update"] #[inline(always)] pub fn rvu(&self) -> RVU_R { RVU_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Watchdog counter window value update"] #[inline(always)] pub fn wvu(&self) -> WVU_R { WVU_R::new(((self.bits >> 2) & 1) != 0) } } #[doc = "Status register (IWDG_SR)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "WINR (r) register accessor: an alias for `Reg`"] pub type WINR = crate::Reg; #[doc = "Window register (IWDG_SR)"] pub mod winr { #[doc = "Register `WINR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `WIN` reader - window counter"] pub type WIN_R = crate::FieldReader; impl R { #[doc = "Bits 0:11 - window counter"] #[inline(always)] pub fn win(&self) -> WIN_R { WIN_R::new((self.bits & 0x0fff) as u16) } } #[doc = "Window register (IWDG_SR)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winr](index.html) module"] pub struct WINR_SPEC; impl crate::RegisterSpec for WINR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [winr::R](R) reader structure"] impl crate::Readable for WINR_SPEC { type Reader = R; } #[doc = "`reset()` method sets WINR to value 0"] impl crate::Resettable for WINR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Window watchdog"] pub struct WWDG { _marker: PhantomData<*const ()>, } unsafe impl Send for WWDG {} impl WWDG { #[doc = r"Pointer to the register block"] pub const PTR: *const wwdg::RegisterBlock = 0x4000_2c00 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const wwdg::RegisterBlock { Self::PTR } } impl Deref for WWDG { type Target = wwdg::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for WWDG { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("WWDG").finish() } } #[doc = "Window watchdog"] pub mod wwdg { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Control register (WWDG_CR)"] pub cr: CR, #[doc = "0x04 - Configuration register (WWDG_CFR)"] pub cfr: CFR, #[doc = "0x08 - Status register (WWDG_SR)"] pub sr: SR, } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Control register (WWDG_CR)"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `T` reader - 7-bit counter (MSB to LSB)"] pub type T_R = crate::FieldReader; #[doc = "Field `T` writer - 7-bit counter (MSB to LSB)"] pub type T_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 7, O>; #[doc = "Field `WDGA` reader - Activation bit"] pub type WDGA_R = crate::BitReader; #[doc = "Field `WDGA` writer - Activation bit"] pub type WDGA_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl R { #[doc = "Bits 0:6 - 7-bit counter (MSB to LSB)"] #[inline(always)] pub fn t(&self) -> T_R { T_R::new((self.bits & 0x7f) as u8) } #[doc = "Bit 7 - Activation bit"] #[inline(always)] pub fn wdga(&self) -> WDGA_R { WDGA_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bits 0:6 - 7-bit counter (MSB to LSB)"] #[inline(always)] #[must_use] pub fn t(&mut self) -> T_W<0> { T_W::new(self) } #[doc = "Bit 7 - Activation bit"] #[inline(always)] #[must_use] pub fn wdga(&mut self) -> WDGA_W<7> { WDGA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register (WWDG_CR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0x7f"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0x7f; } } #[doc = "CFR (rw) register accessor: an alias for `Reg`"] pub type CFR = crate::Reg; #[doc = "Configuration register (WWDG_CFR)"] pub mod cfr { #[doc = "Register `CFR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `W` reader - 7-bit window value"] pub type W_R = crate::FieldReader; #[doc = "Field `W` writer - 7-bit window value"] pub type W_W<'a, const O: u8> = crate::FieldWriter<'a, CFR_SPEC, 7, O>; #[doc = "Field `WDGTB` reader - Timer Base"] pub type WDGTB_R = crate::FieldReader; #[doc = "Field `WDGTB` writer - Timer Base"] pub type WDGTB_W<'a, const O: u8> = crate::FieldWriter<'a, CFR_SPEC, 2, O>; #[doc = "Field `EWI` reader - Early Wakeup Interrupt"] pub type EWI_R = crate::BitReader; #[doc = "Field `EWI` writer - Early Wakeup Interrupt"] pub type EWI_W<'a, const O: u8> = crate::BitWriter<'a, CFR_SPEC, O>; impl R { #[doc = "Bits 0:6 - 7-bit window value"] #[inline(always)] pub fn w(&self) -> W_R { W_R::new((self.bits & 0x7f) as u8) } #[doc = "Bits 7:8 - Timer Base"] #[inline(always)] pub fn wdgtb(&self) -> WDGTB_R { WDGTB_R::new(((self.bits >> 7) & 3) as u8) } #[doc = "Bit 9 - Early Wakeup Interrupt"] #[inline(always)] pub fn ewi(&self) -> EWI_R { EWI_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:6 - 7-bit window value"] #[inline(always)] #[must_use] pub fn w(&mut self) -> W_W<0> { W_W::new(self) } #[doc = "Bits 7:8 - Timer Base"] #[inline(always)] #[must_use] pub fn wdgtb(&mut self) -> WDGTB_W<7> { WDGTB_W::new(self) } #[doc = "Bit 9 - Early Wakeup Interrupt"] #[inline(always)] #[must_use] pub fn ewi(&mut self) -> EWI_W<9> { EWI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Configuration register (WWDG_CFR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfr](index.html) module"] pub struct CFR_SPEC; impl crate::RegisterSpec for CFR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfr::R](R) reader structure"] impl crate::Readable for CFR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfr::W](W) writer structure"] impl crate::Writable for CFR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFR to value 0x7f"] impl crate::Resettable for CFR_SPEC { const RESET_VALUE: Self::Ux = 0x7f; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "Status register (WWDG_SR)"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EWIF` reader - Early Wakeup Interrupt flag"] pub type EWIF_R = crate::BitReader; #[doc = "Field `EWIF` writer - Early Wakeup Interrupt flag"] pub type EWIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - Early Wakeup Interrupt flag"] #[inline(always)] pub fn ewif(&self) -> EWIF_R { EWIF_R::new((self.bits & 1) != 0) } } impl W { #[doc = "Bit 0 - Early Wakeup Interrupt flag"] #[inline(always)] #[must_use] pub fn ewif(&mut self) -> EWIF_W<0> { EWIF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Status register (WWDG_SR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Advanced timer"] pub struct TIM1 { _marker: PhantomData<*const ()>, } unsafe impl Send for TIM1 {} impl TIM1 { #[doc = r"Pointer to the register block"] pub const PTR: *const tim1::RegisterBlock = 0x4001_2c00 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const tim1::RegisterBlock { Self::PTR } } impl Deref for TIM1 { type Target = tim1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for TIM1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("TIM1").finish() } } #[doc = "Advanced timer"] pub mod tim1 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - control register 1"] pub cr1: CR1, #[doc = "0x04 - control register 2"] pub cr2: CR2, #[doc = "0x08 - slave mode control register"] pub smcr: SMCR, #[doc = "0x0c - DMA/Interrupt enable register"] pub dier: DIER, #[doc = "0x10 - status register"] pub sr: SR, #[doc = "0x14 - event generation register"] pub egr: EGR, _reserved_6_ccmr1: [u8; 0x04], _reserved_7_ccmr2: [u8; 0x04], #[doc = "0x20 - capture/compare enable register"] pub ccer: CCER, #[doc = "0x24 - counter"] pub cnt: CNT, #[doc = "0x28 - prescaler"] pub psc: PSC, #[doc = "0x2c - auto-reload register"] pub arr: ARR, #[doc = "0x30 - repetition counter register"] pub rcr: RCR, #[doc = "0x34 - capture/compare register 1"] pub ccr1: CCR1, #[doc = "0x38 - capture/compare register 2"] pub ccr2: CCR2, #[doc = "0x3c - capture/compare register 3"] pub ccr3: CCR3, #[doc = "0x40 - capture/compare register 4"] pub ccr4: CCR4, #[doc = "0x44 - break and dead-time register"] pub bdtr: BDTR, #[doc = "0x48 - DMA control register"] pub dcr: DCR, #[doc = "0x4c - DMA address for full transfer"] pub dmar: DMAR, } impl RegisterBlock { #[doc = "0x18 - capture/compare mode register 1 (input mode)"] #[inline(always)] pub const fn ccmr1_input(&self) -> &CCMR1_INPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } #[doc = "0x18 - capture/compare mode register (output mode)"] #[inline(always)] pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } #[doc = "0x1c - capture/compare mode register 2 (input mode)"] #[inline(always)] pub const fn ccmr2_input(&self) -> &CCMR2_INPUT { unsafe { &*(self as *const Self).cast::().add(28usize).cast() } } #[doc = "0x1c - capture/compare mode register (output mode)"] #[inline(always)] pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT { unsafe { &*(self as *const Self).cast::().add(28usize).cast() } } } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "control register 1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CEN` reader - Counter enable"] pub type CEN_R = crate::BitReader; #[doc = "Field `CEN` writer - Counter enable"] pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `UDIS` reader - Update disable"] pub type UDIS_R = crate::BitReader; #[doc = "Field `UDIS` writer - Update disable"] pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `URS` reader - Update request source"] pub type URS_R = crate::BitReader; #[doc = "Field `URS` writer - Update request source"] pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `OPM` reader - One-pulse mode"] pub type OPM_R = crate::BitReader; #[doc = "Field `OPM` writer - One-pulse mode"] pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `DIR` reader - Direction"] pub type DIR_R = crate::BitReader; #[doc = "Field `DIR` writer - Direction"] pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CMS` reader - Center-aligned mode selection"] pub type CMS_R = crate::FieldReader; #[doc = "Field `CMS` writer - Center-aligned mode selection"] pub type CMS_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; #[doc = "Field `ARPE` reader - Auto-reload preload enable"] pub type ARPE_R = crate::BitReader; #[doc = "Field `ARPE` writer - Auto-reload preload enable"] pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CKD` reader - Clock division"] pub type CKD_R = crate::FieldReader; #[doc = "Field `CKD` writer - Clock division"] pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; impl R { #[doc = "Bit 0 - Counter enable"] #[inline(always)] pub fn cen(&self) -> CEN_R { CEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Update disable"] #[inline(always)] pub fn udis(&self) -> UDIS_R { UDIS_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Update request source"] #[inline(always)] pub fn urs(&self) -> URS_R { URS_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - One-pulse mode"] #[inline(always)] pub fn opm(&self) -> OPM_R { OPM_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Direction"] #[inline(always)] pub fn dir(&self) -> DIR_R { DIR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bits 5:6 - Center-aligned mode selection"] #[inline(always)] pub fn cms(&self) -> CMS_R { CMS_R::new(((self.bits >> 5) & 3) as u8) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] pub fn arpe(&self) -> ARPE_R { ARPE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Clock division"] #[inline(always)] pub fn ckd(&self) -> CKD_R { CKD_R::new(((self.bits >> 8) & 3) as u8) } } impl W { #[doc = "Bit 0 - Counter enable"] #[inline(always)] #[must_use] pub fn cen(&mut self) -> CEN_W<0> { CEN_W::new(self) } #[doc = "Bit 1 - Update disable"] #[inline(always)] #[must_use] pub fn udis(&mut self) -> UDIS_W<1> { UDIS_W::new(self) } #[doc = "Bit 2 - Update request source"] #[inline(always)] #[must_use] pub fn urs(&mut self) -> URS_W<2> { URS_W::new(self) } #[doc = "Bit 3 - One-pulse mode"] #[inline(always)] #[must_use] pub fn opm(&mut self) -> OPM_W<3> { OPM_W::new(self) } #[doc = "Bit 4 - Direction"] #[inline(always)] #[must_use] pub fn dir(&mut self) -> DIR_W<4> { DIR_W::new(self) } #[doc = "Bits 5:6 - Center-aligned mode selection"] #[inline(always)] #[must_use] pub fn cms(&mut self) -> CMS_W<5> { CMS_W::new(self) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] #[must_use] pub fn arpe(&mut self) -> ARPE_W<7> { ARPE_W::new(self) } #[doc = "Bits 8:9 - Clock division"] #[inline(always)] #[must_use] pub fn ckd(&mut self) -> CKD_W<8> { CKD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCPC` reader - Capture/compare preloaded control"] pub type CCPC_R = crate::BitReader; #[doc = "Field `CCPC` writer - Capture/compare preloaded control"] pub type CCPC_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `CCUS` reader - Capture/compare control update selection"] pub type CCUS_R = crate::BitReader; #[doc = "Field `CCUS` writer - Capture/compare control update selection"] pub type CCUS_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `CCDS` reader - Capture/compare DMA selection"] pub type CCDS_R = crate::BitReader; #[doc = "Field `CCDS` writer - Capture/compare DMA selection"] pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `MMS` reader - Master mode selection"] pub type MMS_R = crate::FieldReader; #[doc = "Field `MMS` writer - Master mode selection"] pub type MMS_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 3, O>; #[doc = "Field `TI1S` reader - TI1 selection"] pub type TI1S_R = crate::BitReader; #[doc = "Field `TI1S` writer - TI1 selection"] pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS1` reader - Output Idle state 1"] pub type OIS1_R = crate::BitReader; #[doc = "Field `OIS1` writer - Output Idle state 1"] pub type OIS1_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS1N` reader - Output Idle state 1"] pub type OIS1N_R = crate::BitReader; #[doc = "Field `OIS1N` writer - Output Idle state 1"] pub type OIS1N_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS2` reader - Output Idle state 2"] pub type OIS2_R = crate::BitReader; #[doc = "Field `OIS2` writer - Output Idle state 2"] pub type OIS2_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS2N` reader - Output Idle state 2"] pub type OIS2N_R = crate::BitReader; #[doc = "Field `OIS2N` writer - Output Idle state 2"] pub type OIS2N_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS3` reader - Output Idle state 3"] pub type OIS3_R = crate::BitReader; #[doc = "Field `OIS3` writer - Output Idle state 3"] pub type OIS3_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS3N` reader - Output Idle state 3"] pub type OIS3N_R = crate::BitReader; #[doc = "Field `OIS3N` writer - Output Idle state 3"] pub type OIS3N_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS4` reader - Output Idle state 4"] pub type OIS4_R = crate::BitReader; #[doc = "Field `OIS4` writer - Output Idle state 4"] pub type OIS4_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; impl R { #[doc = "Bit 0 - Capture/compare preloaded control"] #[inline(always)] pub fn ccpc(&self) -> CCPC_R { CCPC_R::new((self.bits & 1) != 0) } #[doc = "Bit 2 - Capture/compare control update selection"] #[inline(always)] pub fn ccus(&self) -> CCUS_R { CCUS_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/compare DMA selection"] #[inline(always)] pub fn ccds(&self) -> CCDS_R { CCDS_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Master mode selection"] #[inline(always)] pub fn mms(&self) -> MMS_R { MMS_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - TI1 selection"] #[inline(always)] pub fn ti1s(&self) -> TI1S_R { TI1S_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Output Idle state 1"] #[inline(always)] pub fn ois1(&self) -> OIS1_R { OIS1_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Output Idle state 1"] #[inline(always)] pub fn ois1n(&self) -> OIS1N_R { OIS1N_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Output Idle state 2"] #[inline(always)] pub fn ois2(&self) -> OIS2_R { OIS2_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Output Idle state 2"] #[inline(always)] pub fn ois2n(&self) -> OIS2N_R { OIS2N_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Output Idle state 3"] #[inline(always)] pub fn ois3(&self) -> OIS3_R { OIS3_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Output Idle state 3"] #[inline(always)] pub fn ois3n(&self) -> OIS3N_R { OIS3N_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Output Idle state 4"] #[inline(always)] pub fn ois4(&self) -> OIS4_R { OIS4_R::new(((self.bits >> 14) & 1) != 0) } } impl W { #[doc = "Bit 0 - Capture/compare preloaded control"] #[inline(always)] #[must_use] pub fn ccpc(&mut self) -> CCPC_W<0> { CCPC_W::new(self) } #[doc = "Bit 2 - Capture/compare control update selection"] #[inline(always)] #[must_use] pub fn ccus(&mut self) -> CCUS_W<2> { CCUS_W::new(self) } #[doc = "Bit 3 - Capture/compare DMA selection"] #[inline(always)] #[must_use] pub fn ccds(&mut self) -> CCDS_W<3> { CCDS_W::new(self) } #[doc = "Bits 4:6 - Master mode selection"] #[inline(always)] #[must_use] pub fn mms(&mut self) -> MMS_W<4> { MMS_W::new(self) } #[doc = "Bit 7 - TI1 selection"] #[inline(always)] #[must_use] pub fn ti1s(&mut self) -> TI1S_W<7> { TI1S_W::new(self) } #[doc = "Bit 8 - Output Idle state 1"] #[inline(always)] #[must_use] pub fn ois1(&mut self) -> OIS1_W<8> { OIS1_W::new(self) } #[doc = "Bit 9 - Output Idle state 1"] #[inline(always)] #[must_use] pub fn ois1n(&mut self) -> OIS1N_W<9> { OIS1N_W::new(self) } #[doc = "Bit 10 - Output Idle state 2"] #[inline(always)] #[must_use] pub fn ois2(&mut self) -> OIS2_W<10> { OIS2_W::new(self) } #[doc = "Bit 11 - Output Idle state 2"] #[inline(always)] #[must_use] pub fn ois2n(&mut self) -> OIS2N_W<11> { OIS2N_W::new(self) } #[doc = "Bit 12 - Output Idle state 3"] #[inline(always)] #[must_use] pub fn ois3(&mut self) -> OIS3_W<12> { OIS3_W::new(self) } #[doc = "Bit 13 - Output Idle state 3"] #[inline(always)] #[must_use] pub fn ois3n(&mut self) -> OIS3N_W<13> { OIS3N_W::new(self) } #[doc = "Bit 14 - Output Idle state 4"] #[inline(always)] #[must_use] pub fn ois4(&mut self) -> OIS4_W<14> { OIS4_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SMCR (rw) register accessor: an alias for `Reg`"] pub type SMCR = crate::Reg; #[doc = "slave mode control register"] pub mod smcr { #[doc = "Register `SMCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SMCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SMS` reader - Slave mode selection"] pub type SMS_R = crate::FieldReader; #[doc = "Field `SMS` writer - Slave mode selection"] pub type SMS_W<'a, const O: u8> = crate::FieldWriter<'a, SMCR_SPEC, 3, O>; #[doc = "Field `OCCS` reader - OCREF clear selection bit"] pub type OCCS_R = crate::BitReader; #[doc = "Field `OCCS` writer - OCREF clear selection bit"] pub type OCCS_W<'a, const O: u8> = crate::BitWriter<'a, SMCR_SPEC, O>; #[doc = "Field `TS` reader - Trigger selection"] pub type TS_R = crate::FieldReader; #[doc = "Field `TS` writer - Trigger selection"] pub type TS_W<'a, const O: u8> = crate::FieldWriter<'a, SMCR_SPEC, 3, O>; #[doc = "Field `MSM` reader - Master/Slave mode"] pub type MSM_R = crate::BitReader; #[doc = "Field `MSM` writer - Master/Slave mode"] pub type MSM_W<'a, const O: u8> = crate::BitWriter<'a, SMCR_SPEC, O>; #[doc = "Field `ETF` reader - External trigger filter"] pub type ETF_R = crate::FieldReader; #[doc = "Field `ETF` writer - External trigger filter"] pub type ETF_W<'a, const O: u8> = crate::FieldWriter<'a, SMCR_SPEC, 4, O>; #[doc = "Field `ETPS` reader - External trigger prescaler"] pub type ETPS_R = crate::FieldReader; #[doc = "Field `ETPS` writer - External trigger prescaler"] pub type ETPS_W<'a, const O: u8> = crate::FieldWriter<'a, SMCR_SPEC, 2, O>; #[doc = "Field `ECE` reader - External clock enable"] pub type ECE_R = crate::BitReader; #[doc = "Field `ECE` writer - External clock enable"] pub type ECE_W<'a, const O: u8> = crate::BitWriter<'a, SMCR_SPEC, O>; #[doc = "Field `ETP` reader - External trigger polarity"] pub type ETP_R = crate::BitReader; #[doc = "Field `ETP` writer - External trigger polarity"] pub type ETP_W<'a, const O: u8> = crate::BitWriter<'a, SMCR_SPEC, O>; impl R { #[doc = "Bits 0:2 - Slave mode selection"] #[inline(always)] pub fn sms(&self) -> SMS_R { SMS_R::new((self.bits & 7) as u8) } #[doc = "Bit 3 - OCREF clear selection bit"] #[inline(always)] pub fn occs(&self) -> OCCS_R { OCCS_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Trigger selection"] #[inline(always)] pub fn ts(&self) -> TS_R { TS_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - Master/Slave mode"] #[inline(always)] pub fn msm(&self) -> MSM_R { MSM_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:11 - External trigger filter"] #[inline(always)] pub fn etf(&self) -> ETF_R { ETF_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:13 - External trigger prescaler"] #[inline(always)] pub fn etps(&self) -> ETPS_R { ETPS_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bit 14 - External clock enable"] #[inline(always)] pub fn ece(&self) -> ECE_R { ECE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - External trigger polarity"] #[inline(always)] pub fn etp(&self) -> ETP_R { ETP_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:2 - Slave mode selection"] #[inline(always)] #[must_use] pub fn sms(&mut self) -> SMS_W<0> { SMS_W::new(self) } #[doc = "Bit 3 - OCREF clear selection bit"] #[inline(always)] #[must_use] pub fn occs(&mut self) -> OCCS_W<3> { OCCS_W::new(self) } #[doc = "Bits 4:6 - Trigger selection"] #[inline(always)] #[must_use] pub fn ts(&mut self) -> TS_W<4> { TS_W::new(self) } #[doc = "Bit 7 - Master/Slave mode"] #[inline(always)] #[must_use] pub fn msm(&mut self) -> MSM_W<7> { MSM_W::new(self) } #[doc = "Bits 8:11 - External trigger filter"] #[inline(always)] #[must_use] pub fn etf(&mut self) -> ETF_W<8> { ETF_W::new(self) } #[doc = "Bits 12:13 - External trigger prescaler"] #[inline(always)] #[must_use] pub fn etps(&mut self) -> ETPS_W<12> { ETPS_W::new(self) } #[doc = "Bit 14 - External clock enable"] #[inline(always)] #[must_use] pub fn ece(&mut self) -> ECE_W<14> { ECE_W::new(self) } #[doc = "Bit 15 - External trigger polarity"] #[inline(always)] #[must_use] pub fn etp(&mut self) -> ETP_W<15> { ETP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "slave mode control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smcr](index.html) module"] pub struct SMCR_SPEC; impl crate::RegisterSpec for SMCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [smcr::R](R) reader structure"] impl crate::Readable for SMCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [smcr::W](W) writer structure"] impl crate::Writable for SMCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SMCR to value 0"] impl crate::Resettable for SMCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DIER (rw) register accessor: an alias for `Reg`"] pub type DIER = crate::Reg; #[doc = "DMA/Interrupt enable register"] pub mod dier { #[doc = "Register `DIER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DIER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIE` reader - Update interrupt enable"] pub type UIE_R = crate::BitReader; #[doc = "Field `UIE` writer - Update interrupt enable"] pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable"] pub type CC1IE_R = crate::BitReader; #[doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable"] pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC2IE` reader - Capture/Compare 2 interrupt enable"] pub type CC2IE_R = crate::BitReader; #[doc = "Field `CC2IE` writer - Capture/Compare 2 interrupt enable"] pub type CC2IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC3IE` reader - Capture/Compare 3 interrupt enable"] pub type CC3IE_R = crate::BitReader; #[doc = "Field `CC3IE` writer - Capture/Compare 3 interrupt enable"] pub type CC3IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC4IE` reader - Capture/Compare 4 interrupt enable"] pub type CC4IE_R = crate::BitReader; #[doc = "Field `CC4IE` writer - Capture/Compare 4 interrupt enable"] pub type CC4IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `COMIE` reader - COM interrupt enable"] pub type COMIE_R = crate::BitReader; #[doc = "Field `COMIE` writer - COM interrupt enable"] pub type COMIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `TIE` reader - Trigger interrupt enable"] pub type TIE_R = crate::BitReader; #[doc = "Field `TIE` writer - Trigger interrupt enable"] pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `BIE` reader - Break interrupt enable"] pub type BIE_R = crate::BitReader; #[doc = "Field `BIE` writer - Break interrupt enable"] pub type BIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `UDE` reader - Update DMA request enable"] pub type UDE_R = crate::BitReader; #[doc = "Field `UDE` writer - Update DMA request enable"] pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1DE` reader - Capture/Compare 1 DMA request enable"] pub type CC1DE_R = crate::BitReader; #[doc = "Field `CC1DE` writer - Capture/Compare 1 DMA request enable"] pub type CC1DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC2DE` reader - Capture/Compare 2 DMA request enable"] pub type CC2DE_R = crate::BitReader; #[doc = "Field `CC2DE` writer - Capture/Compare 2 DMA request enable"] pub type CC2DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC3DE` reader - Capture/Compare 3 DMA request enable"] pub type CC3DE_R = crate::BitReader; #[doc = "Field `CC3DE` writer - Capture/Compare 3 DMA request enable"] pub type CC3DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC4DE` reader - Capture/Compare 4 DMA request enable"] pub type CC4DE_R = crate::BitReader; #[doc = "Field `CC4DE` writer - Capture/Compare 4 DMA request enable"] pub type CC4DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `COMDE` reader - COM DMA request enable"] pub type COMDE_R = crate::BitReader; #[doc = "Field `COMDE` writer - COM DMA request enable"] pub type COMDE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `TDE` reader - Trigger DMA request enable"] pub type TDE_R = crate::BitReader; #[doc = "Field `TDE` writer - Trigger DMA request enable"] pub type TDE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] pub fn uie(&self) -> UIE_R { UIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 interrupt enable"] #[inline(always)] pub fn cc1ie(&self) -> CC1IE_R { CC1IE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Capture/Compare 2 interrupt enable"] #[inline(always)] pub fn cc2ie(&self) -> CC2IE_R { CC2IE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 3 interrupt enable"] #[inline(always)] pub fn cc3ie(&self) -> CC3IE_R { CC3IE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Capture/Compare 4 interrupt enable"] #[inline(always)] pub fn cc4ie(&self) -> CC4IE_R { CC4IE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - COM interrupt enable"] #[inline(always)] pub fn comie(&self) -> COMIE_R { COMIE_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Trigger interrupt enable"] #[inline(always)] pub fn tie(&self) -> TIE_R { TIE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Break interrupt enable"] #[inline(always)] pub fn bie(&self) -> BIE_R { BIE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Update DMA request enable"] #[inline(always)] pub fn ude(&self) -> UDE_R { UDE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Capture/Compare 1 DMA request enable"] #[inline(always)] pub fn cc1de(&self) -> CC1DE_R { CC1DE_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Capture/Compare 2 DMA request enable"] #[inline(always)] pub fn cc2de(&self) -> CC2DE_R { CC2DE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Capture/Compare 3 DMA request enable"] #[inline(always)] pub fn cc3de(&self) -> CC3DE_R { CC3DE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Capture/Compare 4 DMA request enable"] #[inline(always)] pub fn cc4de(&self) -> CC4DE_R { CC4DE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - COM DMA request enable"] #[inline(always)] pub fn comde(&self) -> COMDE_R { COMDE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Trigger DMA request enable"] #[inline(always)] pub fn tde(&self) -> TDE_R { TDE_R::new(((self.bits >> 14) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] #[must_use] pub fn uie(&mut self) -> UIE_W<0> { UIE_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 interrupt enable"] #[inline(always)] #[must_use] pub fn cc1ie(&mut self) -> CC1IE_W<1> { CC1IE_W::new(self) } #[doc = "Bit 2 - Capture/Compare 2 interrupt enable"] #[inline(always)] #[must_use] pub fn cc2ie(&mut self) -> CC2IE_W<2> { CC2IE_W::new(self) } #[doc = "Bit 3 - Capture/Compare 3 interrupt enable"] #[inline(always)] #[must_use] pub fn cc3ie(&mut self) -> CC3IE_W<3> { CC3IE_W::new(self) } #[doc = "Bit 4 - Capture/Compare 4 interrupt enable"] #[inline(always)] #[must_use] pub fn cc4ie(&mut self) -> CC4IE_W<4> { CC4IE_W::new(self) } #[doc = "Bit 5 - COM interrupt enable"] #[inline(always)] #[must_use] pub fn comie(&mut self) -> COMIE_W<5> { COMIE_W::new(self) } #[doc = "Bit 6 - Trigger interrupt enable"] #[inline(always)] #[must_use] pub fn tie(&mut self) -> TIE_W<6> { TIE_W::new(self) } #[doc = "Bit 7 - Break interrupt enable"] #[inline(always)] #[must_use] pub fn bie(&mut self) -> BIE_W<7> { BIE_W::new(self) } #[doc = "Bit 8 - Update DMA request enable"] #[inline(always)] #[must_use] pub fn ude(&mut self) -> UDE_W<8> { UDE_W::new(self) } #[doc = "Bit 9 - Capture/Compare 1 DMA request enable"] #[inline(always)] #[must_use] pub fn cc1de(&mut self) -> CC1DE_W<9> { CC1DE_W::new(self) } #[doc = "Bit 10 - Capture/Compare 2 DMA request enable"] #[inline(always)] #[must_use] pub fn cc2de(&mut self) -> CC2DE_W<10> { CC2DE_W::new(self) } #[doc = "Bit 11 - Capture/Compare 3 DMA request enable"] #[inline(always)] #[must_use] pub fn cc3de(&mut self) -> CC3DE_W<11> { CC3DE_W::new(self) } #[doc = "Bit 12 - Capture/Compare 4 DMA request enable"] #[inline(always)] #[must_use] pub fn cc4de(&mut self) -> CC4DE_W<12> { CC4DE_W::new(self) } #[doc = "Bit 13 - COM DMA request enable"] #[inline(always)] #[must_use] pub fn comde(&mut self) -> COMDE_W<13> { COMDE_W::new(self) } #[doc = "Bit 14 - Trigger DMA request enable"] #[inline(always)] #[must_use] pub fn tde(&mut self) -> TDE_W<14> { TDE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA/Interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"] pub struct DIER_SPEC; impl crate::RegisterSpec for DIER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dier::R](R) reader structure"] impl crate::Readable for DIER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"] impl crate::Writable for DIER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DIER to value 0"] impl crate::Resettable for DIER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIF` reader - Update interrupt flag"] pub type UIF_R = crate::BitReader; #[doc = "Field `UIF` writer - Update interrupt flag"] pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1IF` reader - Capture/compare 1 interrupt flag"] pub type CC1IF_R = crate::BitReader; #[doc = "Field `CC1IF` writer - Capture/compare 1 interrupt flag"] pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC2IF` reader - Capture/Compare 2 interrupt flag"] pub type CC2IF_R = crate::BitReader; #[doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag"] pub type CC2IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC3IF` reader - Capture/Compare 3 interrupt flag"] pub type CC3IF_R = crate::BitReader; #[doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag"] pub type CC3IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC4IF` reader - Capture/Compare 4 interrupt flag"] pub type CC4IF_R = crate::BitReader; #[doc = "Field `CC4IF` writer - Capture/Compare 4 interrupt flag"] pub type CC4IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `COMIF` reader - COM interrupt flag"] pub type COMIF_R = crate::BitReader; #[doc = "Field `COMIF` writer - COM interrupt flag"] pub type COMIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `TIF` reader - Trigger interrupt flag"] pub type TIF_R = crate::BitReader; #[doc = "Field `TIF` writer - Trigger interrupt flag"] pub type TIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `BIF` reader - Break interrupt flag"] pub type BIF_R = crate::BitReader; #[doc = "Field `BIF` writer - Break interrupt flag"] pub type BIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1OF` reader - Capture/Compare 1 overcapture flag"] pub type CC1OF_R = crate::BitReader; #[doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag"] pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC2OF` reader - Capture/compare 2 overcapture flag"] pub type CC2OF_R = crate::BitReader; #[doc = "Field `CC2OF` writer - Capture/compare 2 overcapture flag"] pub type CC2OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC3OF` reader - Capture/Compare 3 overcapture flag"] pub type CC3OF_R = crate::BitReader; #[doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag"] pub type CC3OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC4OF` reader - Capture/Compare 4 overcapture flag"] pub type CC4OF_R = crate::BitReader; #[doc = "Field `CC4OF` writer - Capture/Compare 4 overcapture flag"] pub type CC4OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] pub fn uif(&self) -> UIF_R { UIF_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/compare 1 interrupt flag"] #[inline(always)] pub fn cc1if(&self) -> CC1IF_R { CC1IF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Capture/Compare 2 interrupt flag"] #[inline(always)] pub fn cc2if(&self) -> CC2IF_R { CC2IF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 3 interrupt flag"] #[inline(always)] pub fn cc3if(&self) -> CC3IF_R { CC3IF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Capture/Compare 4 interrupt flag"] #[inline(always)] pub fn cc4if(&self) -> CC4IF_R { CC4IF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - COM interrupt flag"] #[inline(always)] pub fn comif(&self) -> COMIF_R { COMIF_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Trigger interrupt flag"] #[inline(always)] pub fn tif(&self) -> TIF_R { TIF_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Break interrupt flag"] #[inline(always)] pub fn bif(&self) -> BIF_R { BIF_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 9 - Capture/Compare 1 overcapture flag"] #[inline(always)] pub fn cc1of(&self) -> CC1OF_R { CC1OF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Capture/compare 2 overcapture flag"] #[inline(always)] pub fn cc2of(&self) -> CC2OF_R { CC2OF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Capture/Compare 3 overcapture flag"] #[inline(always)] pub fn cc3of(&self) -> CC3OF_R { CC3OF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Capture/Compare 4 overcapture flag"] #[inline(always)] pub fn cc4of(&self) -> CC4OF_R { CC4OF_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] #[must_use] pub fn uif(&mut self) -> UIF_W<0> { UIF_W::new(self) } #[doc = "Bit 1 - Capture/compare 1 interrupt flag"] #[inline(always)] #[must_use] pub fn cc1if(&mut self) -> CC1IF_W<1> { CC1IF_W::new(self) } #[doc = "Bit 2 - Capture/Compare 2 interrupt flag"] #[inline(always)] #[must_use] pub fn cc2if(&mut self) -> CC2IF_W<2> { CC2IF_W::new(self) } #[doc = "Bit 3 - Capture/Compare 3 interrupt flag"] #[inline(always)] #[must_use] pub fn cc3if(&mut self) -> CC3IF_W<3> { CC3IF_W::new(self) } #[doc = "Bit 4 - Capture/Compare 4 interrupt flag"] #[inline(always)] #[must_use] pub fn cc4if(&mut self) -> CC4IF_W<4> { CC4IF_W::new(self) } #[doc = "Bit 5 - COM interrupt flag"] #[inline(always)] #[must_use] pub fn comif(&mut self) -> COMIF_W<5> { COMIF_W::new(self) } #[doc = "Bit 6 - Trigger interrupt flag"] #[inline(always)] #[must_use] pub fn tif(&mut self) -> TIF_W<6> { TIF_W::new(self) } #[doc = "Bit 7 - Break interrupt flag"] #[inline(always)] #[must_use] pub fn bif(&mut self) -> BIF_W<7> { BIF_W::new(self) } #[doc = "Bit 9 - Capture/Compare 1 overcapture flag"] #[inline(always)] #[must_use] pub fn cc1of(&mut self) -> CC1OF_W<9> { CC1OF_W::new(self) } #[doc = "Bit 10 - Capture/compare 2 overcapture flag"] #[inline(always)] #[must_use] pub fn cc2of(&mut self) -> CC2OF_W<10> { CC2OF_W::new(self) } #[doc = "Bit 11 - Capture/Compare 3 overcapture flag"] #[inline(always)] #[must_use] pub fn cc3of(&mut self) -> CC3OF_W<11> { CC3OF_W::new(self) } #[doc = "Bit 12 - Capture/Compare 4 overcapture flag"] #[inline(always)] #[must_use] pub fn cc4of(&mut self) -> CC4OF_W<12> { CC4OF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EGR (w) register accessor: an alias for `Reg`"] pub type EGR = crate::Reg; #[doc = "event generation register"] pub mod egr { #[doc = "Register `EGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UG` writer - Update generation"] pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC1G` writer - Capture/compare 1 generation"] pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC2G` writer - Capture/compare 2 generation"] pub type CC2G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC3G` writer - Capture/compare 3 generation"] pub type CC3G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC4G` writer - Capture/compare 4 generation"] pub type CC4G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `COMG` writer - Capture/Compare control update generation"] pub type COMG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `TG` writer - Trigger generation"] pub type TG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `BG` writer - Break generation"] pub type BG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; impl W { #[doc = "Bit 0 - Update generation"] #[inline(always)] #[must_use] pub fn ug(&mut self) -> UG_W<0> { UG_W::new(self) } #[doc = "Bit 1 - Capture/compare 1 generation"] #[inline(always)] #[must_use] pub fn cc1g(&mut self) -> CC1G_W<1> { CC1G_W::new(self) } #[doc = "Bit 2 - Capture/compare 2 generation"] #[inline(always)] #[must_use] pub fn cc2g(&mut self) -> CC2G_W<2> { CC2G_W::new(self) } #[doc = "Bit 3 - Capture/compare 3 generation"] #[inline(always)] #[must_use] pub fn cc3g(&mut self) -> CC3G_W<3> { CC3G_W::new(self) } #[doc = "Bit 4 - Capture/compare 4 generation"] #[inline(always)] #[must_use] pub fn cc4g(&mut self) -> CC4G_W<4> { CC4G_W::new(self) } #[doc = "Bit 5 - Capture/Compare control update generation"] #[inline(always)] #[must_use] pub fn comg(&mut self) -> COMG_W<5> { COMG_W::new(self) } #[doc = "Bit 6 - Trigger generation"] #[inline(always)] #[must_use] pub fn tg(&mut self) -> TG_W<6> { TG_W::new(self) } #[doc = "Bit 7 - Break generation"] #[inline(always)] #[must_use] pub fn bg(&mut self) -> BG_W<7> { BG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"] pub struct EGR_SPEC; impl crate::RegisterSpec for EGR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"] impl crate::Writable for EGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EGR to value 0"] impl crate::Resettable for EGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg`"] pub type CCMR1_OUTPUT = crate::Reg; #[doc = "capture/compare mode register (output mode)"] pub mod ccmr1_output { #[doc = "Register `CCMR1_Output` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Output` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC1FE` reader - Output Compare 1 fast enable"] pub type OC1FE_R = crate::BitReader; #[doc = "Field `OC1FE` writer - Output Compare 1 fast enable"] pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1PE` reader - Output Compare 1 preload enable"] pub type OC1PE_R = crate::BitReader; #[doc = "Field `OC1PE` writer - Output Compare 1 preload enable"] pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1M` reader - Output Compare 1 mode"] pub type OC1M_R = crate::FieldReader; #[doc = "Field `OC1M` writer - Output Compare 1 mode"] pub type OC1M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC1CE` reader - Output Compare 1 clear enable"] pub type OC1CE_R = crate::BitReader; #[doc = "Field `OC1CE` writer - Output Compare 1 clear enable"] pub type OC1CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `CC2S` reader - Capture/Compare 2 selection"] pub type CC2S_R = crate::FieldReader; #[doc = "Field `CC2S` writer - Capture/Compare 2 selection"] pub type CC2S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC2FE` reader - Output Compare 2 fast enable"] pub type OC2FE_R = crate::BitReader; #[doc = "Field `OC2FE` writer - Output Compare 2 fast enable"] pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC2PE` reader - Output Compare 2 preload enable"] pub type OC2PE_R = crate::BitReader; #[doc = "Field `OC2PE` writer - Output Compare 2 preload enable"] pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC2M` reader - Output Compare 2 mode"] pub type OC2M_R = crate::FieldReader; #[doc = "Field `OC2M` writer - Output Compare 2 mode"] pub type OC2M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC2CE` reader - Output Compare 2 clear enable"] pub type OC2CE_R = crate::BitReader; #[doc = "Field `OC2CE` writer - Output Compare 2 clear enable"] pub type OC2CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Output Compare 1 fast enable"] #[inline(always)] pub fn oc1fe(&self) -> OC1FE_R { OC1FE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] pub fn oc1pe(&self) -> OC1PE_R { OC1PE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] pub fn oc1m(&self) -> OC1M_R { OC1M_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - Output Compare 1 clear enable"] #[inline(always)] pub fn oc1ce(&self) -> OC1CE_R { OC1CE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Capture/Compare 2 selection"] #[inline(always)] pub fn cc2s(&self) -> CC2S_R { CC2S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 10 - Output Compare 2 fast enable"] #[inline(always)] pub fn oc2fe(&self) -> OC2FE_R { OC2FE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Output Compare 2 preload enable"] #[inline(always)] pub fn oc2pe(&self) -> OC2PE_R { OC2PE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bits 12:14 - Output Compare 2 mode"] #[inline(always)] pub fn oc2m(&self) -> OC2M_R { OC2M_R::new(((self.bits >> 12) & 7) as u8) } #[doc = "Bit 15 - Output Compare 2 clear enable"] #[inline(always)] pub fn oc2ce(&self) -> OC2CE_R { OC2CE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bit 2 - Output Compare 1 fast enable"] #[inline(always)] #[must_use] pub fn oc1fe(&mut self) -> OC1FE_W<2> { OC1FE_W::new(self) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] #[must_use] pub fn oc1pe(&mut self) -> OC1PE_W<3> { OC1PE_W::new(self) } #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] #[must_use] pub fn oc1m(&mut self) -> OC1M_W<4> { OC1M_W::new(self) } #[doc = "Bit 7 - Output Compare 1 clear enable"] #[inline(always)] #[must_use] pub fn oc1ce(&mut self) -> OC1CE_W<7> { OC1CE_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 2 selection"] #[inline(always)] #[must_use] pub fn cc2s(&mut self) -> CC2S_W<8> { CC2S_W::new(self) } #[doc = "Bit 10 - Output Compare 2 fast enable"] #[inline(always)] #[must_use] pub fn oc2fe(&mut self) -> OC2FE_W<10> { OC2FE_W::new(self) } #[doc = "Bit 11 - Output Compare 2 preload enable"] #[inline(always)] #[must_use] pub fn oc2pe(&mut self) -> OC2PE_W<11> { OC2PE_W::new(self) } #[doc = "Bits 12:14 - Output Compare 2 mode"] #[inline(always)] #[must_use] pub fn oc2m(&mut self) -> OC2M_W<12> { OC2M_W::new(self) } #[doc = "Bit 15 - Output Compare 2 clear enable"] #[inline(always)] #[must_use] pub fn oc2ce(&mut self) -> OC2CE_W<15> { OC2CE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"] pub struct CCMR1_OUTPUT_SPEC; impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"] impl crate::Readable for CCMR1_OUTPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"] impl crate::Writable for CCMR1_OUTPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Output to value 0"] impl crate::Resettable for CCMR1_OUTPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg`"] pub type CCMR1_INPUT = crate::Reg; #[doc = "capture/compare mode register 1 (input mode)"] pub mod ccmr1_input { #[doc = "Register `CCMR1_Input` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Input` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `ICPSC` reader - Input capture 1 prescaler"] pub type ICPSC_R = crate::FieldReader; #[doc = "Field `ICPSC` writer - Input capture 1 prescaler"] pub type ICPSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1F` reader - Input capture 1 filter"] pub type IC1F_R = crate::FieldReader; #[doc = "Field `IC1F` writer - Input capture 1 filter"] pub type IC1F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 4, O>; #[doc = "Field `CC2S` reader - Capture/Compare 2 selection"] pub type CC2S_R = crate::FieldReader; #[doc = "Field `CC2S` writer - Capture/Compare 2 selection"] pub type CC2S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC2PSC` reader - Input capture 2 prescaler"] pub type IC2PSC_R = crate::FieldReader; #[doc = "Field `IC2PSC` writer - Input capture 2 prescaler"] pub type IC2PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC2F` reader - Input capture 2 filter"] pub type IC2F_R = crate::FieldReader; #[doc = "Field `IC2F` writer - Input capture 2 filter"] pub type IC2F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 4, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] pub fn icpsc(&self) -> ICPSC_R { ICPSC_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] pub fn ic1f(&self) -> IC1F_R { IC1F_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:9 - Capture/Compare 2 selection"] #[inline(always)] pub fn cc2s(&self) -> CC2S_R { CC2S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Input capture 2 prescaler"] #[inline(always)] pub fn ic2psc(&self) -> IC2PSC_R { IC2PSC_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:15 - Input capture 2 filter"] #[inline(always)] pub fn ic2f(&self) -> IC2F_R { IC2F_R::new(((self.bits >> 12) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] #[must_use] pub fn icpsc(&mut self) -> ICPSC_W<2> { ICPSC_W::new(self) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] #[must_use] pub fn ic1f(&mut self) -> IC1F_W<4> { IC1F_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 2 selection"] #[inline(always)] #[must_use] pub fn cc2s(&mut self) -> CC2S_W<8> { CC2S_W::new(self) } #[doc = "Bits 10:11 - Input capture 2 prescaler"] #[inline(always)] #[must_use] pub fn ic2psc(&mut self) -> IC2PSC_W<10> { IC2PSC_W::new(self) } #[doc = "Bits 12:15 - Input capture 2 filter"] #[inline(always)] #[must_use] pub fn ic2f(&mut self) -> IC2F_W<12> { IC2F_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 1 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"] pub struct CCMR1_INPUT_SPEC; impl crate::RegisterSpec for CCMR1_INPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"] impl crate::Readable for CCMR1_INPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"] impl crate::Writable for CCMR1_INPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Input to value 0"] impl crate::Resettable for CCMR1_INPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR2_Output (rw) register accessor: an alias for `Reg`"] pub type CCMR2_OUTPUT = crate::Reg; #[doc = "capture/compare mode register (output mode)"] pub mod ccmr2_output { #[doc = "Register `CCMR2_Output` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR2_Output` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC3S` reader - Capture/Compare 3 selection"] pub type CC3S_R = crate::FieldReader; #[doc = "Field `CC3S` writer - Capture/Compare 3 selection"] pub type CC3S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC3FE` reader - Output compare 3 fast enable"] pub type OC3FE_R = crate::BitReader; #[doc = "Field `OC3FE` writer - Output compare 3 fast enable"] pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC3PE` reader - Output compare 3 preload enable"] pub type OC3PE_R = crate::BitReader; #[doc = "Field `OC3PE` writer - Output compare 3 preload enable"] pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC3M` reader - Output compare 3 mode"] pub type OC3M_R = crate::FieldReader; #[doc = "Field `OC3M` writer - Output compare 3 mode"] pub type OC3M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC3CE` reader - Output compare 3 clear enable"] pub type OC3CE_R = crate::BitReader; #[doc = "Field `OC3CE` writer - Output compare 3 clear enable"] pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `CC4S` reader - Capture/Compare 4 selection"] pub type CC4S_R = crate::FieldReader; #[doc = "Field `CC4S` writer - Capture/Compare 4 selection"] pub type CC4S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC4FE` reader - Output compare 4 fast enable"] pub type OC4FE_R = crate::BitReader; #[doc = "Field `OC4FE` writer - Output compare 4 fast enable"] pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC4PE` reader - Output compare 4 preload enable"] pub type OC4PE_R = crate::BitReader; #[doc = "Field `OC4PE` writer - Output compare 4 preload enable"] pub type OC4PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC4M` reader - Output compare 4 mode"] pub type OC4M_R = crate::FieldReader; #[doc = "Field `OC4M` writer - Output compare 4 mode"] pub type OC4M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC4CE` reader - Output compare 4 clear enable"] pub type OC4CE_R = crate::BitReader; #[doc = "Field `OC4CE` writer - Output compare 4 clear enable"] pub type OC4CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 3 selection"] #[inline(always)] pub fn cc3s(&self) -> CC3S_R { CC3S_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Output compare 3 fast enable"] #[inline(always)] pub fn oc3fe(&self) -> OC3FE_R { OC3FE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Output compare 3 preload enable"] #[inline(always)] pub fn oc3pe(&self) -> OC3PE_R { OC3PE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Output compare 3 mode"] #[inline(always)] pub fn oc3m(&self) -> OC3M_R { OC3M_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - Output compare 3 clear enable"] #[inline(always)] pub fn oc3ce(&self) -> OC3CE_R { OC3CE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] pub fn cc4s(&self) -> CC4S_R { CC4S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 10 - Output compare 4 fast enable"] #[inline(always)] pub fn oc4fe(&self) -> OC4FE_R { OC4FE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Output compare 4 preload enable"] #[inline(always)] pub fn oc4pe(&self) -> OC4PE_R { OC4PE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bits 12:14 - Output compare 4 mode"] #[inline(always)] pub fn oc4m(&self) -> OC4M_R { OC4M_R::new(((self.bits >> 12) & 7) as u8) } #[doc = "Bit 15 - Output compare 4 clear enable"] #[inline(always)] pub fn oc4ce(&self) -> OC4CE_R { OC4CE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 3 selection"] #[inline(always)] #[must_use] pub fn cc3s(&mut self) -> CC3S_W<0> { CC3S_W::new(self) } #[doc = "Bit 2 - Output compare 3 fast enable"] #[inline(always)] #[must_use] pub fn oc3fe(&mut self) -> OC3FE_W<2> { OC3FE_W::new(self) } #[doc = "Bit 3 - Output compare 3 preload enable"] #[inline(always)] #[must_use] pub fn oc3pe(&mut self) -> OC3PE_W<3> { OC3PE_W::new(self) } #[doc = "Bits 4:6 - Output compare 3 mode"] #[inline(always)] #[must_use] pub fn oc3m(&mut self) -> OC3M_W<4> { OC3M_W::new(self) } #[doc = "Bit 7 - Output compare 3 clear enable"] #[inline(always)] #[must_use] pub fn oc3ce(&mut self) -> OC3CE_W<7> { OC3CE_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] #[must_use] pub fn cc4s(&mut self) -> CC4S_W<8> { CC4S_W::new(self) } #[doc = "Bit 10 - Output compare 4 fast enable"] #[inline(always)] #[must_use] pub fn oc4fe(&mut self) -> OC4FE_W<10> { OC4FE_W::new(self) } #[doc = "Bit 11 - Output compare 4 preload enable"] #[inline(always)] #[must_use] pub fn oc4pe(&mut self) -> OC4PE_W<11> { OC4PE_W::new(self) } #[doc = "Bits 12:14 - Output compare 4 mode"] #[inline(always)] #[must_use] pub fn oc4m(&mut self) -> OC4M_W<12> { OC4M_W::new(self) } #[doc = "Bit 15 - Output compare 4 clear enable"] #[inline(always)] #[must_use] pub fn oc4ce(&mut self) -> OC4CE_W<15> { OC4CE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_output](index.html) module"] pub struct CCMR2_OUTPUT_SPEC; impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr2_output::R](R) reader structure"] impl crate::Readable for CCMR2_OUTPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure"] impl crate::Writable for CCMR2_OUTPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR2_Output to value 0"] impl crate::Resettable for CCMR2_OUTPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR2_Input (rw) register accessor: an alias for `Reg`"] pub type CCMR2_INPUT = crate::Reg; #[doc = "capture/compare mode register 2 (input mode)"] pub mod ccmr2_input { #[doc = "Register `CCMR2_Input` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR2_Input` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC3S` reader - Capture/compare 3 selection"] pub type CC3S_R = crate::FieldReader; #[doc = "Field `CC3S` writer - Capture/compare 3 selection"] pub type CC3S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC3PSC` reader - Input capture 3 prescaler"] pub type IC3PSC_R = crate::FieldReader; #[doc = "Field `IC3PSC` writer - Input capture 3 prescaler"] pub type IC3PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC3F` reader - Input capture 3 filter"] pub type IC3F_R = crate::FieldReader; #[doc = "Field `IC3F` writer - Input capture 3 filter"] pub type IC3F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 4, O>; #[doc = "Field `CC4S` reader - Capture/Compare 4 selection"] pub type CC4S_R = crate::FieldReader; #[doc = "Field `CC4S` writer - Capture/Compare 4 selection"] pub type CC4S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC4PSC` reader - Input capture 4 prescaler"] pub type IC4PSC_R = crate::FieldReader; #[doc = "Field `IC4PSC` writer - Input capture 4 prescaler"] pub type IC4PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC4F` reader - Input capture 4 filter"] pub type IC4F_R = crate::FieldReader; #[doc = "Field `IC4F` writer - Input capture 4 filter"] pub type IC4F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 4, O>; impl R { #[doc = "Bits 0:1 - Capture/compare 3 selection"] #[inline(always)] pub fn cc3s(&self) -> CC3S_R { CC3S_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Input capture 3 prescaler"] #[inline(always)] pub fn ic3psc(&self) -> IC3PSC_R { IC3PSC_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:7 - Input capture 3 filter"] #[inline(always)] pub fn ic3f(&self) -> IC3F_R { IC3F_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] pub fn cc4s(&self) -> CC4S_R { CC4S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Input capture 4 prescaler"] #[inline(always)] pub fn ic4psc(&self) -> IC4PSC_R { IC4PSC_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:15 - Input capture 4 filter"] #[inline(always)] pub fn ic4f(&self) -> IC4F_R { IC4F_R::new(((self.bits >> 12) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/compare 3 selection"] #[inline(always)] #[must_use] pub fn cc3s(&mut self) -> CC3S_W<0> { CC3S_W::new(self) } #[doc = "Bits 2:3 - Input capture 3 prescaler"] #[inline(always)] #[must_use] pub fn ic3psc(&mut self) -> IC3PSC_W<2> { IC3PSC_W::new(self) } #[doc = "Bits 4:7 - Input capture 3 filter"] #[inline(always)] #[must_use] pub fn ic3f(&mut self) -> IC3F_W<4> { IC3F_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] #[must_use] pub fn cc4s(&mut self) -> CC4S_W<8> { CC4S_W::new(self) } #[doc = "Bits 10:11 - Input capture 4 prescaler"] #[inline(always)] #[must_use] pub fn ic4psc(&mut self) -> IC4PSC_W<10> { IC4PSC_W::new(self) } #[doc = "Bits 12:15 - Input capture 4 filter"] #[inline(always)] #[must_use] pub fn ic4f(&mut self) -> IC4F_W<12> { IC4F_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 2 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_input](index.html) module"] pub struct CCMR2_INPUT_SPEC; impl crate::RegisterSpec for CCMR2_INPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr2_input::R](R) reader structure"] impl crate::Readable for CCMR2_INPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr2_input::W](W) writer structure"] impl crate::Writable for CCMR2_INPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR2_Input to value 0"] impl crate::Resettable for CCMR2_INPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCER (rw) register accessor: an alias for `Reg`"] pub type CCER = crate::Reg; #[doc = "capture/compare enable register"] pub mod ccer { #[doc = "Register `CCER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1E` reader - Capture/Compare 1 output enable"] pub type CC1E_R = crate::BitReader; #[doc = "Field `CC1E` writer - Capture/Compare 1 output enable"] pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity"] pub type CC1P_R = crate::BitReader; #[doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity"] pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1NE` reader - Capture/Compare 1 complementary output enable"] pub type CC1NE_R = crate::BitReader; #[doc = "Field `CC1NE` writer - Capture/Compare 1 complementary output enable"] pub type CC1NE_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1NP` reader - Capture/Compare 1 output Polarity"] pub type CC1NP_R = crate::BitReader; #[doc = "Field `CC1NP` writer - Capture/Compare 1 output Polarity"] pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2E` reader - Capture/Compare 2 output enable"] pub type CC2E_R = crate::BitReader; #[doc = "Field `CC2E` writer - Capture/Compare 2 output enable"] pub type CC2E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2P` reader - Capture/Compare 2 output Polarity"] pub type CC2P_R = crate::BitReader; #[doc = "Field `CC2P` writer - Capture/Compare 2 output Polarity"] pub type CC2P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2NE` reader - Capture/Compare 2 complementary output enable"] pub type CC2NE_R = crate::BitReader; #[doc = "Field `CC2NE` writer - Capture/Compare 2 complementary output enable"] pub type CC2NE_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2NP` reader - Capture/Compare 2 output Polarity"] pub type CC2NP_R = crate::BitReader; #[doc = "Field `CC2NP` writer - Capture/Compare 2 output Polarity"] pub type CC2NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3E` reader - Capture/Compare 3 output enable"] pub type CC3E_R = crate::BitReader; #[doc = "Field `CC3E` writer - Capture/Compare 3 output enable"] pub type CC3E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3P` reader - Capture/Compare 3 output Polarity"] pub type CC3P_R = crate::BitReader; #[doc = "Field `CC3P` writer - Capture/Compare 3 output Polarity"] pub type CC3P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3NE` reader - Capture/Compare 3 complementary output enable"] pub type CC3NE_R = crate::BitReader; #[doc = "Field `CC3NE` writer - Capture/Compare 3 complementary output enable"] pub type CC3NE_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3NP` reader - Capture/Compare 3 output Polarity"] pub type CC3NP_R = crate::BitReader; #[doc = "Field `CC3NP` writer - Capture/Compare 3 output Polarity"] pub type CC3NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC4E` reader - Capture/Compare 4 output enable"] pub type CC4E_R = crate::BitReader; #[doc = "Field `CC4E` writer - Capture/Compare 4 output enable"] pub type CC4E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC4P` reader - Capture/Compare 3 output Polarity"] pub type CC4P_R = crate::BitReader; #[doc = "Field `CC4P` writer - Capture/Compare 3 output Polarity"] pub type CC4P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; impl R { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] pub fn cc1e(&self) -> CC1E_R { CC1E_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1p(&self) -> CC1P_R { CC1P_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Capture/Compare 1 complementary output enable"] #[inline(always)] pub fn cc1ne(&self) -> CC1NE_R { CC1NE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1np(&self) -> CC1NP_R { CC1NP_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Capture/Compare 2 output enable"] #[inline(always)] pub fn cc2e(&self) -> CC2E_R { CC2E_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Capture/Compare 2 output Polarity"] #[inline(always)] pub fn cc2p(&self) -> CC2P_R { CC2P_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Capture/Compare 2 complementary output enable"] #[inline(always)] pub fn cc2ne(&self) -> CC2NE_R { CC2NE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Capture/Compare 2 output Polarity"] #[inline(always)] pub fn cc2np(&self) -> CC2NP_R { CC2NP_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Capture/Compare 3 output enable"] #[inline(always)] pub fn cc3e(&self) -> CC3E_R { CC3E_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Capture/Compare 3 output Polarity"] #[inline(always)] pub fn cc3p(&self) -> CC3P_R { CC3P_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Capture/Compare 3 complementary output enable"] #[inline(always)] pub fn cc3ne(&self) -> CC3NE_R { CC3NE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Capture/Compare 3 output Polarity"] #[inline(always)] pub fn cc3np(&self) -> CC3NP_R { CC3NP_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Capture/Compare 4 output enable"] #[inline(always)] pub fn cc4e(&self) -> CC4E_R { CC4E_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Capture/Compare 3 output Polarity"] #[inline(always)] pub fn cc4p(&self) -> CC4P_R { CC4P_R::new(((self.bits >> 13) & 1) != 0) } } impl W { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] #[must_use] pub fn cc1e(&mut self) -> CC1E_W<0> { CC1E_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1p(&mut self) -> CC1P_W<1> { CC1P_W::new(self) } #[doc = "Bit 2 - Capture/Compare 1 complementary output enable"] #[inline(always)] #[must_use] pub fn cc1ne(&mut self) -> CC1NE_W<2> { CC1NE_W::new(self) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1np(&mut self) -> CC1NP_W<3> { CC1NP_W::new(self) } #[doc = "Bit 4 - Capture/Compare 2 output enable"] #[inline(always)] #[must_use] pub fn cc2e(&mut self) -> CC2E_W<4> { CC2E_W::new(self) } #[doc = "Bit 5 - Capture/Compare 2 output Polarity"] #[inline(always)] #[must_use] pub fn cc2p(&mut self) -> CC2P_W<5> { CC2P_W::new(self) } #[doc = "Bit 6 - Capture/Compare 2 complementary output enable"] #[inline(always)] #[must_use] pub fn cc2ne(&mut self) -> CC2NE_W<6> { CC2NE_W::new(self) } #[doc = "Bit 7 - Capture/Compare 2 output Polarity"] #[inline(always)] #[must_use] pub fn cc2np(&mut self) -> CC2NP_W<7> { CC2NP_W::new(self) } #[doc = "Bit 8 - Capture/Compare 3 output enable"] #[inline(always)] #[must_use] pub fn cc3e(&mut self) -> CC3E_W<8> { CC3E_W::new(self) } #[doc = "Bit 9 - Capture/Compare 3 output Polarity"] #[inline(always)] #[must_use] pub fn cc3p(&mut self) -> CC3P_W<9> { CC3P_W::new(self) } #[doc = "Bit 10 - Capture/Compare 3 complementary output enable"] #[inline(always)] #[must_use] pub fn cc3ne(&mut self) -> CC3NE_W<10> { CC3NE_W::new(self) } #[doc = "Bit 11 - Capture/Compare 3 output Polarity"] #[inline(always)] #[must_use] pub fn cc3np(&mut self) -> CC3NP_W<11> { CC3NP_W::new(self) } #[doc = "Bit 12 - Capture/Compare 4 output enable"] #[inline(always)] #[must_use] pub fn cc4e(&mut self) -> CC4E_W<12> { CC4E_W::new(self) } #[doc = "Bit 13 - Capture/Compare 3 output Polarity"] #[inline(always)] #[must_use] pub fn cc4p(&mut self) -> CC4P_W<13> { CC4P_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"] pub struct CCER_SPEC; impl crate::RegisterSpec for CCER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccer::R](R) reader structure"] impl crate::Readable for CCER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"] impl crate::Writable for CCER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCER to value 0"] impl crate::Resettable for CCER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNT (rw) register accessor: an alias for `Reg`"] pub type CNT = crate::Reg; #[doc = "counter"] pub mod cnt { #[doc = "Register `CNT` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNT` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CNT` reader - counter value"] pub type CNT_R = crate::FieldReader; #[doc = "Field `CNT` writer - counter value"] pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, CNT_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - counter value"] #[inline(always)] pub fn cnt(&self) -> CNT_R { CNT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - counter value"] #[inline(always)] #[must_use] pub fn cnt(&mut self) -> CNT_W<0> { CNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"] pub struct CNT_SPEC; impl crate::RegisterSpec for CNT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cnt::R](R) reader structure"] impl crate::Readable for CNT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"] impl crate::Writable for CNT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNT to value 0"] impl crate::Resettable for CNT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PSC (rw) register accessor: an alias for `Reg`"] pub type PSC = crate::Reg; #[doc = "prescaler"] pub mod psc { #[doc = "Register `PSC` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PSC` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PSC` reader - Prescaler value"] pub type PSC_R = crate::FieldReader; #[doc = "Field `PSC` writer - Prescaler value"] pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, PSC_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] pub fn psc(&self) -> PSC_R { PSC_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] #[must_use] pub fn psc(&mut self) -> PSC_W<0> { PSC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"] pub struct PSC_SPEC; impl crate::RegisterSpec for PSC_SPEC { type Ux = u32; } #[doc = "`read()` method returns [psc::R](R) reader structure"] impl crate::Readable for PSC_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"] impl crate::Writable for PSC_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PSC to value 0"] impl crate::Resettable for PSC_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ARR (rw) register accessor: an alias for `Reg`"] pub type ARR = crate::Reg; #[doc = "auto-reload register"] pub mod arr { #[doc = "Register `ARR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ARR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARR` reader - Auto-reload value"] pub type ARR_R = crate::FieldReader; #[doc = "Field `ARR` writer - Auto-reload value"] pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, ARR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] pub fn arr(&self) -> ARR_R { ARR_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] #[must_use] pub fn arr(&mut self) -> ARR_W<0> { ARR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "auto-reload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"] pub struct ARR_SPEC; impl crate::RegisterSpec for ARR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [arr::R](R) reader structure"] impl crate::Readable for ARR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"] impl crate::Writable for ARR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ARR to value 0"] impl crate::Resettable for ARR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "RCR (rw) register accessor: an alias for `Reg`"] pub type RCR = crate::Reg; #[doc = "repetition counter register"] pub mod rcr { #[doc = "Register `RCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `RCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `REP` reader - Repetition counter value"] pub type REP_R = crate::FieldReader; #[doc = "Field `REP` writer - Repetition counter value"] pub type REP_W<'a, const O: u8> = crate::FieldWriter<'a, RCR_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - Repetition counter value"] #[inline(always)] pub fn rep(&self) -> REP_R { REP_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - Repetition counter value"] #[inline(always)] #[must_use] pub fn rep(&mut self) -> REP_W<0> { REP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "repetition counter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcr](index.html) module"] pub struct RCR_SPEC; impl crate::RegisterSpec for RCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [rcr::R](R) reader structure"] impl crate::Readable for RCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [rcr::W](W) writer structure"] impl crate::Writable for RCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets RCR to value 0"] impl crate::Resettable for RCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR1 (rw) register accessor: an alias for `Reg`"] pub type CCR1 = crate::Reg; #[doc = "capture/compare register 1"] pub mod ccr1 { #[doc = "Register `CCR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR1` reader - Capture/Compare 1 value"] pub type CCR1_R = crate::FieldReader; #[doc = "Field `CCR1` writer - Capture/Compare 1 value"] pub type CCR1_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] pub fn ccr1(&self) -> CCR1_R { CCR1_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] #[must_use] pub fn ccr1(&mut self) -> CCR1_W<0> { CCR1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"] pub struct CCR1_SPEC; impl crate::RegisterSpec for CCR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr1::R](R) reader structure"] impl crate::Readable for CCR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"] impl crate::Writable for CCR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR1 to value 0"] impl crate::Resettable for CCR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR2 (rw) register accessor: an alias for `Reg`"] pub type CCR2 = crate::Reg; #[doc = "capture/compare register 2"] pub mod ccr2 { #[doc = "Register `CCR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR2` reader - Capture/Compare 2 value"] pub type CCR2_R = crate::FieldReader; #[doc = "Field `CCR2` writer - Capture/Compare 2 value"] pub type CCR2_W<'a, const O: u8> = crate::FieldWriter<'a, CCR2_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare 2 value"] #[inline(always)] pub fn ccr2(&self) -> CCR2_R { CCR2_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare 2 value"] #[inline(always)] #[must_use] pub fn ccr2(&mut self) -> CCR2_W<0> { CCR2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr2](index.html) module"] pub struct CCR2_SPEC; impl crate::RegisterSpec for CCR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr2::R](R) reader structure"] impl crate::Readable for CCR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr2::W](W) writer structure"] impl crate::Writable for CCR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR2 to value 0"] impl crate::Resettable for CCR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR3 (rw) register accessor: an alias for `Reg`"] pub type CCR3 = crate::Reg; #[doc = "capture/compare register 3"] pub mod ccr3 { #[doc = "Register `CCR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR3` reader - Capture/Compare value"] pub type CCR3_R = crate::FieldReader; #[doc = "Field `CCR3` writer - Capture/Compare value"] pub type CCR3_W<'a, const O: u8> = crate::FieldWriter<'a, CCR3_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] pub fn ccr3(&self) -> CCR3_R { CCR3_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] #[must_use] pub fn ccr3(&mut self) -> CCR3_W<0> { CCR3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr3](index.html) module"] pub struct CCR3_SPEC; impl crate::RegisterSpec for CCR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr3::R](R) reader structure"] impl crate::Readable for CCR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr3::W](W) writer structure"] impl crate::Writable for CCR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR3 to value 0"] impl crate::Resettable for CCR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR4 (rw) register accessor: an alias for `Reg`"] pub type CCR4 = crate::Reg; #[doc = "capture/compare register 4"] pub mod ccr4 { #[doc = "Register `CCR4` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR4` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR4` reader - Capture/Compare value"] pub type CCR4_R = crate::FieldReader; #[doc = "Field `CCR4` writer - Capture/Compare value"] pub type CCR4_W<'a, const O: u8> = crate::FieldWriter<'a, CCR4_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] pub fn ccr4(&self) -> CCR4_R { CCR4_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] #[must_use] pub fn ccr4(&mut self) -> CCR4_W<0> { CCR4_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr4](index.html) module"] pub struct CCR4_SPEC; impl crate::RegisterSpec for CCR4_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr4::R](R) reader structure"] impl crate::Readable for CCR4_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr4::W](W) writer structure"] impl crate::Writable for CCR4_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR4 to value 0"] impl crate::Resettable for CCR4_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BDTR (rw) register accessor: an alias for `Reg`"] pub type BDTR = crate::Reg; #[doc = "break and dead-time register"] pub mod bdtr { #[doc = "Register `BDTR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `BDTR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DTG` reader - Dead-time generator setup"] pub type DTG_R = crate::FieldReader; #[doc = "Field `DTG` writer - Dead-time generator setup"] pub type DTG_W<'a, const O: u8> = crate::FieldWriter<'a, BDTR_SPEC, 8, O>; #[doc = "Field `LOCK` reader - Lock configuration"] pub type LOCK_R = crate::FieldReader; #[doc = "Field `LOCK` writer - Lock configuration"] pub type LOCK_W<'a, const O: u8> = crate::FieldWriter<'a, BDTR_SPEC, 2, O>; #[doc = "Field `OSSI` reader - Off-state selection for Idle mode"] pub type OSSI_R = crate::BitReader; #[doc = "Field `OSSI` writer - Off-state selection for Idle mode"] pub type OSSI_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `OSSR` reader - Off-state selection for Run mode"] pub type OSSR_R = crate::BitReader; #[doc = "Field `OSSR` writer - Off-state selection for Run mode"] pub type OSSR_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `BKE` reader - Break enable"] pub type BKE_R = crate::BitReader; #[doc = "Field `BKE` writer - Break enable"] pub type BKE_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `BKP` reader - Break polarity"] pub type BKP_R = crate::BitReader; #[doc = "Field `BKP` writer - Break polarity"] pub type BKP_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `AOE` reader - Automatic output enable"] pub type AOE_R = crate::BitReader; #[doc = "Field `AOE` writer - Automatic output enable"] pub type AOE_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `MOE` reader - Main output enable"] pub type MOE_R = crate::BitReader; #[doc = "Field `MOE` writer - Main output enable"] pub type MOE_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; impl R { #[doc = "Bits 0:7 - Dead-time generator setup"] #[inline(always)] pub fn dtg(&self) -> DTG_R { DTG_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:9 - Lock configuration"] #[inline(always)] pub fn lock(&self) -> LOCK_R { LOCK_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 10 - Off-state selection for Idle mode"] #[inline(always)] pub fn ossi(&self) -> OSSI_R { OSSI_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Off-state selection for Run mode"] #[inline(always)] pub fn ossr(&self) -> OSSR_R { OSSR_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Break enable"] #[inline(always)] pub fn bke(&self) -> BKE_R { BKE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Break polarity"] #[inline(always)] pub fn bkp(&self) -> BKP_R { BKP_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Automatic output enable"] #[inline(always)] pub fn aoe(&self) -> AOE_R { AOE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Main output enable"] #[inline(always)] pub fn moe(&self) -> MOE_R { MOE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:7 - Dead-time generator setup"] #[inline(always)] #[must_use] pub fn dtg(&mut self) -> DTG_W<0> { DTG_W::new(self) } #[doc = "Bits 8:9 - Lock configuration"] #[inline(always)] #[must_use] pub fn lock(&mut self) -> LOCK_W<8> { LOCK_W::new(self) } #[doc = "Bit 10 - Off-state selection for Idle mode"] #[inline(always)] #[must_use] pub fn ossi(&mut self) -> OSSI_W<10> { OSSI_W::new(self) } #[doc = "Bit 11 - Off-state selection for Run mode"] #[inline(always)] #[must_use] pub fn ossr(&mut self) -> OSSR_W<11> { OSSR_W::new(self) } #[doc = "Bit 12 - Break enable"] #[inline(always)] #[must_use] pub fn bke(&mut self) -> BKE_W<12> { BKE_W::new(self) } #[doc = "Bit 13 - Break polarity"] #[inline(always)] #[must_use] pub fn bkp(&mut self) -> BKP_W<13> { BKP_W::new(self) } #[doc = "Bit 14 - Automatic output enable"] #[inline(always)] #[must_use] pub fn aoe(&mut self) -> AOE_W<14> { AOE_W::new(self) } #[doc = "Bit 15 - Main output enable"] #[inline(always)] #[must_use] pub fn moe(&mut self) -> MOE_W<15> { MOE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "break and dead-time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bdtr](index.html) module"] pub struct BDTR_SPEC; impl crate::RegisterSpec for BDTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [bdtr::R](R) reader structure"] impl crate::Readable for BDTR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [bdtr::W](W) writer structure"] impl crate::Writable for BDTR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BDTR to value 0"] impl crate::Resettable for BDTR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DCR (rw) register accessor: an alias for `Reg`"] pub type DCR = crate::Reg; #[doc = "DMA control register"] pub mod dcr { #[doc = "Register `DCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DBA` reader - DMA base address"] pub type DBA_R = crate::FieldReader; #[doc = "Field `DBA` writer - DMA base address"] pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, DCR_SPEC, 5, O>; #[doc = "Field `DBL` reader - DMA burst length"] pub type DBL_R = crate::FieldReader; #[doc = "Field `DBL` writer - DMA burst length"] pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, DCR_SPEC, 5, O>; impl R { #[doc = "Bits 0:4 - DMA base address"] #[inline(always)] pub fn dba(&self) -> DBA_R { DBA_R::new((self.bits & 0x1f) as u8) } #[doc = "Bits 8:12 - DMA burst length"] #[inline(always)] pub fn dbl(&self) -> DBL_R { DBL_R::new(((self.bits >> 8) & 0x1f) as u8) } } impl W { #[doc = "Bits 0:4 - DMA base address"] #[inline(always)] #[must_use] pub fn dba(&mut self) -> DBA_W<0> { DBA_W::new(self) } #[doc = "Bits 8:12 - DMA burst length"] #[inline(always)] #[must_use] pub fn dbl(&mut self) -> DBL_W<8> { DBL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"] pub struct DCR_SPEC; impl crate::RegisterSpec for DCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dcr::R](R) reader structure"] impl crate::Readable for DCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"] impl crate::Writable for DCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DCR to value 0"] impl crate::Resettable for DCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DMAR (rw) register accessor: an alias for `Reg`"] pub type DMAR = crate::Reg; #[doc = "DMA address for full transfer"] pub mod dmar { #[doc = "Register `DMAR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DMAR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMAB` reader - DMA register for burst accesses"] pub type DMAB_R = crate::FieldReader; #[doc = "Field `DMAB` writer - DMA register for burst accesses"] pub type DMAB_W<'a, const O: u8> = crate::FieldWriter<'a, DMAR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - DMA register for burst accesses"] #[inline(always)] pub fn dmab(&self) -> DMAB_R { DMAB_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - DMA register for burst accesses"] #[inline(always)] #[must_use] pub fn dmab(&mut self) -> DMAB_W<0> { DMAB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA address for full transfer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"] pub struct DMAR_SPEC; impl crate::RegisterSpec for DMAR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dmar::R](R) reader structure"] impl crate::Readable for DMAR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"] impl crate::Writable for DMAR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DMAR to value 0"] impl crate::Resettable for DMAR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General purpose timer"] pub struct TIM3 { _marker: PhantomData<*const ()>, } unsafe impl Send for TIM3 {} impl TIM3 { #[doc = r"Pointer to the register block"] pub const PTR: *const tim3::RegisterBlock = 0x4000_0400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const tim3::RegisterBlock { Self::PTR } } impl Deref for TIM3 { type Target = tim3::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for TIM3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("TIM3").finish() } } #[doc = "General purpose timer"] pub mod tim3 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - control register 1"] pub cr1: CR1, #[doc = "0x04 - control register 2"] pub cr2: CR2, #[doc = "0x08 - slave mode control register"] pub smcr: SMCR, #[doc = "0x0c - DMA/Interrupt enable register"] pub dier: DIER, #[doc = "0x10 - status register"] pub sr: SR, #[doc = "0x14 - event generation register"] pub egr: EGR, _reserved_6_ccmr1: [u8; 0x04], _reserved_7_ccmr2: [u8; 0x04], #[doc = "0x20 - capture/compare enable register"] pub ccer: CCER, #[doc = "0x24 - counter"] pub cnt: CNT, #[doc = "0x28 - prescaler"] pub psc: PSC, #[doc = "0x2c - auto-reload register"] pub arr: ARR, _reserved12: [u8; 0x04], #[doc = "0x34 - capture/compare register 1"] pub ccr1: CCR1, #[doc = "0x38 - capture/compare register 2"] pub ccr2: CCR2, #[doc = "0x3c - capture/compare register 3"] pub ccr3: CCR3, #[doc = "0x40 - capture/compare register 4"] pub ccr4: CCR4, _reserved16: [u8; 0x04], #[doc = "0x48 - DMA control register"] pub dcr: DCR, #[doc = "0x4c - DMA address for full transfer"] pub dmar: DMAR, } impl RegisterBlock { #[doc = "0x18 - capture/compare mode register 1 (input mode)"] #[inline(always)] pub const fn ccmr1_input(&self) -> &CCMR1_INPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } #[doc = "0x18 - capture/compare mode register 1 (output mode)"] #[inline(always)] pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } #[doc = "0x1c - capture/compare mode register 2 (input mode)"] #[inline(always)] pub const fn ccmr2_input(&self) -> &CCMR2_INPUT { unsafe { &*(self as *const Self).cast::().add(28usize).cast() } } #[doc = "0x1c - capture/compare mode register 2 (output mode)"] #[inline(always)] pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT { unsafe { &*(self as *const Self).cast::().add(28usize).cast() } } } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "control register 1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CEN` reader - Counter enable"] pub type CEN_R = crate::BitReader; #[doc = "Field `CEN` writer - Counter enable"] pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `UDIS` reader - Update disable"] pub type UDIS_R = crate::BitReader; #[doc = "Field `UDIS` writer - Update disable"] pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `URS` reader - Update request source"] pub type URS_R = crate::BitReader; #[doc = "Field `URS` writer - Update request source"] pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `OPM` reader - One-pulse mode"] pub type OPM_R = crate::BitReader; #[doc = "Field `OPM` writer - One-pulse mode"] pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `DIR` reader - Direction"] pub type DIR_R = crate::BitReader; #[doc = "Field `DIR` writer - Direction"] pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CMS` reader - Center-aligned mode selection"] pub type CMS_R = crate::FieldReader; #[doc = "Field `CMS` writer - Center-aligned mode selection"] pub type CMS_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; #[doc = "Field `ARPE` reader - Auto-reload preload enable"] pub type ARPE_R = crate::BitReader; #[doc = "Field `ARPE` writer - Auto-reload preload enable"] pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CKD` reader - Clock division"] pub type CKD_R = crate::FieldReader; #[doc = "Field `CKD` writer - Clock division"] pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; impl R { #[doc = "Bit 0 - Counter enable"] #[inline(always)] pub fn cen(&self) -> CEN_R { CEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Update disable"] #[inline(always)] pub fn udis(&self) -> UDIS_R { UDIS_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Update request source"] #[inline(always)] pub fn urs(&self) -> URS_R { URS_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - One-pulse mode"] #[inline(always)] pub fn opm(&self) -> OPM_R { OPM_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Direction"] #[inline(always)] pub fn dir(&self) -> DIR_R { DIR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bits 5:6 - Center-aligned mode selection"] #[inline(always)] pub fn cms(&self) -> CMS_R { CMS_R::new(((self.bits >> 5) & 3) as u8) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] pub fn arpe(&self) -> ARPE_R { ARPE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Clock division"] #[inline(always)] pub fn ckd(&self) -> CKD_R { CKD_R::new(((self.bits >> 8) & 3) as u8) } } impl W { #[doc = "Bit 0 - Counter enable"] #[inline(always)] #[must_use] pub fn cen(&mut self) -> CEN_W<0> { CEN_W::new(self) } #[doc = "Bit 1 - Update disable"] #[inline(always)] #[must_use] pub fn udis(&mut self) -> UDIS_W<1> { UDIS_W::new(self) } #[doc = "Bit 2 - Update request source"] #[inline(always)] #[must_use] pub fn urs(&mut self) -> URS_W<2> { URS_W::new(self) } #[doc = "Bit 3 - One-pulse mode"] #[inline(always)] #[must_use] pub fn opm(&mut self) -> OPM_W<3> { OPM_W::new(self) } #[doc = "Bit 4 - Direction"] #[inline(always)] #[must_use] pub fn dir(&mut self) -> DIR_W<4> { DIR_W::new(self) } #[doc = "Bits 5:6 - Center-aligned mode selection"] #[inline(always)] #[must_use] pub fn cms(&mut self) -> CMS_W<5> { CMS_W::new(self) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] #[must_use] pub fn arpe(&mut self) -> ARPE_W<7> { ARPE_W::new(self) } #[doc = "Bits 8:9 - Clock division"] #[inline(always)] #[must_use] pub fn ckd(&mut self) -> CKD_W<8> { CKD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCDS` reader - Capture/compare DMA selection"] pub type CCDS_R = crate::BitReader; #[doc = "Field `CCDS` writer - Capture/compare DMA selection"] pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `MMS` reader - Master mode selection"] pub type MMS_R = crate::FieldReader; #[doc = "Field `MMS` writer - Master mode selection"] pub type MMS_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 3, O>; #[doc = "Field `TI1S` reader - TI1 selection"] pub type TI1S_R = crate::BitReader; #[doc = "Field `TI1S` writer - TI1 selection"] pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; impl R { #[doc = "Bit 3 - Capture/compare DMA selection"] #[inline(always)] pub fn ccds(&self) -> CCDS_R { CCDS_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Master mode selection"] #[inline(always)] pub fn mms(&self) -> MMS_R { MMS_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - TI1 selection"] #[inline(always)] pub fn ti1s(&self) -> TI1S_R { TI1S_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 3 - Capture/compare DMA selection"] #[inline(always)] #[must_use] pub fn ccds(&mut self) -> CCDS_W<3> { CCDS_W::new(self) } #[doc = "Bits 4:6 - Master mode selection"] #[inline(always)] #[must_use] pub fn mms(&mut self) -> MMS_W<4> { MMS_W::new(self) } #[doc = "Bit 7 - TI1 selection"] #[inline(always)] #[must_use] pub fn ti1s(&mut self) -> TI1S_W<7> { TI1S_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SMCR (rw) register accessor: an alias for `Reg`"] pub type SMCR = crate::Reg; #[doc = "slave mode control register"] pub mod smcr { #[doc = "Register `SMCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SMCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SMS` reader - Slave mode selection"] pub type SMS_R = crate::FieldReader; #[doc = "Field `SMS` writer - Slave mode selection"] pub type SMS_W<'a, const O: u8> = crate::FieldWriter<'a, SMCR_SPEC, 3, O>; #[doc = "Field `OCCS` reader - OCREF Clear Selection"] pub type OCCS_R = crate::BitReader; #[doc = "Field `OCCS` writer - OCREF Clear Selection"] pub type OCCS_W<'a, const O: u8> = crate::BitWriter<'a, SMCR_SPEC, O>; #[doc = "Field `TS` reader - Trigger selection"] pub type TS_R = crate::FieldReader; #[doc = "Field `TS` writer - Trigger selection"] pub type TS_W<'a, const O: u8> = crate::FieldWriter<'a, SMCR_SPEC, 3, O>; #[doc = "Field `MSM` reader - Master/Slave mode"] pub type MSM_R = crate::BitReader; #[doc = "Field `MSM` writer - Master/Slave mode"] pub type MSM_W<'a, const O: u8> = crate::BitWriter<'a, SMCR_SPEC, O>; impl R { #[doc = "Bits 0:2 - Slave mode selection"] #[inline(always)] pub fn sms(&self) -> SMS_R { SMS_R::new((self.bits & 7) as u8) } #[doc = "Bit 3 - OCREF Clear Selection"] #[inline(always)] pub fn occs(&self) -> OCCS_R { OCCS_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Trigger selection"] #[inline(always)] pub fn ts(&self) -> TS_R { TS_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - Master/Slave mode"] #[inline(always)] pub fn msm(&self) -> MSM_R { MSM_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bits 0:2 - Slave mode selection"] #[inline(always)] #[must_use] pub fn sms(&mut self) -> SMS_W<0> { SMS_W::new(self) } #[doc = "Bit 3 - OCREF Clear Selection"] #[inline(always)] #[must_use] pub fn occs(&mut self) -> OCCS_W<3> { OCCS_W::new(self) } #[doc = "Bits 4:6 - Trigger selection"] #[inline(always)] #[must_use] pub fn ts(&mut self) -> TS_W<4> { TS_W::new(self) } #[doc = "Bit 7 - Master/Slave mode"] #[inline(always)] #[must_use] pub fn msm(&mut self) -> MSM_W<7> { MSM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "slave mode control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smcr](index.html) module"] pub struct SMCR_SPEC; impl crate::RegisterSpec for SMCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [smcr::R](R) reader structure"] impl crate::Readable for SMCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [smcr::W](W) writer structure"] impl crate::Writable for SMCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SMCR to value 0"] impl crate::Resettable for SMCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DIER (rw) register accessor: an alias for `Reg`"] pub type DIER = crate::Reg; #[doc = "DMA/Interrupt enable register"] pub mod dier { #[doc = "Register `DIER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DIER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIE` reader - Update interrupt enable"] pub type UIE_R = crate::BitReader; #[doc = "Field `UIE` writer - Update interrupt enable"] pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable"] pub type CC1IE_R = crate::BitReader; #[doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable"] pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC2IE` reader - Capture/Compare 2 interrupt enable"] pub type CC2IE_R = crate::BitReader; #[doc = "Field `CC2IE` writer - Capture/Compare 2 interrupt enable"] pub type CC2IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC3IE` reader - Capture/Compare 3 interrupt enable"] pub type CC3IE_R = crate::BitReader; #[doc = "Field `CC3IE` writer - Capture/Compare 3 interrupt enable"] pub type CC3IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC4IE` reader - Capture/Compare 4 interrupt enable"] pub type CC4IE_R = crate::BitReader; #[doc = "Field `CC4IE` writer - Capture/Compare 4 interrupt enable"] pub type CC4IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `TIE` reader - Trigger interrupt enable"] pub type TIE_R = crate::BitReader; #[doc = "Field `TIE` writer - Trigger interrupt enable"] pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `UDE` reader - Update DMA request enable"] pub type UDE_R = crate::BitReader; #[doc = "Field `UDE` writer - Update DMA request enable"] pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1DE` reader - Capture/Compare 1 DMA request enable"] pub type CC1DE_R = crate::BitReader; #[doc = "Field `CC1DE` writer - Capture/Compare 1 DMA request enable"] pub type CC1DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC2DE` reader - Capture/Compare 2 DMA request enable"] pub type CC2DE_R = crate::BitReader; #[doc = "Field `CC2DE` writer - Capture/Compare 2 DMA request enable"] pub type CC2DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC3DE` reader - Capture/Compare 3 DMA request enable"] pub type CC3DE_R = crate::BitReader; #[doc = "Field `CC3DE` writer - Capture/Compare 3 DMA request enable"] pub type CC3DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC4DE` reader - Capture/Compare 4 DMA request enable"] pub type CC4DE_R = crate::BitReader; #[doc = "Field `CC4DE` writer - Capture/Compare 4 DMA request enable"] pub type CC4DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `TDE` reader - Trigger DMA request enable"] pub type TDE_R = crate::BitReader; #[doc = "Field `TDE` writer - Trigger DMA request enable"] pub type TDE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] pub fn uie(&self) -> UIE_R { UIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 interrupt enable"] #[inline(always)] pub fn cc1ie(&self) -> CC1IE_R { CC1IE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Capture/Compare 2 interrupt enable"] #[inline(always)] pub fn cc2ie(&self) -> CC2IE_R { CC2IE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 3 interrupt enable"] #[inline(always)] pub fn cc3ie(&self) -> CC3IE_R { CC3IE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Capture/Compare 4 interrupt enable"] #[inline(always)] pub fn cc4ie(&self) -> CC4IE_R { CC4IE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 6 - Trigger interrupt enable"] #[inline(always)] pub fn tie(&self) -> TIE_R { TIE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 8 - Update DMA request enable"] #[inline(always)] pub fn ude(&self) -> UDE_R { UDE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Capture/Compare 1 DMA request enable"] #[inline(always)] pub fn cc1de(&self) -> CC1DE_R { CC1DE_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Capture/Compare 2 DMA request enable"] #[inline(always)] pub fn cc2de(&self) -> CC2DE_R { CC2DE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Capture/Compare 3 DMA request enable"] #[inline(always)] pub fn cc3de(&self) -> CC3DE_R { CC3DE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Capture/Compare 4 DMA request enable"] #[inline(always)] pub fn cc4de(&self) -> CC4DE_R { CC4DE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 14 - Trigger DMA request enable"] #[inline(always)] pub fn tde(&self) -> TDE_R { TDE_R::new(((self.bits >> 14) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] #[must_use] pub fn uie(&mut self) -> UIE_W<0> { UIE_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 interrupt enable"] #[inline(always)] #[must_use] pub fn cc1ie(&mut self) -> CC1IE_W<1> { CC1IE_W::new(self) } #[doc = "Bit 2 - Capture/Compare 2 interrupt enable"] #[inline(always)] #[must_use] pub fn cc2ie(&mut self) -> CC2IE_W<2> { CC2IE_W::new(self) } #[doc = "Bit 3 - Capture/Compare 3 interrupt enable"] #[inline(always)] #[must_use] pub fn cc3ie(&mut self) -> CC3IE_W<3> { CC3IE_W::new(self) } #[doc = "Bit 4 - Capture/Compare 4 interrupt enable"] #[inline(always)] #[must_use] pub fn cc4ie(&mut self) -> CC4IE_W<4> { CC4IE_W::new(self) } #[doc = "Bit 6 - Trigger interrupt enable"] #[inline(always)] #[must_use] pub fn tie(&mut self) -> TIE_W<6> { TIE_W::new(self) } #[doc = "Bit 8 - Update DMA request enable"] #[inline(always)] #[must_use] pub fn ude(&mut self) -> UDE_W<8> { UDE_W::new(self) } #[doc = "Bit 9 - Capture/Compare 1 DMA request enable"] #[inline(always)] #[must_use] pub fn cc1de(&mut self) -> CC1DE_W<9> { CC1DE_W::new(self) } #[doc = "Bit 10 - Capture/Compare 2 DMA request enable"] #[inline(always)] #[must_use] pub fn cc2de(&mut self) -> CC2DE_W<10> { CC2DE_W::new(self) } #[doc = "Bit 11 - Capture/Compare 3 DMA request enable"] #[inline(always)] #[must_use] pub fn cc3de(&mut self) -> CC3DE_W<11> { CC3DE_W::new(self) } #[doc = "Bit 12 - Capture/Compare 4 DMA request enable"] #[inline(always)] #[must_use] pub fn cc4de(&mut self) -> CC4DE_W<12> { CC4DE_W::new(self) } #[doc = "Bit 14 - Trigger DMA request enable"] #[inline(always)] #[must_use] pub fn tde(&mut self) -> TDE_W<14> { TDE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA/Interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"] pub struct DIER_SPEC; impl crate::RegisterSpec for DIER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dier::R](R) reader structure"] impl crate::Readable for DIER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"] impl crate::Writable for DIER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DIER to value 0"] impl crate::Resettable for DIER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIF` reader - Update interrupt flag"] pub type UIF_R = crate::BitReader; #[doc = "Field `UIF` writer - Update interrupt flag"] pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1IF` reader - Capture/compare 1 interrupt flag"] pub type CC1IF_R = crate::BitReader; #[doc = "Field `CC1IF` writer - Capture/compare 1 interrupt flag"] pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC2IF` reader - Capture/Compare 2 interrupt flag"] pub type CC2IF_R = crate::BitReader; #[doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag"] pub type CC2IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC3IF` reader - Capture/Compare 3 interrupt flag"] pub type CC3IF_R = crate::BitReader; #[doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag"] pub type CC3IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC4IF` reader - Capture/Compare 4 interrupt flag"] pub type CC4IF_R = crate::BitReader; #[doc = "Field `CC4IF` writer - Capture/Compare 4 interrupt flag"] pub type CC4IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `TIF` reader - Trigger interrupt flag"] pub type TIF_R = crate::BitReader; #[doc = "Field `TIF` writer - Trigger interrupt flag"] pub type TIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1OF` reader - Capture/Compare 1 overcapture flag"] pub type CC1OF_R = crate::BitReader; #[doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag"] pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC2OF` reader - Capture/compare 2 overcapture flag"] pub type CC2OF_R = crate::BitReader; #[doc = "Field `CC2OF` writer - Capture/compare 2 overcapture flag"] pub type CC2OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC3OF` reader - Capture/Compare 3 overcapture flag"] pub type CC3OF_R = crate::BitReader; #[doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag"] pub type CC3OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC4OF` reader - Capture/Compare 4 overcapture flag"] pub type CC4OF_R = crate::BitReader; #[doc = "Field `CC4OF` writer - Capture/Compare 4 overcapture flag"] pub type CC4OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] pub fn uif(&self) -> UIF_R { UIF_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/compare 1 interrupt flag"] #[inline(always)] pub fn cc1if(&self) -> CC1IF_R { CC1IF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Capture/Compare 2 interrupt flag"] #[inline(always)] pub fn cc2if(&self) -> CC2IF_R { CC2IF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 3 interrupt flag"] #[inline(always)] pub fn cc3if(&self) -> CC3IF_R { CC3IF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Capture/Compare 4 interrupt flag"] #[inline(always)] pub fn cc4if(&self) -> CC4IF_R { CC4IF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 6 - Trigger interrupt flag"] #[inline(always)] pub fn tif(&self) -> TIF_R { TIF_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 9 - Capture/Compare 1 overcapture flag"] #[inline(always)] pub fn cc1of(&self) -> CC1OF_R { CC1OF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Capture/compare 2 overcapture flag"] #[inline(always)] pub fn cc2of(&self) -> CC2OF_R { CC2OF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Capture/Compare 3 overcapture flag"] #[inline(always)] pub fn cc3of(&self) -> CC3OF_R { CC3OF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Capture/Compare 4 overcapture flag"] #[inline(always)] pub fn cc4of(&self) -> CC4OF_R { CC4OF_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] #[must_use] pub fn uif(&mut self) -> UIF_W<0> { UIF_W::new(self) } #[doc = "Bit 1 - Capture/compare 1 interrupt flag"] #[inline(always)] #[must_use] pub fn cc1if(&mut self) -> CC1IF_W<1> { CC1IF_W::new(self) } #[doc = "Bit 2 - Capture/Compare 2 interrupt flag"] #[inline(always)] #[must_use] pub fn cc2if(&mut self) -> CC2IF_W<2> { CC2IF_W::new(self) } #[doc = "Bit 3 - Capture/Compare 3 interrupt flag"] #[inline(always)] #[must_use] pub fn cc3if(&mut self) -> CC3IF_W<3> { CC3IF_W::new(self) } #[doc = "Bit 4 - Capture/Compare 4 interrupt flag"] #[inline(always)] #[must_use] pub fn cc4if(&mut self) -> CC4IF_W<4> { CC4IF_W::new(self) } #[doc = "Bit 6 - Trigger interrupt flag"] #[inline(always)] #[must_use] pub fn tif(&mut self) -> TIF_W<6> { TIF_W::new(self) } #[doc = "Bit 9 - Capture/Compare 1 overcapture flag"] #[inline(always)] #[must_use] pub fn cc1of(&mut self) -> CC1OF_W<9> { CC1OF_W::new(self) } #[doc = "Bit 10 - Capture/compare 2 overcapture flag"] #[inline(always)] #[must_use] pub fn cc2of(&mut self) -> CC2OF_W<10> { CC2OF_W::new(self) } #[doc = "Bit 11 - Capture/Compare 3 overcapture flag"] #[inline(always)] #[must_use] pub fn cc3of(&mut self) -> CC3OF_W<11> { CC3OF_W::new(self) } #[doc = "Bit 12 - Capture/Compare 4 overcapture flag"] #[inline(always)] #[must_use] pub fn cc4of(&mut self) -> CC4OF_W<12> { CC4OF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EGR (w) register accessor: an alias for `Reg`"] pub type EGR = crate::Reg; #[doc = "event generation register"] pub mod egr { #[doc = "Register `EGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UG` writer - Update generation"] pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC1G` writer - Capture/compare 1 generation"] pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC2G` writer - Capture/compare 2 generation"] pub type CC2G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC3G` writer - Capture/compare 3 generation"] pub type CC3G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC4G` writer - Capture/compare 4 generation"] pub type CC4G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `TG` writer - Trigger generation"] pub type TG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; impl W { #[doc = "Bit 0 - Update generation"] #[inline(always)] #[must_use] pub fn ug(&mut self) -> UG_W<0> { UG_W::new(self) } #[doc = "Bit 1 - Capture/compare 1 generation"] #[inline(always)] #[must_use] pub fn cc1g(&mut self) -> CC1G_W<1> { CC1G_W::new(self) } #[doc = "Bit 2 - Capture/compare 2 generation"] #[inline(always)] #[must_use] pub fn cc2g(&mut self) -> CC2G_W<2> { CC2G_W::new(self) } #[doc = "Bit 3 - Capture/compare 3 generation"] #[inline(always)] #[must_use] pub fn cc3g(&mut self) -> CC3G_W<3> { CC3G_W::new(self) } #[doc = "Bit 4 - Capture/compare 4 generation"] #[inline(always)] #[must_use] pub fn cc4g(&mut self) -> CC4G_W<4> { CC4G_W::new(self) } #[doc = "Bit 6 - Trigger generation"] #[inline(always)] #[must_use] pub fn tg(&mut self) -> TG_W<6> { TG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"] pub struct EGR_SPEC; impl crate::RegisterSpec for EGR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"] impl crate::Writable for EGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EGR to value 0"] impl crate::Resettable for EGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg`"] pub type CCMR1_OUTPUT = crate::Reg; #[doc = "capture/compare mode register 1 (output mode)"] pub mod ccmr1_output { #[doc = "Register `CCMR1_Output` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Output` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC1FE` reader - Output compare 1 fast enable"] pub type OC1FE_R = crate::BitReader; #[doc = "Field `OC1FE` writer - Output compare 1 fast enable"] pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1PE` reader - Output compare 1 preload enable"] pub type OC1PE_R = crate::BitReader; #[doc = "Field `OC1PE` writer - Output compare 1 preload enable"] pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1M` reader - Output compare 1 mode"] pub type OC1M_R = crate::FieldReader; #[doc = "Field `OC1M` writer - Output compare 1 mode"] pub type OC1M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC1CE` reader - Output compare 1 clear enable"] pub type OC1CE_R = crate::BitReader; #[doc = "Field `OC1CE` writer - Output compare 1 clear enable"] pub type OC1CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `CC2S` reader - Capture/Compare 2 selection"] pub type CC2S_R = crate::FieldReader; #[doc = "Field `CC2S` writer - Capture/Compare 2 selection"] pub type CC2S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC2FE` reader - Output compare 2 fast enable"] pub type OC2FE_R = crate::BitReader; #[doc = "Field `OC2FE` writer - Output compare 2 fast enable"] pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC2PE` reader - Output compare 2 preload enable"] pub type OC2PE_R = crate::BitReader; #[doc = "Field `OC2PE` writer - Output compare 2 preload enable"] pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC2M` reader - Output compare 2 mode"] pub type OC2M_R = crate::FieldReader; #[doc = "Field `OC2M` writer - Output compare 2 mode"] pub type OC2M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC2CE` reader - Output compare 2 clear enable"] pub type OC2CE_R = crate::BitReader; #[doc = "Field `OC2CE` writer - Output compare 2 clear enable"] pub type OC2CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Output compare 1 fast enable"] #[inline(always)] pub fn oc1fe(&self) -> OC1FE_R { OC1FE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Output compare 1 preload enable"] #[inline(always)] pub fn oc1pe(&self) -> OC1PE_R { OC1PE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Output compare 1 mode"] #[inline(always)] pub fn oc1m(&self) -> OC1M_R { OC1M_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - Output compare 1 clear enable"] #[inline(always)] pub fn oc1ce(&self) -> OC1CE_R { OC1CE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Capture/Compare 2 selection"] #[inline(always)] pub fn cc2s(&self) -> CC2S_R { CC2S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 10 - Output compare 2 fast enable"] #[inline(always)] pub fn oc2fe(&self) -> OC2FE_R { OC2FE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Output compare 2 preload enable"] #[inline(always)] pub fn oc2pe(&self) -> OC2PE_R { OC2PE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bits 12:14 - Output compare 2 mode"] #[inline(always)] pub fn oc2m(&self) -> OC2M_R { OC2M_R::new(((self.bits >> 12) & 7) as u8) } #[doc = "Bit 15 - Output compare 2 clear enable"] #[inline(always)] pub fn oc2ce(&self) -> OC2CE_R { OC2CE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bit 2 - Output compare 1 fast enable"] #[inline(always)] #[must_use] pub fn oc1fe(&mut self) -> OC1FE_W<2> { OC1FE_W::new(self) } #[doc = "Bit 3 - Output compare 1 preload enable"] #[inline(always)] #[must_use] pub fn oc1pe(&mut self) -> OC1PE_W<3> { OC1PE_W::new(self) } #[doc = "Bits 4:6 - Output compare 1 mode"] #[inline(always)] #[must_use] pub fn oc1m(&mut self) -> OC1M_W<4> { OC1M_W::new(self) } #[doc = "Bit 7 - Output compare 1 clear enable"] #[inline(always)] #[must_use] pub fn oc1ce(&mut self) -> OC1CE_W<7> { OC1CE_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 2 selection"] #[inline(always)] #[must_use] pub fn cc2s(&mut self) -> CC2S_W<8> { CC2S_W::new(self) } #[doc = "Bit 10 - Output compare 2 fast enable"] #[inline(always)] #[must_use] pub fn oc2fe(&mut self) -> OC2FE_W<10> { OC2FE_W::new(self) } #[doc = "Bit 11 - Output compare 2 preload enable"] #[inline(always)] #[must_use] pub fn oc2pe(&mut self) -> OC2PE_W<11> { OC2PE_W::new(self) } #[doc = "Bits 12:14 - Output compare 2 mode"] #[inline(always)] #[must_use] pub fn oc2m(&mut self) -> OC2M_W<12> { OC2M_W::new(self) } #[doc = "Bit 15 - Output compare 2 clear enable"] #[inline(always)] #[must_use] pub fn oc2ce(&mut self) -> OC2CE_W<15> { OC2CE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 1 (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"] pub struct CCMR1_OUTPUT_SPEC; impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"] impl crate::Readable for CCMR1_OUTPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"] impl crate::Writable for CCMR1_OUTPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Output to value 0"] impl crate::Resettable for CCMR1_OUTPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg`"] pub type CCMR1_INPUT = crate::Reg; #[doc = "capture/compare mode register 1 (input mode)"] pub mod ccmr1_input { #[doc = "Register `CCMR1_Input` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Input` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1PSC` reader - Input capture 1 prescaler"] pub type IC1PSC_R = crate::FieldReader; #[doc = "Field `IC1PSC` writer - Input capture 1 prescaler"] pub type IC1PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1F` reader - Input capture 1 filter"] pub type IC1F_R = crate::FieldReader; #[doc = "Field `IC1F` writer - Input capture 1 filter"] pub type IC1F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 4, O>; #[doc = "Field `CC2S` reader - Capture/compare 2 selection"] pub type CC2S_R = crate::FieldReader; #[doc = "Field `CC2S` writer - Capture/compare 2 selection"] pub type CC2S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC2PSC` reader - Input capture 2 prescaler"] pub type IC2PSC_R = crate::FieldReader; #[doc = "Field `IC2PSC` writer - Input capture 2 prescaler"] pub type IC2PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC2F` reader - Input capture 2 filter"] pub type IC2F_R = crate::FieldReader; #[doc = "Field `IC2F` writer - Input capture 2 filter"] pub type IC2F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 4, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] pub fn ic1psc(&self) -> IC1PSC_R { IC1PSC_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] pub fn ic1f(&self) -> IC1F_R { IC1F_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:9 - Capture/compare 2 selection"] #[inline(always)] pub fn cc2s(&self) -> CC2S_R { CC2S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Input capture 2 prescaler"] #[inline(always)] pub fn ic2psc(&self) -> IC2PSC_R { IC2PSC_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:15 - Input capture 2 filter"] #[inline(always)] pub fn ic2f(&self) -> IC2F_R { IC2F_R::new(((self.bits >> 12) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] #[must_use] pub fn ic1psc(&mut self) -> IC1PSC_W<2> { IC1PSC_W::new(self) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] #[must_use] pub fn ic1f(&mut self) -> IC1F_W<4> { IC1F_W::new(self) } #[doc = "Bits 8:9 - Capture/compare 2 selection"] #[inline(always)] #[must_use] pub fn cc2s(&mut self) -> CC2S_W<8> { CC2S_W::new(self) } #[doc = "Bits 10:11 - Input capture 2 prescaler"] #[inline(always)] #[must_use] pub fn ic2psc(&mut self) -> IC2PSC_W<10> { IC2PSC_W::new(self) } #[doc = "Bits 12:15 - Input capture 2 filter"] #[inline(always)] #[must_use] pub fn ic2f(&mut self) -> IC2F_W<12> { IC2F_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 1 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"] pub struct CCMR1_INPUT_SPEC; impl crate::RegisterSpec for CCMR1_INPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"] impl crate::Readable for CCMR1_INPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"] impl crate::Writable for CCMR1_INPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Input to value 0"] impl crate::Resettable for CCMR1_INPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR2_Output (rw) register accessor: an alias for `Reg`"] pub type CCMR2_OUTPUT = crate::Reg; #[doc = "capture/compare mode register 2 (output mode)"] pub mod ccmr2_output { #[doc = "Register `CCMR2_Output` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR2_Output` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC3S` reader - Capture/Compare 3 selection"] pub type CC3S_R = crate::FieldReader; #[doc = "Field `CC3S` writer - Capture/Compare 3 selection"] pub type CC3S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC3FE` reader - Output compare 3 fast enable"] pub type OC3FE_R = crate::BitReader; #[doc = "Field `OC3FE` writer - Output compare 3 fast enable"] pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC3PE` reader - Output compare 3 preload enable"] pub type OC3PE_R = crate::BitReader; #[doc = "Field `OC3PE` writer - Output compare 3 preload enable"] pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC3M` reader - Output compare 3 mode"] pub type OC3M_R = crate::FieldReader; #[doc = "Field `OC3M` writer - Output compare 3 mode"] pub type OC3M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC3CE` reader - Output compare 3 clear enable"] pub type OC3CE_R = crate::BitReader; #[doc = "Field `OC3CE` writer - Output compare 3 clear enable"] pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `CC4S` reader - Capture/Compare 4 selection"] pub type CC4S_R = crate::FieldReader; #[doc = "Field `CC4S` writer - Capture/Compare 4 selection"] pub type CC4S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC4FE` reader - Output compare 4 fast enable"] pub type OC4FE_R = crate::BitReader; #[doc = "Field `OC4FE` writer - Output compare 4 fast enable"] pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC4PE` reader - Output compare 4 preload enable"] pub type OC4PE_R = crate::BitReader; #[doc = "Field `OC4PE` writer - Output compare 4 preload enable"] pub type OC4PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; #[doc = "Field `OC4M` reader - Output compare 4 mode"] pub type OC4M_R = crate::FieldReader; #[doc = "Field `OC4M` writer - Output compare 4 mode"] pub type OC4M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_OUTPUT_SPEC, 3, O>; #[doc = "Field `OC4CE` reader - Output compare 4 clear enable"] pub type OC4CE_R = crate::BitReader; #[doc = "Field `OC4CE` writer - Output compare 4 clear enable"] pub type OC4CE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR2_OUTPUT_SPEC, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 3 selection"] #[inline(always)] pub fn cc3s(&self) -> CC3S_R { CC3S_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Output compare 3 fast enable"] #[inline(always)] pub fn oc3fe(&self) -> OC3FE_R { OC3FE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Output compare 3 preload enable"] #[inline(always)] pub fn oc3pe(&self) -> OC3PE_R { OC3PE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Output compare 3 mode"] #[inline(always)] pub fn oc3m(&self) -> OC3M_R { OC3M_R::new(((self.bits >> 4) & 7) as u8) } #[doc = "Bit 7 - Output compare 3 clear enable"] #[inline(always)] pub fn oc3ce(&self) -> OC3CE_R { OC3CE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] pub fn cc4s(&self) -> CC4S_R { CC4S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 10 - Output compare 4 fast enable"] #[inline(always)] pub fn oc4fe(&self) -> OC4FE_R { OC4FE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Output compare 4 preload enable"] #[inline(always)] pub fn oc4pe(&self) -> OC4PE_R { OC4PE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bits 12:14 - Output compare 4 mode"] #[inline(always)] pub fn oc4m(&self) -> OC4M_R { OC4M_R::new(((self.bits >> 12) & 7) as u8) } #[doc = "Bit 15 - Output compare 4 clear enable"] #[inline(always)] pub fn oc4ce(&self) -> OC4CE_R { OC4CE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 3 selection"] #[inline(always)] #[must_use] pub fn cc3s(&mut self) -> CC3S_W<0> { CC3S_W::new(self) } #[doc = "Bit 2 - Output compare 3 fast enable"] #[inline(always)] #[must_use] pub fn oc3fe(&mut self) -> OC3FE_W<2> { OC3FE_W::new(self) } #[doc = "Bit 3 - Output compare 3 preload enable"] #[inline(always)] #[must_use] pub fn oc3pe(&mut self) -> OC3PE_W<3> { OC3PE_W::new(self) } #[doc = "Bits 4:6 - Output compare 3 mode"] #[inline(always)] #[must_use] pub fn oc3m(&mut self) -> OC3M_W<4> { OC3M_W::new(self) } #[doc = "Bit 7 - Output compare 3 clear enable"] #[inline(always)] #[must_use] pub fn oc3ce(&mut self) -> OC3CE_W<7> { OC3CE_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] #[must_use] pub fn cc4s(&mut self) -> CC4S_W<8> { CC4S_W::new(self) } #[doc = "Bit 10 - Output compare 4 fast enable"] #[inline(always)] #[must_use] pub fn oc4fe(&mut self) -> OC4FE_W<10> { OC4FE_W::new(self) } #[doc = "Bit 11 - Output compare 4 preload enable"] #[inline(always)] #[must_use] pub fn oc4pe(&mut self) -> OC4PE_W<11> { OC4PE_W::new(self) } #[doc = "Bits 12:14 - Output compare 4 mode"] #[inline(always)] #[must_use] pub fn oc4m(&mut self) -> OC4M_W<12> { OC4M_W::new(self) } #[doc = "Bit 15 - Output compare 4 clear enable"] #[inline(always)] #[must_use] pub fn oc4ce(&mut self) -> OC4CE_W<15> { OC4CE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 2 (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_output](index.html) module"] pub struct CCMR2_OUTPUT_SPEC; impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr2_output::R](R) reader structure"] impl crate::Readable for CCMR2_OUTPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure"] impl crate::Writable for CCMR2_OUTPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR2_Output to value 0"] impl crate::Resettable for CCMR2_OUTPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR2_Input (rw) register accessor: an alias for `Reg`"] pub type CCMR2_INPUT = crate::Reg; #[doc = "capture/compare mode register 2 (input mode)"] pub mod ccmr2_input { #[doc = "Register `CCMR2_Input` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR2_Input` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC3S` reader - Capture/Compare 3 selection"] pub type CC3S_R = crate::FieldReader; #[doc = "Field `CC3S` writer - Capture/Compare 3 selection"] pub type CC3S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC3PSC` reader - Input capture 3 prescaler"] pub type IC3PSC_R = crate::FieldReader; #[doc = "Field `IC3PSC` writer - Input capture 3 prescaler"] pub type IC3PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC3F` reader - Input capture 3 filter"] pub type IC3F_R = crate::FieldReader; #[doc = "Field `IC3F` writer - Input capture 3 filter"] pub type IC3F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 4, O>; #[doc = "Field `CC4S` reader - Capture/Compare 4 selection"] pub type CC4S_R = crate::FieldReader; #[doc = "Field `CC4S` writer - Capture/Compare 4 selection"] pub type CC4S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC4PSC` reader - Input capture 4 prescaler"] pub type IC4PSC_R = crate::FieldReader; #[doc = "Field `IC4PSC` writer - Input capture 4 prescaler"] pub type IC4PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 2, O>; #[doc = "Field `IC4F` reader - Input capture 4 filter"] pub type IC4F_R = crate::FieldReader; #[doc = "Field `IC4F` writer - Input capture 4 filter"] pub type IC4F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR2_INPUT_SPEC, 4, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 3 selection"] #[inline(always)] pub fn cc3s(&self) -> CC3S_R { CC3S_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Input capture 3 prescaler"] #[inline(always)] pub fn ic3psc(&self) -> IC3PSC_R { IC3PSC_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:7 - Input capture 3 filter"] #[inline(always)] pub fn ic3f(&self) -> IC3F_R { IC3F_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] pub fn cc4s(&self) -> CC4S_R { CC4S_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Input capture 4 prescaler"] #[inline(always)] pub fn ic4psc(&self) -> IC4PSC_R { IC4PSC_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:15 - Input capture 4 filter"] #[inline(always)] pub fn ic4f(&self) -> IC4F_R { IC4F_R::new(((self.bits >> 12) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 3 selection"] #[inline(always)] #[must_use] pub fn cc3s(&mut self) -> CC3S_W<0> { CC3S_W::new(self) } #[doc = "Bits 2:3 - Input capture 3 prescaler"] #[inline(always)] #[must_use] pub fn ic3psc(&mut self) -> IC3PSC_W<2> { IC3PSC_W::new(self) } #[doc = "Bits 4:7 - Input capture 3 filter"] #[inline(always)] #[must_use] pub fn ic3f(&mut self) -> IC3F_W<4> { IC3F_W::new(self) } #[doc = "Bits 8:9 - Capture/Compare 4 selection"] #[inline(always)] #[must_use] pub fn cc4s(&mut self) -> CC4S_W<8> { CC4S_W::new(self) } #[doc = "Bits 10:11 - Input capture 4 prescaler"] #[inline(always)] #[must_use] pub fn ic4psc(&mut self) -> IC4PSC_W<10> { IC4PSC_W::new(self) } #[doc = "Bits 12:15 - Input capture 4 filter"] #[inline(always)] #[must_use] pub fn ic4f(&mut self) -> IC4F_W<12> { IC4F_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 2 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_input](index.html) module"] pub struct CCMR2_INPUT_SPEC; impl crate::RegisterSpec for CCMR2_INPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr2_input::R](R) reader structure"] impl crate::Readable for CCMR2_INPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr2_input::W](W) writer structure"] impl crate::Writable for CCMR2_INPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR2_Input to value 0"] impl crate::Resettable for CCMR2_INPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCER (rw) register accessor: an alias for `Reg`"] pub type CCER = crate::Reg; #[doc = "capture/compare enable register"] pub mod ccer { #[doc = "Register `CCER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1E` reader - Capture/Compare 1 output enable"] pub type CC1E_R = crate::BitReader; #[doc = "Field `CC1E` writer - Capture/Compare 1 output enable"] pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity"] pub type CC1P_R = crate::BitReader; #[doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity"] pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1NP` reader - Capture/Compare 1 output Polarity"] pub type CC1NP_R = crate::BitReader; #[doc = "Field `CC1NP` writer - Capture/Compare 1 output Polarity"] pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2E` reader - Capture/Compare 2 output enable"] pub type CC2E_R = crate::BitReader; #[doc = "Field `CC2E` writer - Capture/Compare 2 output enable"] pub type CC2E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2P` reader - Capture/Compare 2 output Polarity"] pub type CC2P_R = crate::BitReader; #[doc = "Field `CC2P` writer - Capture/Compare 2 output Polarity"] pub type CC2P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC2NP` reader - Capture/Compare 2 output Polarity"] pub type CC2NP_R = crate::BitReader; #[doc = "Field `CC2NP` writer - Capture/Compare 2 output Polarity"] pub type CC2NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3E` reader - Capture/Compare 3 output enable"] pub type CC3E_R = crate::BitReader; #[doc = "Field `CC3E` writer - Capture/Compare 3 output enable"] pub type CC3E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3P` reader - Capture/Compare 3 output Polarity"] pub type CC3P_R = crate::BitReader; #[doc = "Field `CC3P` writer - Capture/Compare 3 output Polarity"] pub type CC3P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC3NP` reader - Capture/Compare 3 output Polarity"] pub type CC3NP_R = crate::BitReader; #[doc = "Field `CC3NP` writer - Capture/Compare 3 output Polarity"] pub type CC3NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC4E` reader - Capture/Compare 4 output enable"] pub type CC4E_R = crate::BitReader; #[doc = "Field `CC4E` writer - Capture/Compare 4 output enable"] pub type CC4E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC4P` reader - Capture/Compare 4 output Polarity"] pub type CC4P_R = crate::BitReader; #[doc = "Field `CC4P` writer - Capture/Compare 4 output Polarity"] pub type CC4P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC4NP` reader - Capture/Compare 4 output Polarity"] pub type CC4NP_R = crate::BitReader; #[doc = "Field `CC4NP` writer - Capture/Compare 4 output Polarity"] pub type CC4NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; impl R { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] pub fn cc1e(&self) -> CC1E_R { CC1E_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1p(&self) -> CC1P_R { CC1P_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1np(&self) -> CC1NP_R { CC1NP_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Capture/Compare 2 output enable"] #[inline(always)] pub fn cc2e(&self) -> CC2E_R { CC2E_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Capture/Compare 2 output Polarity"] #[inline(always)] pub fn cc2p(&self) -> CC2P_R { CC2P_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 7 - Capture/Compare 2 output Polarity"] #[inline(always)] pub fn cc2np(&self) -> CC2NP_R { CC2NP_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Capture/Compare 3 output enable"] #[inline(always)] pub fn cc3e(&self) -> CC3E_R { CC3E_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Capture/Compare 3 output Polarity"] #[inline(always)] pub fn cc3p(&self) -> CC3P_R { CC3P_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 11 - Capture/Compare 3 output Polarity"] #[inline(always)] pub fn cc3np(&self) -> CC3NP_R { CC3NP_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Capture/Compare 4 output enable"] #[inline(always)] pub fn cc4e(&self) -> CC4E_R { CC4E_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Capture/Compare 4 output Polarity"] #[inline(always)] pub fn cc4p(&self) -> CC4P_R { CC4P_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 15 - Capture/Compare 4 output Polarity"] #[inline(always)] pub fn cc4np(&self) -> CC4NP_R { CC4NP_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] #[must_use] pub fn cc1e(&mut self) -> CC1E_W<0> { CC1E_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1p(&mut self) -> CC1P_W<1> { CC1P_W::new(self) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1np(&mut self) -> CC1NP_W<3> { CC1NP_W::new(self) } #[doc = "Bit 4 - Capture/Compare 2 output enable"] #[inline(always)] #[must_use] pub fn cc2e(&mut self) -> CC2E_W<4> { CC2E_W::new(self) } #[doc = "Bit 5 - Capture/Compare 2 output Polarity"] #[inline(always)] #[must_use] pub fn cc2p(&mut self) -> CC2P_W<5> { CC2P_W::new(self) } #[doc = "Bit 7 - Capture/Compare 2 output Polarity"] #[inline(always)] #[must_use] pub fn cc2np(&mut self) -> CC2NP_W<7> { CC2NP_W::new(self) } #[doc = "Bit 8 - Capture/Compare 3 output enable"] #[inline(always)] #[must_use] pub fn cc3e(&mut self) -> CC3E_W<8> { CC3E_W::new(self) } #[doc = "Bit 9 - Capture/Compare 3 output Polarity"] #[inline(always)] #[must_use] pub fn cc3p(&mut self) -> CC3P_W<9> { CC3P_W::new(self) } #[doc = "Bit 11 - Capture/Compare 3 output Polarity"] #[inline(always)] #[must_use] pub fn cc3np(&mut self) -> CC3NP_W<11> { CC3NP_W::new(self) } #[doc = "Bit 12 - Capture/Compare 4 output enable"] #[inline(always)] #[must_use] pub fn cc4e(&mut self) -> CC4E_W<12> { CC4E_W::new(self) } #[doc = "Bit 13 - Capture/Compare 4 output Polarity"] #[inline(always)] #[must_use] pub fn cc4p(&mut self) -> CC4P_W<13> { CC4P_W::new(self) } #[doc = "Bit 15 - Capture/Compare 4 output Polarity"] #[inline(always)] #[must_use] pub fn cc4np(&mut self) -> CC4NP_W<15> { CC4NP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"] pub struct CCER_SPEC; impl crate::RegisterSpec for CCER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccer::R](R) reader structure"] impl crate::Readable for CCER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"] impl crate::Writable for CCER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCER to value 0"] impl crate::Resettable for CCER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNT (rw) register accessor: an alias for `Reg`"] pub type CNT = crate::Reg; #[doc = "counter"] pub mod cnt { #[doc = "Register `CNT` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNT` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CNT` reader - counter value"] pub type CNT_R = crate::FieldReader; #[doc = "Field `CNT` writer - counter value"] pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, CNT_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - counter value"] #[inline(always)] pub fn cnt(&self) -> CNT_R { CNT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - counter value"] #[inline(always)] #[must_use] pub fn cnt(&mut self) -> CNT_W<0> { CNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"] pub struct CNT_SPEC; impl crate::RegisterSpec for CNT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cnt::R](R) reader structure"] impl crate::Readable for CNT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"] impl crate::Writable for CNT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNT to value 0"] impl crate::Resettable for CNT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PSC (rw) register accessor: an alias for `Reg`"] pub type PSC = crate::Reg; #[doc = "prescaler"] pub mod psc { #[doc = "Register `PSC` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PSC` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PSC` reader - Prescaler value"] pub type PSC_R = crate::FieldReader; #[doc = "Field `PSC` writer - Prescaler value"] pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, PSC_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] pub fn psc(&self) -> PSC_R { PSC_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] #[must_use] pub fn psc(&mut self) -> PSC_W<0> { PSC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"] pub struct PSC_SPEC; impl crate::RegisterSpec for PSC_SPEC { type Ux = u32; } #[doc = "`read()` method returns [psc::R](R) reader structure"] impl crate::Readable for PSC_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"] impl crate::Writable for PSC_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PSC to value 0"] impl crate::Resettable for PSC_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ARR (rw) register accessor: an alias for `Reg`"] pub type ARR = crate::Reg; #[doc = "auto-reload register"] pub mod arr { #[doc = "Register `ARR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ARR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARR` reader - Auto-reload value"] pub type ARR_R = crate::FieldReader; #[doc = "Field `ARR` writer - Auto-reload value"] pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, ARR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] pub fn arr(&self) -> ARR_R { ARR_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] #[must_use] pub fn arr(&mut self) -> ARR_W<0> { ARR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "auto-reload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"] pub struct ARR_SPEC; impl crate::RegisterSpec for ARR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [arr::R](R) reader structure"] impl crate::Readable for ARR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"] impl crate::Writable for ARR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ARR to value 0"] impl crate::Resettable for ARR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR1 (rw) register accessor: an alias for `Reg`"] pub type CCR1 = crate::Reg; #[doc = "capture/compare register 1"] pub mod ccr1 { #[doc = "Register `CCR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR1` reader - Capture/Compare 1 value"] pub type CCR1_R = crate::FieldReader; #[doc = "Field `CCR1` writer - Capture/Compare 1 value"] pub type CCR1_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] pub fn ccr1(&self) -> CCR1_R { CCR1_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] #[must_use] pub fn ccr1(&mut self) -> CCR1_W<0> { CCR1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"] pub struct CCR1_SPEC; impl crate::RegisterSpec for CCR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr1::R](R) reader structure"] impl crate::Readable for CCR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"] impl crate::Writable for CCR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR1 to value 0"] impl crate::Resettable for CCR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR2 (rw) register accessor: an alias for `Reg`"] pub type CCR2 = crate::Reg; #[doc = "capture/compare register 2"] pub mod ccr2 { #[doc = "Register `CCR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR2` reader - Capture/Compare 2 value"] pub type CCR2_R = crate::FieldReader; #[doc = "Field `CCR2` writer - Capture/Compare 2 value"] pub type CCR2_W<'a, const O: u8> = crate::FieldWriter<'a, CCR2_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare 2 value"] #[inline(always)] pub fn ccr2(&self) -> CCR2_R { CCR2_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare 2 value"] #[inline(always)] #[must_use] pub fn ccr2(&mut self) -> CCR2_W<0> { CCR2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr2](index.html) module"] pub struct CCR2_SPEC; impl crate::RegisterSpec for CCR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr2::R](R) reader structure"] impl crate::Readable for CCR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr2::W](W) writer structure"] impl crate::Writable for CCR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR2 to value 0"] impl crate::Resettable for CCR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR3 (rw) register accessor: an alias for `Reg`"] pub type CCR3 = crate::Reg; #[doc = "capture/compare register 3"] pub mod ccr3 { #[doc = "Register `CCR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR3` reader - Capture/Compare value"] pub type CCR3_R = crate::FieldReader; #[doc = "Field `CCR3` writer - Capture/Compare value"] pub type CCR3_W<'a, const O: u8> = crate::FieldWriter<'a, CCR3_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] pub fn ccr3(&self) -> CCR3_R { CCR3_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] #[must_use] pub fn ccr3(&mut self) -> CCR3_W<0> { CCR3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr3](index.html) module"] pub struct CCR3_SPEC; impl crate::RegisterSpec for CCR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr3::R](R) reader structure"] impl crate::Readable for CCR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr3::W](W) writer structure"] impl crate::Writable for CCR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR3 to value 0"] impl crate::Resettable for CCR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR4 (rw) register accessor: an alias for `Reg`"] pub type CCR4 = crate::Reg; #[doc = "capture/compare register 4"] pub mod ccr4 { #[doc = "Register `CCR4` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR4` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR4` reader - Capture/Compare value"] pub type CCR4_R = crate::FieldReader; #[doc = "Field `CCR4` writer - Capture/Compare value"] pub type CCR4_W<'a, const O: u8> = crate::FieldWriter<'a, CCR4_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] pub fn ccr4(&self) -> CCR4_R { CCR4_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare value"] #[inline(always)] #[must_use] pub fn ccr4(&mut self) -> CCR4_W<0> { CCR4_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr4](index.html) module"] pub struct CCR4_SPEC; impl crate::RegisterSpec for CCR4_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr4::R](R) reader structure"] impl crate::Readable for CCR4_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr4::W](W) writer structure"] impl crate::Writable for CCR4_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR4 to value 0"] impl crate::Resettable for CCR4_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DCR (rw) register accessor: an alias for `Reg`"] pub type DCR = crate::Reg; #[doc = "DMA control register"] pub mod dcr { #[doc = "Register `DCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DBA` reader - DMA base address"] pub type DBA_R = crate::FieldReader; #[doc = "Field `DBA` writer - DMA base address"] pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, DCR_SPEC, 5, O>; #[doc = "Field `DBL` reader - DMA burst length"] pub type DBL_R = crate::FieldReader; #[doc = "Field `DBL` writer - DMA burst length"] pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, DCR_SPEC, 5, O>; impl R { #[doc = "Bits 0:4 - DMA base address"] #[inline(always)] pub fn dba(&self) -> DBA_R { DBA_R::new((self.bits & 0x1f) as u8) } #[doc = "Bits 8:12 - DMA burst length"] #[inline(always)] pub fn dbl(&self) -> DBL_R { DBL_R::new(((self.bits >> 8) & 0x1f) as u8) } } impl W { #[doc = "Bits 0:4 - DMA base address"] #[inline(always)] #[must_use] pub fn dba(&mut self) -> DBA_W<0> { DBA_W::new(self) } #[doc = "Bits 8:12 - DMA burst length"] #[inline(always)] #[must_use] pub fn dbl(&mut self) -> DBL_W<8> { DBL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"] pub struct DCR_SPEC; impl crate::RegisterSpec for DCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dcr::R](R) reader structure"] impl crate::Readable for DCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"] impl crate::Writable for DCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DCR to value 0"] impl crate::Resettable for DCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DMAR (rw) register accessor: an alias for `Reg`"] pub type DMAR = crate::Reg; #[doc = "DMA address for full transfer"] pub mod dmar { #[doc = "Register `DMAR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DMAR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMAB` reader - DMA register for burst accesses"] pub type DMAB_R = crate::FieldReader; #[doc = "Field `DMAB` writer - DMA register for burst accesses"] pub type DMAB_W<'a, const O: u8> = crate::FieldWriter<'a, DMAR_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA register for burst accesses"] #[inline(always)] pub fn dmab(&self) -> DMAB_R { DMAB_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - DMA register for burst accesses"] #[inline(always)] #[must_use] pub fn dmab(&mut self) -> DMAB_W<0> { DMAB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA address for full transfer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"] pub struct DMAR_SPEC; impl crate::RegisterSpec for DMAR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dmar::R](R) reader structure"] impl crate::Readable for DMAR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"] impl crate::Writable for DMAR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DMAR to value 0"] impl crate::Resettable for DMAR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General purpose timer"] pub struct TIM14 { _marker: PhantomData<*const ()>, } unsafe impl Send for TIM14 {} impl TIM14 { #[doc = r"Pointer to the register block"] pub const PTR: *const tim14::RegisterBlock = 0x4000_2000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const tim14::RegisterBlock { Self::PTR } } impl Deref for TIM14 { type Target = tim14::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for TIM14 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("TIM14").finish() } } #[doc = "General purpose timer"] pub mod tim14 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - TIM14 control register1"] pub cr1: CR1, _reserved1: [u8; 0x08], #[doc = "0x0c - DMA/Interrupt enable register"] pub dier: DIER, #[doc = "0x10 - status register"] pub sr: SR, #[doc = "0x14 - event generation register"] pub egr: EGR, _reserved_4_ccmr1: [u8; 0x04], _reserved5: [u8; 0x04], #[doc = "0x20 - capture/compare enable register"] pub ccer: CCER, #[doc = "0x24 - counter"] pub cnt: CNT, #[doc = "0x28 - prescaler"] pub psc: PSC, #[doc = "0x2c - auto-reload register"] pub arr: ARR, _reserved9: [u8; 0x04], #[doc = "0x34 - capture/compare register 1"] pub ccr1: CCR1, _reserved10: [u8; 0x18], #[doc = "0x50 - Option register"] pub or: OR, } impl RegisterBlock { #[doc = "0x18 - capture/compare mode register 1 (input mode)"] #[inline(always)] pub const fn ccmr1_input(&self) -> &CCMR1_INPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } #[doc = "0x18 - capture/compare mode register (output mode)"] #[inline(always)] pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "TIM14 control register1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CEN` reader - Counter enable"] pub type CEN_R = crate::BitReader; #[doc = "Field `CEN` writer - Counter enable"] pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `UDIS` reader - Update disable"] pub type UDIS_R = crate::BitReader; #[doc = "Field `UDIS` writer - Update disable"] pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `URS` reader - Update request source"] pub type URS_R = crate::BitReader; #[doc = "Field `URS` writer - Update request source"] pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `ARPE` reader - Auto-reload preload enable"] pub type ARPE_R = crate::BitReader; #[doc = "Field `ARPE` writer - Auto-reload preload enable"] pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CKD` reader - Prescaler factor"] pub type CKD_R = crate::FieldReader; #[doc = "Field `CKD` writer - Prescaler factor"] pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; impl R { #[doc = "Bit 0 - Counter enable"] #[inline(always)] pub fn cen(&self) -> CEN_R { CEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Update disable"] #[inline(always)] pub fn udis(&self) -> UDIS_R { UDIS_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Update request source"] #[inline(always)] pub fn urs(&self) -> URS_R { URS_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] pub fn arpe(&self) -> ARPE_R { ARPE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Prescaler factor"] #[inline(always)] pub fn ckd(&self) -> CKD_R { CKD_R::new(((self.bits >> 8) & 3) as u8) } } impl W { #[doc = "Bit 0 - Counter enable"] #[inline(always)] #[must_use] pub fn cen(&mut self) -> CEN_W<0> { CEN_W::new(self) } #[doc = "Bit 1 - Update disable"] #[inline(always)] #[must_use] pub fn udis(&mut self) -> UDIS_W<1> { UDIS_W::new(self) } #[doc = "Bit 2 - Update request source"] #[inline(always)] #[must_use] pub fn urs(&mut self) -> URS_W<2> { URS_W::new(self) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] #[must_use] pub fn arpe(&mut self) -> ARPE_W<7> { ARPE_W::new(self) } #[doc = "Bits 8:9 - Prescaler factor"] #[inline(always)] #[must_use] pub fn ckd(&mut self) -> CKD_W<8> { CKD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "TIM14 control register1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DIER (rw) register accessor: an alias for `Reg`"] pub type DIER = crate::Reg; #[doc = "DMA/Interrupt enable register"] pub mod dier { #[doc = "Register `DIER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DIER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIE` reader - Update interrupt enable"] pub type UIE_R = crate::BitReader; #[doc = "Field `UIE` writer - Update interrupt enable"] pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1IE` reader - Compare/"] pub type CC1IE_R = crate::BitReader; #[doc = "Field `CC1IE` writer - Compare/"] pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] pub fn uie(&self) -> UIE_R { UIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Compare/"] #[inline(always)] pub fn cc1ie(&self) -> CC1IE_R { CC1IE_R::new(((self.bits >> 1) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] #[must_use] pub fn uie(&mut self) -> UIE_W<0> { UIE_W::new(self) } #[doc = "Bit 1 - Compare/"] #[inline(always)] #[must_use] pub fn cc1ie(&mut self) -> CC1IE_W<1> { CC1IE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA/Interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"] pub struct DIER_SPEC; impl crate::RegisterSpec for DIER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dier::R](R) reader structure"] impl crate::Readable for DIER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"] impl crate::Writable for DIER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DIER to value 0"] impl crate::Resettable for DIER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIF` reader - Update interrupt flag"] pub type UIF_R = crate::BitReader; #[doc = "Field `UIF` writer - Update interrupt flag"] pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1IF` reader - Compare/capture 1 interrupt flag"] pub type CC1IF_R = crate::BitReader; #[doc = "Field `CC1IF` writer - Compare/capture 1 interrupt flag"] pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1OF` reader - Compare/capture 1 flag"] pub type CC1OF_R = crate::BitReader; #[doc = "Field `CC1OF` writer - Compare/capture 1 flag"] pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] pub fn uif(&self) -> UIF_R { UIF_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Compare/capture 1 interrupt flag"] #[inline(always)] pub fn cc1if(&self) -> CC1IF_R { CC1IF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 9 - Compare/capture 1 flag"] #[inline(always)] pub fn cc1of(&self) -> CC1OF_R { CC1OF_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] #[must_use] pub fn uif(&mut self) -> UIF_W<0> { UIF_W::new(self) } #[doc = "Bit 1 - Compare/capture 1 interrupt flag"] #[inline(always)] #[must_use] pub fn cc1if(&mut self) -> CC1IF_W<1> { CC1IF_W::new(self) } #[doc = "Bit 9 - Compare/capture 1 flag"] #[inline(always)] #[must_use] pub fn cc1of(&mut self) -> CC1OF_W<9> { CC1OF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EGR (w) register accessor: an alias for `Reg`"] pub type EGR = crate::Reg; #[doc = "event generation register"] pub mod egr { #[doc = "Register `EGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UG` writer - Update generation"] pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC1G` writer - Compare/capture1 event"] pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; impl W { #[doc = "Bit 0 - Update generation"] #[inline(always)] #[must_use] pub fn ug(&mut self) -> UG_W<0> { UG_W::new(self) } #[doc = "Bit 1 - Compare/capture1 event"] #[inline(always)] #[must_use] pub fn cc1g(&mut self) -> CC1G_W<1> { CC1G_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"] pub struct EGR_SPEC; impl crate::RegisterSpec for EGR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"] impl crate::Writable for EGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EGR to value 0"] impl crate::Resettable for EGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg`"] pub type CCMR1_OUTPUT = crate::Reg; #[doc = "capture/compare mode register (output mode)"] pub mod ccmr1_output { #[doc = "Register `CCMR1_Output` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Output` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC1FE` reader - Output Compare 1 fast enable"] pub type OC1FE_R = crate::BitReader; #[doc = "Field `OC1FE` writer - Output Compare 1 fast enable"] pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1PE` reader - Output Compare 1 preload enable"] pub type OC1PE_R = crate::BitReader; #[doc = "Field `OC1PE` writer - Output Compare 1 preload enable"] pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1M` reader - Output Compare 1 mode"] pub type OC1M_R = crate::FieldReader; #[doc = "Field `OC1M` writer - Output Compare 1 mode"] pub type OC1M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 3, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Output Compare 1 fast enable"] #[inline(always)] pub fn oc1fe(&self) -> OC1FE_R { OC1FE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] pub fn oc1pe(&self) -> OC1PE_R { OC1PE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] pub fn oc1m(&self) -> OC1M_R { OC1M_R::new(((self.bits >> 4) & 7) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bit 2 - Output Compare 1 fast enable"] #[inline(always)] #[must_use] pub fn oc1fe(&mut self) -> OC1FE_W<2> { OC1FE_W::new(self) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] #[must_use] pub fn oc1pe(&mut self) -> OC1PE_W<3> { OC1PE_W::new(self) } #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] #[must_use] pub fn oc1m(&mut self) -> OC1M_W<4> { OC1M_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"] pub struct CCMR1_OUTPUT_SPEC; impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"] impl crate::Readable for CCMR1_OUTPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"] impl crate::Writable for CCMR1_OUTPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Output to value 0"] impl crate::Resettable for CCMR1_OUTPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg`"] pub type CCMR1_INPUT = crate::Reg; #[doc = "capture/compare mode register 1 (input mode)"] pub mod ccmr1_input { #[doc = "Register `CCMR1_Input` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Input` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1PSC` reader - Input capture 1 prescaler"] pub type IC1PSC_R = crate::FieldReader; #[doc = "Field `IC1PSC` writer - Input capture 1 prescaler"] pub type IC1PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1F` reader - Input capture 1 filter"] pub type IC1F_R = crate::FieldReader; #[doc = "Field `IC1F` writer - Input capture 1 filter"] pub type IC1F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 4, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] pub fn ic1psc(&self) -> IC1PSC_R { IC1PSC_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] pub fn ic1f(&self) -> IC1F_R { IC1F_R::new(((self.bits >> 4) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] #[must_use] pub fn ic1psc(&mut self) -> IC1PSC_W<2> { IC1PSC_W::new(self) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] #[must_use] pub fn ic1f(&mut self) -> IC1F_W<4> { IC1F_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 1 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"] pub struct CCMR1_INPUT_SPEC; impl crate::RegisterSpec for CCMR1_INPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"] impl crate::Readable for CCMR1_INPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"] impl crate::Writable for CCMR1_INPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Input to value 0"] impl crate::Resettable for CCMR1_INPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCER (rw) register accessor: an alias for `Reg`"] pub type CCER = crate::Reg; #[doc = "capture/compare enable register"] pub mod ccer { #[doc = "Register `CCER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1E` reader - Capture/Compare 1 output enable"] pub type CC1E_R = crate::BitReader; #[doc = "Field `CC1E` writer - Capture/Compare 1 output enable"] pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity"] pub type CC1P_R = crate::BitReader; #[doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity"] pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1NP` reader - Capture/Compare 1 output Polarity"] pub type CC1NP_R = crate::BitReader; #[doc = "Field `CC1NP` writer - Capture/Compare 1 output Polarity"] pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; impl R { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] pub fn cc1e(&self) -> CC1E_R { CC1E_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1p(&self) -> CC1P_R { CC1P_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1np(&self) -> CC1NP_R { CC1NP_R::new(((self.bits >> 3) & 1) != 0) } } impl W { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] #[must_use] pub fn cc1e(&mut self) -> CC1E_W<0> { CC1E_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1p(&mut self) -> CC1P_W<1> { CC1P_W::new(self) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1np(&mut self) -> CC1NP_W<3> { CC1NP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"] pub struct CCER_SPEC; impl crate::RegisterSpec for CCER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccer::R](R) reader structure"] impl crate::Readable for CCER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"] impl crate::Writable for CCER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCER to value 0"] impl crate::Resettable for CCER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNT (rw) register accessor: an alias for `Reg`"] pub type CNT = crate::Reg; #[doc = "counter"] pub mod cnt { #[doc = "Register `CNT` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNT` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CNT` reader - counter value"] pub type CNT_R = crate::FieldReader; #[doc = "Field `CNT` writer - counter value"] pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, CNT_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - counter value"] #[inline(always)] pub fn cnt(&self) -> CNT_R { CNT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - counter value"] #[inline(always)] #[must_use] pub fn cnt(&mut self) -> CNT_W<0> { CNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"] pub struct CNT_SPEC; impl crate::RegisterSpec for CNT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cnt::R](R) reader structure"] impl crate::Readable for CNT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"] impl crate::Writable for CNT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNT to value 0"] impl crate::Resettable for CNT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PSC (rw) register accessor: an alias for `Reg`"] pub type PSC = crate::Reg; #[doc = "prescaler"] pub mod psc { #[doc = "Register `PSC` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PSC` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PSC` reader - Prescaler value"] pub type PSC_R = crate::FieldReader; #[doc = "Field `PSC` writer - Prescaler value"] pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, PSC_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] pub fn psc(&self) -> PSC_R { PSC_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] #[must_use] pub fn psc(&mut self) -> PSC_W<0> { PSC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"] pub struct PSC_SPEC; impl crate::RegisterSpec for PSC_SPEC { type Ux = u32; } #[doc = "`read()` method returns [psc::R](R) reader structure"] impl crate::Readable for PSC_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"] impl crate::Writable for PSC_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PSC to value 0"] impl crate::Resettable for PSC_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ARR (rw) register accessor: an alias for `Reg`"] pub type ARR = crate::Reg; #[doc = "auto-reload register"] pub mod arr { #[doc = "Register `ARR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ARR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARR` reader - Auto-reload value"] pub type ARR_R = crate::FieldReader; #[doc = "Field `ARR` writer - Auto-reload value"] pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, ARR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] pub fn arr(&self) -> ARR_R { ARR_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] #[must_use] pub fn arr(&mut self) -> ARR_W<0> { ARR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "auto-reload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"] pub struct ARR_SPEC; impl crate::RegisterSpec for ARR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [arr::R](R) reader structure"] impl crate::Readable for ARR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"] impl crate::Writable for ARR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ARR to value 0"] impl crate::Resettable for ARR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR1 (rw) register accessor: an alias for `Reg`"] pub type CCR1 = crate::Reg; #[doc = "capture/compare register 1"] pub mod ccr1 { #[doc = "Register `CCR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR1` reader - Capture/Compare 1 value"] pub type CCR1_R = crate::FieldReader; #[doc = "Field `CCR1` writer - Capture/Compare 1 value"] pub type CCR1_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] pub fn ccr1(&self) -> CCR1_R { CCR1_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] #[must_use] pub fn ccr1(&mut self) -> CCR1_W<0> { CCR1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"] pub struct CCR1_SPEC; impl crate::RegisterSpec for CCR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr1::R](R) reader structure"] impl crate::Readable for CCR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"] impl crate::Writable for CCR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR1 to value 0"] impl crate::Resettable for CCR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "OR (rw) register accessor: an alias for `Reg`"] pub type OR = crate::Reg; #[doc = "Option register"] pub mod or { #[doc = "Register `OR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TI1_RMP` reader - TIM14 channel1 input remap"] pub type TI1_RMP_R = crate::FieldReader; #[doc = "Field `TI1_RMP` writer - TIM14 channel1 input remap"] pub type TI1_RMP_W<'a, const O: u8> = crate::FieldWriter<'a, OR_SPEC, 2, O>; impl R { #[doc = "Bits 0:1 - TIM14 channel1 input remap"] #[inline(always)] pub fn ti1_rmp(&self) -> TI1_RMP_R { TI1_RMP_R::new((self.bits & 3) as u8) } } impl W { #[doc = "Bits 0:1 - TIM14 channel1 input remap"] #[inline(always)] #[must_use] pub fn ti1_rmp(&mut self) -> TI1_RMP_W<0> { TI1_RMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Option register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [or](index.html) module"] pub struct OR_SPEC; impl crate::RegisterSpec for OR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [or::R](R) reader structure"] impl crate::Readable for OR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [or::W](W) writer structure"] impl crate::Writable for OR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OR to value 0"] impl crate::Resettable for OR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General purpose timer"] pub struct TIM16 { _marker: PhantomData<*const ()>, } unsafe impl Send for TIM16 {} impl TIM16 { #[doc = r"Pointer to the register block"] pub const PTR: *const tim16::RegisterBlock = 0x4001_4400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const tim16::RegisterBlock { Self::PTR } } impl Deref for TIM16 { type Target = tim16::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for TIM16 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("TIM16").finish() } } #[doc = "General purpose timer"] pub mod tim16 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - TIM16 control register1"] pub cr1: CR1, #[doc = "0x04 - control register 2"] pub cr2: CR2, _reserved2: [u8; 0x04], #[doc = "0x0c - DMA/Interrupt enable register"] pub dier: DIER, #[doc = "0x10 - status register"] pub sr: SR, #[doc = "0x14 - event generation register"] pub egr: EGR, _reserved_5_ccmr1: [u8; 0x04], _reserved6: [u8; 0x04], #[doc = "0x20 - capture/compare enable register"] pub ccer: CCER, #[doc = "0x24 - counter"] pub cnt: CNT, #[doc = "0x28 - prescaler"] pub psc: PSC, #[doc = "0x2c - auto-reload register"] pub arr: ARR, #[doc = "0x30 - repetition counter register"] pub rcr: RCR, #[doc = "0x34 - capture/compare register 1"] pub ccr1: CCR1, _reserved12: [u8; 0x0c], #[doc = "0x44 - break and dead-time register"] pub bdtr: BDTR, #[doc = "0x48 - DMA control register"] pub dcr: DCR, #[doc = "0x4c - DMA address for full transfer"] pub dmar: DMAR, } impl RegisterBlock { #[doc = "0x18 - capture/compare mode register 1 (input mode)"] #[inline(always)] pub const fn ccmr1_input(&self) -> &CCMR1_INPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } #[doc = "0x18 - capture/compare mode register (output mode)"] #[inline(always)] pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT { unsafe { &*(self as *const Self).cast::().add(24usize).cast() } } } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "TIM16 control register1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CEN` reader - Counter enable"] pub type CEN_R = crate::BitReader; #[doc = "Field `CEN` writer - Counter enable"] pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `UDIS` reader - Update disable"] pub type UDIS_R = crate::BitReader; #[doc = "Field `UDIS` writer - Update disable"] pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `URS` reader - Update request source"] pub type URS_R = crate::BitReader; #[doc = "Field `URS` writer - Update request source"] pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `OPM` reader - One pulse mode"] pub type OPM_R = crate::BitReader; #[doc = "Field `OPM` writer - One pulse mode"] pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `ARPE` reader - Auto-reload preload enable"] pub type ARPE_R = crate::BitReader; #[doc = "Field `ARPE` writer - Auto-reload preload enable"] pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CKD` reader - Prescaler factor"] pub type CKD_R = crate::FieldReader; #[doc = "Field `CKD` writer - Prescaler factor"] pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 2, O>; impl R { #[doc = "Bit 0 - Counter enable"] #[inline(always)] pub fn cen(&self) -> CEN_R { CEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Update disable"] #[inline(always)] pub fn udis(&self) -> UDIS_R { UDIS_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Update request source"] #[inline(always)] pub fn urs(&self) -> URS_R { URS_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - One pulse mode"] #[inline(always)] pub fn opm(&self) -> OPM_R { OPM_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] pub fn arpe(&self) -> ARPE_R { ARPE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Prescaler factor"] #[inline(always)] pub fn ckd(&self) -> CKD_R { CKD_R::new(((self.bits >> 8) & 3) as u8) } } impl W { #[doc = "Bit 0 - Counter enable"] #[inline(always)] #[must_use] pub fn cen(&mut self) -> CEN_W<0> { CEN_W::new(self) } #[doc = "Bit 1 - Update disable"] #[inline(always)] #[must_use] pub fn udis(&mut self) -> UDIS_W<1> { UDIS_W::new(self) } #[doc = "Bit 2 - Update request source"] #[inline(always)] #[must_use] pub fn urs(&mut self) -> URS_W<2> { URS_W::new(self) } #[doc = "Bit 3 - One pulse mode"] #[inline(always)] #[must_use] pub fn opm(&mut self) -> OPM_W<3> { OPM_W::new(self) } #[doc = "Bit 7 - Auto-reload preload enable"] #[inline(always)] #[must_use] pub fn arpe(&mut self) -> ARPE_W<7> { ARPE_W::new(self) } #[doc = "Bits 8:9 - Prescaler factor"] #[inline(always)] #[must_use] pub fn ckd(&mut self) -> CKD_W<8> { CKD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "TIM16 control register1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCPC` reader - Capture/compare preloaded control"] pub type CCPC_R = crate::BitReader; #[doc = "Field `CCPC` writer - Capture/compare preloaded control"] pub type CCPC_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `CCDS` reader - Capture/compare DMA selection"] pub type CCDS_R = crate::BitReader; #[doc = "Field `CCDS` writer - Capture/compare DMA selection"] pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS1` reader - Output Idle state 1"] pub type OIS1_R = crate::BitReader; #[doc = "Field `OIS1` writer - Output Idle state 1"] pub type OIS1_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `OIS1N` reader - Output Idle state 1"] pub type OIS1N_R = crate::BitReader; #[doc = "Field `OIS1N` writer - Output Idle state 1"] pub type OIS1N_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; impl R { #[doc = "Bit 0 - Capture/compare preloaded control"] #[inline(always)] pub fn ccpc(&self) -> CCPC_R { CCPC_R::new((self.bits & 1) != 0) } #[doc = "Bit 3 - Capture/compare DMA selection"] #[inline(always)] pub fn ccds(&self) -> CCDS_R { CCDS_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 8 - Output Idle state 1"] #[inline(always)] pub fn ois1(&self) -> OIS1_R { OIS1_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Output Idle state 1"] #[inline(always)] pub fn ois1n(&self) -> OIS1N_R { OIS1N_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bit 0 - Capture/compare preloaded control"] #[inline(always)] #[must_use] pub fn ccpc(&mut self) -> CCPC_W<0> { CCPC_W::new(self) } #[doc = "Bit 3 - Capture/compare DMA selection"] #[inline(always)] #[must_use] pub fn ccds(&mut self) -> CCDS_W<3> { CCDS_W::new(self) } #[doc = "Bit 8 - Output Idle state 1"] #[inline(always)] #[must_use] pub fn ois1(&mut self) -> OIS1_W<8> { OIS1_W::new(self) } #[doc = "Bit 9 - Output Idle state 1"] #[inline(always)] #[must_use] pub fn ois1n(&mut self) -> OIS1N_W<9> { OIS1N_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DIER (rw) register accessor: an alias for `Reg`"] pub type DIER = crate::Reg; #[doc = "DMA/Interrupt enable register"] pub mod dier { #[doc = "Register `DIER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DIER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIE` reader - Update interrupt enable"] pub type UIE_R = crate::BitReader; #[doc = "Field `UIE` writer - Update interrupt enable"] pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable"] pub type CC1IE_R = crate::BitReader; #[doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable"] pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `COMIE` reader - Com interrupt enable"] pub type COMIE_R = crate::BitReader; #[doc = "Field `COMIE` writer - Com interrupt enable"] pub type COMIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `BIE` reader - Break interrupt enable"] pub type BIE_R = crate::BitReader; #[doc = "Field `BIE` writer - Break interrupt enable"] pub type BIE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `UDE` reader - Update DMA request enable"] pub type UDE_R = crate::BitReader; #[doc = "Field `UDE` writer - Update DMA request enable"] pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; #[doc = "Field `CC1DE` reader - Compare/capture DMA requeset enable"] pub type CC1DE_R = crate::BitReader; #[doc = "Field `CC1DE` writer - Compare/capture DMA requeset enable"] pub type CC1DE_W<'a, const O: u8> = crate::BitWriter<'a, DIER_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] pub fn uie(&self) -> UIE_R { UIE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 interrupt enable"] #[inline(always)] pub fn cc1ie(&self) -> CC1IE_R { CC1IE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 5 - Com interrupt enable"] #[inline(always)] pub fn comie(&self) -> COMIE_R { COMIE_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 7 - Break interrupt enable"] #[inline(always)] pub fn bie(&self) -> BIE_R { BIE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Update DMA request enable"] #[inline(always)] pub fn ude(&self) -> UDE_R { UDE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Compare/capture DMA requeset enable"] #[inline(always)] pub fn cc1de(&self) -> CC1DE_R { CC1DE_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt enable"] #[inline(always)] #[must_use] pub fn uie(&mut self) -> UIE_W<0> { UIE_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 interrupt enable"] #[inline(always)] #[must_use] pub fn cc1ie(&mut self) -> CC1IE_W<1> { CC1IE_W::new(self) } #[doc = "Bit 5 - Com interrupt enable"] #[inline(always)] #[must_use] pub fn comie(&mut self) -> COMIE_W<5> { COMIE_W::new(self) } #[doc = "Bit 7 - Break interrupt enable"] #[inline(always)] #[must_use] pub fn bie(&mut self) -> BIE_W<7> { BIE_W::new(self) } #[doc = "Bit 8 - Update DMA request enable"] #[inline(always)] #[must_use] pub fn ude(&mut self) -> UDE_W<8> { UDE_W::new(self) } #[doc = "Bit 9 - Compare/capture DMA requeset enable"] #[inline(always)] #[must_use] pub fn cc1de(&mut self) -> CC1DE_W<9> { CC1DE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA/Interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"] pub struct DIER_SPEC; impl crate::RegisterSpec for DIER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dier::R](R) reader structure"] impl crate::Readable for DIER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"] impl crate::Writable for DIER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DIER to value 0"] impl crate::Resettable for DIER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UIF` reader - Update interrupt flag"] pub type UIF_R = crate::BitReader; #[doc = "Field `UIF` writer - Update interrupt flag"] pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1IF` reader - Capture/Compare 1 interrupt flag"] pub type CC1IF_R = crate::BitReader; #[doc = "Field `CC1IF` writer - Capture/Compare 1 interrupt flag"] pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `COMIF` reader - Com interrupt flag"] pub type COMIF_R = crate::BitReader; #[doc = "Field `COMIF` writer - Com interrupt flag"] pub type COMIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `BIF` reader - Break interrupt flag"] pub type BIF_R = crate::BitReader; #[doc = "Field `BIF` writer - Break interrupt flag"] pub type BIF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `CC1OF` reader - Update interrupt flag"] pub type CC1OF_R = crate::BitReader; #[doc = "Field `CC1OF` writer - Update interrupt flag"] pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] pub fn uif(&self) -> UIF_R { UIF_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 interrupt flag"] #[inline(always)] pub fn cc1if(&self) -> CC1IF_R { CC1IF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 5 - Com interrupt flag"] #[inline(always)] pub fn comif(&self) -> COMIF_R { COMIF_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 7 - Break interrupt flag"] #[inline(always)] pub fn bif(&self) -> BIF_R { BIF_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 9 - Update interrupt flag"] #[inline(always)] pub fn cc1of(&self) -> CC1OF_R { CC1OF_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bit 0 - Update interrupt flag"] #[inline(always)] #[must_use] pub fn uif(&mut self) -> UIF_W<0> { UIF_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 interrupt flag"] #[inline(always)] #[must_use] pub fn cc1if(&mut self) -> CC1IF_W<1> { CC1IF_W::new(self) } #[doc = "Bit 5 - Com interrupt flag"] #[inline(always)] #[must_use] pub fn comif(&mut self) -> COMIF_W<5> { COMIF_W::new(self) } #[doc = "Bit 7 - Break interrupt flag"] #[inline(always)] #[must_use] pub fn bif(&mut self) -> BIF_W<7> { BIF_W::new(self) } #[doc = "Bit 9 - Update interrupt flag"] #[inline(always)] #[must_use] pub fn cc1of(&mut self) -> CC1OF_W<9> { CC1OF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "EGR (w) register accessor: an alias for `Reg`"] pub type EGR = crate::Reg; #[doc = "event generation register"] pub mod egr { #[doc = "Register `EGR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `UG` writer - Update generation"] pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `CC1G` writer - Capture/Compare 1 generation"] pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `COMG` writer - COM evnet generation"] pub type COMG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; #[doc = "Field `BG` writer - Break event generation"] pub type BG_W<'a, const O: u8> = crate::BitWriter<'a, EGR_SPEC, O>; impl W { #[doc = "Bit 0 - Update generation"] #[inline(always)] #[must_use] pub fn ug(&mut self) -> UG_W<0> { UG_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 generation"] #[inline(always)] #[must_use] pub fn cc1g(&mut self) -> CC1G_W<1> { CC1G_W::new(self) } #[doc = "Bit 5 - COM evnet generation"] #[inline(always)] #[must_use] pub fn comg(&mut self) -> COMG_W<5> { COMG_W::new(self) } #[doc = "Bit 7 - Break event generation"] #[inline(always)] #[must_use] pub fn bg(&mut self) -> BG_W<7> { BG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"] pub struct EGR_SPEC; impl crate::RegisterSpec for EGR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"] impl crate::Writable for EGR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets EGR to value 0"] impl crate::Resettable for EGR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg`"] pub type CCMR1_OUTPUT = crate::Reg; #[doc = "capture/compare mode register (output mode)"] pub mod ccmr1_output { #[doc = "Register `CCMR1_Output` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Output` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 2, O>; #[doc = "Field `OC1FE` reader - Output Compare 1 fast enable"] pub type OC1FE_R = crate::BitReader; #[doc = "Field `OC1FE` writer - Output Compare 1 fast enable"] pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1PE` reader - Output Compare 1 preload enable"] pub type OC1PE_R = crate::BitReader; #[doc = "Field `OC1PE` writer - Output Compare 1 preload enable"] pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, CCMR1_OUTPUT_SPEC, O>; #[doc = "Field `OC1M` reader - Output Compare 1 mode"] pub type OC1M_R = crate::FieldReader; #[doc = "Field `OC1M` writer - Output Compare 1 mode"] pub type OC1M_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_OUTPUT_SPEC, 3, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Output Compare 1 fast enable"] #[inline(always)] pub fn oc1fe(&self) -> OC1FE_R { OC1FE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] pub fn oc1pe(&self) -> OC1PE_R { OC1PE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] pub fn oc1m(&self) -> OC1M_R { OC1M_R::new(((self.bits >> 4) & 7) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bit 2 - Output Compare 1 fast enable"] #[inline(always)] #[must_use] pub fn oc1fe(&mut self) -> OC1FE_W<2> { OC1FE_W::new(self) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] #[must_use] pub fn oc1pe(&mut self) -> OC1PE_W<3> { OC1PE_W::new(self) } #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] #[must_use] pub fn oc1m(&mut self) -> OC1M_W<4> { OC1M_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"] pub struct CCMR1_OUTPUT_SPEC; impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"] impl crate::Readable for CCMR1_OUTPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"] impl crate::Writable for CCMR1_OUTPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Output to value 0"] impl crate::Resettable for CCMR1_OUTPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg`"] pub type CCMR1_INPUT = crate::Reg; #[doc = "capture/compare mode register 1 (input mode)"] pub mod ccmr1_input { #[doc = "Register `CCMR1_Input` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCMR1_Input` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1S` reader - Capture/Compare 1 selection"] pub type CC1S_R = crate::FieldReader; #[doc = "Field `CC1S` writer - Capture/Compare 1 selection"] pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1PSC` reader - Input capture 1 prescaler"] pub type IC1PSC_R = crate::FieldReader; #[doc = "Field `IC1PSC` writer - Input capture 1 prescaler"] pub type IC1PSC_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 2, O>; #[doc = "Field `IC1F` reader - Input capture 1 filter"] pub type IC1F_R = crate::FieldReader; #[doc = "Field `IC1F` writer - Input capture 1 filter"] pub type IC1F_W<'a, const O: u8> = crate::FieldWriter<'a, CCMR1_INPUT_SPEC, 4, O>; impl R { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 3) as u8) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] pub fn ic1psc(&self) -> IC1PSC_R { IC1PSC_R::new(((self.bits >> 2) & 3) as u8) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] pub fn ic1f(&self) -> IC1F_R { IC1F_R::new(((self.bits >> 4) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] #[must_use] pub fn cc1s(&mut self) -> CC1S_W<0> { CC1S_W::new(self) } #[doc = "Bits 2:3 - Input capture 1 prescaler"] #[inline(always)] #[must_use] pub fn ic1psc(&mut self) -> IC1PSC_W<2> { IC1PSC_W::new(self) } #[doc = "Bits 4:7 - Input capture 1 filter"] #[inline(always)] #[must_use] pub fn ic1f(&mut self) -> IC1F_W<4> { IC1F_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare mode register 1 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"] pub struct CCMR1_INPUT_SPEC; impl crate::RegisterSpec for CCMR1_INPUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"] impl crate::Readable for CCMR1_INPUT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"] impl crate::Writable for CCMR1_INPUT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCMR1_Input to value 0"] impl crate::Resettable for CCMR1_INPUT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCER (rw) register accessor: an alias for `Reg`"] pub type CCER = crate::Reg; #[doc = "capture/compare enable register"] pub mod ccer { #[doc = "Register `CCER` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCER` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CC1E` reader - Capture/Compare 1 output enable"] pub type CC1E_R = crate::BitReader; #[doc = "Field `CC1E` writer - Capture/Compare 1 output enable"] pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity"] pub type CC1P_R = crate::BitReader; #[doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity"] pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1NE` reader - Capture/Compare 1 complementary output enable"] pub type CC1NE_R = crate::BitReader; #[doc = "Field `CC1NE` writer - Capture/Compare 1 complementary output enable"] pub type CC1NE_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; #[doc = "Field `CC1NP` reader - Capture/Compare 1 output Polarity"] pub type CC1NP_R = crate::BitReader; #[doc = "Field `CC1NP` writer - Capture/Compare 1 output Polarity"] pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, CCER_SPEC, O>; impl R { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] pub fn cc1e(&self) -> CC1E_R { CC1E_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1p(&self) -> CC1P_R { CC1P_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Capture/Compare 1 complementary output enable"] #[inline(always)] pub fn cc1ne(&self) -> CC1NE_R { CC1NE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] pub fn cc1np(&self) -> CC1NP_R { CC1NP_R::new(((self.bits >> 3) & 1) != 0) } } impl W { #[doc = "Bit 0 - Capture/Compare 1 output enable"] #[inline(always)] #[must_use] pub fn cc1e(&mut self) -> CC1E_W<0> { CC1E_W::new(self) } #[doc = "Bit 1 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1p(&mut self) -> CC1P_W<1> { CC1P_W::new(self) } #[doc = "Bit 2 - Capture/Compare 1 complementary output enable"] #[inline(always)] #[must_use] pub fn cc1ne(&mut self) -> CC1NE_W<2> { CC1NE_W::new(self) } #[doc = "Bit 3 - Capture/Compare 1 output Polarity"] #[inline(always)] #[must_use] pub fn cc1np(&mut self) -> CC1NP_W<3> { CC1NP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"] pub struct CCER_SPEC; impl crate::RegisterSpec for CCER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccer::R](R) reader structure"] impl crate::Readable for CCER_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"] impl crate::Writable for CCER_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCER to value 0"] impl crate::Resettable for CCER_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNT (rw) register accessor: an alias for `Reg`"] pub type CNT = crate::Reg; #[doc = "counter"] pub mod cnt { #[doc = "Register `CNT` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNT` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CNT` reader - counter value"] pub type CNT_R = crate::FieldReader; #[doc = "Field `CNT` writer - counter value"] pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, CNT_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - counter value"] #[inline(always)] pub fn cnt(&self) -> CNT_R { CNT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - counter value"] #[inline(always)] #[must_use] pub fn cnt(&mut self) -> CNT_W<0> { CNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"] pub struct CNT_SPEC; impl crate::RegisterSpec for CNT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cnt::R](R) reader structure"] impl crate::Readable for CNT_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"] impl crate::Writable for CNT_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNT to value 0"] impl crate::Resettable for CNT_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PSC (rw) register accessor: an alias for `Reg`"] pub type PSC = crate::Reg; #[doc = "prescaler"] pub mod psc { #[doc = "Register `PSC` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PSC` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PSC` reader - Prescaler value"] pub type PSC_R = crate::FieldReader; #[doc = "Field `PSC` writer - Prescaler value"] pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, PSC_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] pub fn psc(&self) -> PSC_R { PSC_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Prescaler value"] #[inline(always)] #[must_use] pub fn psc(&mut self) -> PSC_W<0> { PSC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"] pub struct PSC_SPEC; impl crate::RegisterSpec for PSC_SPEC { type Ux = u32; } #[doc = "`read()` method returns [psc::R](R) reader structure"] impl crate::Readable for PSC_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"] impl crate::Writable for PSC_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PSC to value 0"] impl crate::Resettable for PSC_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "ARR (rw) register accessor: an alias for `Reg`"] pub type ARR = crate::Reg; #[doc = "auto-reload register"] pub mod arr { #[doc = "Register `ARR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ARR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ARR` reader - Auto-reload value"] pub type ARR_R = crate::FieldReader; #[doc = "Field `ARR` writer - Auto-reload value"] pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, ARR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] pub fn arr(&self) -> ARR_R { ARR_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Auto-reload value"] #[inline(always)] #[must_use] pub fn arr(&mut self) -> ARR_W<0> { ARR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "auto-reload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"] pub struct ARR_SPEC; impl crate::RegisterSpec for ARR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [arr::R](R) reader structure"] impl crate::Readable for ARR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"] impl crate::Writable for ARR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ARR to value 0"] impl crate::Resettable for ARR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "RCR (rw) register accessor: an alias for `Reg`"] pub type RCR = crate::Reg; #[doc = "repetition counter register"] pub mod rcr { #[doc = "Register `RCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `RCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `REP` reader - Repetition counter value"] pub type REP_R = crate::FieldReader; #[doc = "Field `REP` writer - Repetition counter value"] pub type REP_W<'a, const O: u8> = crate::FieldWriter<'a, RCR_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - Repetition counter value"] #[inline(always)] pub fn rep(&self) -> REP_R { REP_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - Repetition counter value"] #[inline(always)] #[must_use] pub fn rep(&mut self) -> REP_W<0> { REP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "repetition counter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcr](index.html) module"] pub struct RCR_SPEC; impl crate::RegisterSpec for RCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [rcr::R](R) reader structure"] impl crate::Readable for RCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [rcr::W](W) writer structure"] impl crate::Writable for RCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets RCR to value 0"] impl crate::Resettable for RCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR1 (rw) register accessor: an alias for `Reg`"] pub type CCR1 = crate::Reg; #[doc = "capture/compare register 1"] pub mod ccr1 { #[doc = "Register `CCR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR1` reader - Capture/Compare 1 value"] pub type CCR1_R = crate::FieldReader; #[doc = "Field `CCR1` writer - Capture/Compare 1 value"] pub type CCR1_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] pub fn ccr1(&self) -> CCR1_R { CCR1_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Capture/Compare 1 value"] #[inline(always)] #[must_use] pub fn ccr1(&mut self) -> CCR1_W<0> { CCR1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "capture/compare register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"] pub struct CCR1_SPEC; impl crate::RegisterSpec for CCR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr1::R](R) reader structure"] impl crate::Readable for CCR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"] impl crate::Writable for CCR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR1 to value 0"] impl crate::Resettable for CCR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "BDTR (rw) register accessor: an alias for `Reg`"] pub type BDTR = crate::Reg; #[doc = "break and dead-time register"] pub mod bdtr { #[doc = "Register `BDTR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `BDTR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DTG` reader - Dead-time generator setup"] pub type DTG_R = crate::FieldReader; #[doc = "Field `DTG` writer - Dead-time generator setup"] pub type DTG_W<'a, const O: u8> = crate::FieldWriter<'a, BDTR_SPEC, 8, O>; #[doc = "Field `LOCK` reader - Lock configuration"] pub type LOCK_R = crate::FieldReader; #[doc = "Field `LOCK` writer - Lock configuration"] pub type LOCK_W<'a, const O: u8> = crate::FieldWriter<'a, BDTR_SPEC, 2, O>; #[doc = "Field `OSSI` reader - Off-state selection for Idle mode"] pub type OSSI_R = crate::BitReader; #[doc = "Field `OSSI` writer - Off-state selection for Idle mode"] pub type OSSI_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `OSSR` reader - Off-state selection for Run mode"] pub type OSSR_R = crate::BitReader; #[doc = "Field `OSSR` writer - Off-state selection for Run mode"] pub type OSSR_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `BKE` reader - Break enable"] pub type BKE_R = crate::BitReader; #[doc = "Field `BKE` writer - Break enable"] pub type BKE_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `BKP` reader - Break polarity"] pub type BKP_R = crate::BitReader; #[doc = "Field `BKP` writer - Break polarity"] pub type BKP_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `AOE` reader - Automatic output enable"] pub type AOE_R = crate::BitReader; #[doc = "Field `AOE` writer - Automatic output enable"] pub type AOE_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; #[doc = "Field `MOE` reader - Main output enable"] pub type MOE_R = crate::BitReader; #[doc = "Field `MOE` writer - Main output enable"] pub type MOE_W<'a, const O: u8> = crate::BitWriter<'a, BDTR_SPEC, O>; impl R { #[doc = "Bits 0:7 - Dead-time generator setup"] #[inline(always)] pub fn dtg(&self) -> DTG_R { DTG_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:9 - Lock configuration"] #[inline(always)] pub fn lock(&self) -> LOCK_R { LOCK_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bit 10 - Off-state selection for Idle mode"] #[inline(always)] pub fn ossi(&self) -> OSSI_R { OSSI_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Off-state selection for Run mode"] #[inline(always)] pub fn ossr(&self) -> OSSR_R { OSSR_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Break enable"] #[inline(always)] pub fn bke(&self) -> BKE_R { BKE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Break polarity"] #[inline(always)] pub fn bkp(&self) -> BKP_R { BKP_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Automatic output enable"] #[inline(always)] pub fn aoe(&self) -> AOE_R { AOE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Main output enable"] #[inline(always)] pub fn moe(&self) -> MOE_R { MOE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:7 - Dead-time generator setup"] #[inline(always)] #[must_use] pub fn dtg(&mut self) -> DTG_W<0> { DTG_W::new(self) } #[doc = "Bits 8:9 - Lock configuration"] #[inline(always)] #[must_use] pub fn lock(&mut self) -> LOCK_W<8> { LOCK_W::new(self) } #[doc = "Bit 10 - Off-state selection for Idle mode"] #[inline(always)] #[must_use] pub fn ossi(&mut self) -> OSSI_W<10> { OSSI_W::new(self) } #[doc = "Bit 11 - Off-state selection for Run mode"] #[inline(always)] #[must_use] pub fn ossr(&mut self) -> OSSR_W<11> { OSSR_W::new(self) } #[doc = "Bit 12 - Break enable"] #[inline(always)] #[must_use] pub fn bke(&mut self) -> BKE_W<12> { BKE_W::new(self) } #[doc = "Bit 13 - Break polarity"] #[inline(always)] #[must_use] pub fn bkp(&mut self) -> BKP_W<13> { BKP_W::new(self) } #[doc = "Bit 14 - Automatic output enable"] #[inline(always)] #[must_use] pub fn aoe(&mut self) -> AOE_W<14> { AOE_W::new(self) } #[doc = "Bit 15 - Main output enable"] #[inline(always)] #[must_use] pub fn moe(&mut self) -> MOE_W<15> { MOE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "break and dead-time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bdtr](index.html) module"] pub struct BDTR_SPEC; impl crate::RegisterSpec for BDTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [bdtr::R](R) reader structure"] impl crate::Readable for BDTR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [bdtr::W](W) writer structure"] impl crate::Writable for BDTR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets BDTR to value 0"] impl crate::Resettable for BDTR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DCR (rw) register accessor: an alias for `Reg`"] pub type DCR = crate::Reg; #[doc = "DMA control register"] pub mod dcr { #[doc = "Register `DCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DBA` reader - DMA base address"] pub type DBA_R = crate::FieldReader; #[doc = "Field `DBA` writer - DMA base address"] pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, DCR_SPEC, 5, O>; #[doc = "Field `DBL` reader - DMA burst length"] pub type DBL_R = crate::FieldReader; #[doc = "Field `DBL` writer - DMA burst length"] pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, DCR_SPEC, 5, O>; impl R { #[doc = "Bits 0:4 - DMA base address"] #[inline(always)] pub fn dba(&self) -> DBA_R { DBA_R::new((self.bits & 0x1f) as u8) } #[doc = "Bits 8:12 - DMA burst length"] #[inline(always)] pub fn dbl(&self) -> DBL_R { DBL_R::new(((self.bits >> 8) & 0x1f) as u8) } } impl W { #[doc = "Bits 0:4 - DMA base address"] #[inline(always)] #[must_use] pub fn dba(&mut self) -> DBA_W<0> { DBA_W::new(self) } #[doc = "Bits 8:12 - DMA burst length"] #[inline(always)] #[must_use] pub fn dbl(&mut self) -> DBL_W<8> { DBL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"] pub struct DCR_SPEC; impl crate::RegisterSpec for DCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dcr::R](R) reader structure"] impl crate::Readable for DCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"] impl crate::Writable for DCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DCR to value 0"] impl crate::Resettable for DCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DMAR (rw) register accessor: an alias for `Reg`"] pub type DMAR = crate::Reg; #[doc = "DMA address for full transfer"] pub mod dmar { #[doc = "Register `DMAR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DMAR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMAB` reader - DMA register for burst accesses"] pub type DMAB_R = crate::FieldReader; #[doc = "Field `DMAB` writer - DMA register for burst accesses"] pub type DMAB_W<'a, const O: u8> = crate::FieldWriter<'a, DMAR_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA register for burst accesses"] #[inline(always)] pub fn dmab(&self) -> DMAB_R { DMAB_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - DMA register for burst accesses"] #[inline(always)] #[must_use] pub fn dmab(&mut self) -> DMAB_W<0> { DMAB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA address for full transfer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"] pub struct DMAR_SPEC; impl crate::RegisterSpec for DMAR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dmar::R](R) reader structure"] impl crate::Readable for DMAR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"] impl crate::Writable for DMAR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DMAR to value 0"] impl crate::Resettable for DMAR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "General purpose timer"] pub struct TIM17 { _marker: PhantomData<*const ()>, } unsafe impl Send for TIM17 {} impl TIM17 { #[doc = r"Pointer to the register block"] pub const PTR: *const tim16::RegisterBlock = 0x4001_4800 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const tim16::RegisterBlock { Self::PTR } } impl Deref for TIM17 { type Target = tim16::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for TIM17 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("TIM17").finish() } } #[doc = "General purpose timer"] pub use self::tim16 as tim17; #[doc = "System configuration controller"] pub struct SYSCFG { _marker: PhantomData<*const ()>, } unsafe impl Send for SYSCFG {} impl SYSCFG { #[doc = r"Pointer to the register block"] pub const PTR: *const syscfg::RegisterBlock = 0x4001_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const syscfg::RegisterBlock { Self::PTR } } impl Deref for SYSCFG { type Target = syscfg::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for SYSCFG { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("SYSCFG").finish() } } #[doc = "System configuration controller"] pub mod syscfg { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - SYSCFG configuration register 1"] pub cfgr1: CFGR1, _reserved1: [u8; 0x14], #[doc = "0x18 - SYSCFG configuration register 2"] pub cfgr2: CFGR2, #[doc = "0x1c - SYSCFG configuration register 3"] pub cfgr3: CFGR3, } #[doc = "CFGR1 (rw) register accessor: an alias for `Reg`"] pub type CFGR1 = crate::Reg; #[doc = "SYSCFG configuration register 1"] pub mod cfgr1 { #[doc = "Register `CFGR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `MEM_MODE` reader - Memory mapping selection bits"] pub type MEM_MODE_R = crate::FieldReader; #[doc = "Field `MEM_MODE` writer - Memory mapping selection bits"] pub type MEM_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR1_SPEC, 2, O>; #[doc = "Field `I2C_PA2_ANF` reader - Analog filter enable control driving capability activation bits PA2"] pub type I2C_PA2_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA2_ANF` writer - Analog filter enable control driving capability activation bits PA2"] pub type I2C_PA2_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA3_ANF` reader - Analog filter enable control driving capability activation bits PA3"] pub type I2C_PA3_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA3_ANF` writer - Analog filter enable control driving capability activation bits PA3"] pub type I2C_PA3_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA7_ANF` reader - Analog filter enable control driving capability activation bits PA7"] pub type I2C_PA7_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA7_ANF` writer - Analog filter enable control driving capability activation bits PA7"] pub type I2C_PA7_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA8_ANF` reader - Analog filter enable control driving capability activation bits PA8"] pub type I2C_PA8_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA8_ANF` writer - Analog filter enable control driving capability activation bits PA8"] pub type I2C_PA8_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA9_ANF` reader - Analog filter enable control driving capability activation bits PA9"] pub type I2C_PA9_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA9_ANF` writer - Analog filter enable control driving capability activation bits PA9"] pub type I2C_PA9_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA10_ANF` reader - Analog filter enable control driving capability activation bits PA10"] pub type I2C_PA10_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA10_ANF` writer - Analog filter enable control driving capability activation bits PA10"] pub type I2C_PA10_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA11_ANF` reader - Analog filter enable control driving capability activation bits PA11"] pub type I2C_PA11_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA11_ANF` writer - Analog filter enable control driving capability activation bits PA11"] pub type I2C_PA11_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PA12_ANF` reader - Analog filter enable control driving capability activation bits PA12"] pub type I2C_PA12_ANF_R = crate::BitReader; #[doc = "Field `I2C_PA12_ANF` writer - Analog filter enable control driving capability activation bits PA12"] pub type I2C_PA12_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PB6_ANF` reader - Analog filter enable control driving capability activation bits PB6"] pub type I2C_PB6_ANF_R = crate::BitReader; #[doc = "Field `I2C_PB6_ANF` writer - Analog filter enable control driving capability activation bits PB6"] pub type I2C_PB6_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PB7_ANF` reader - Analog filter enable control driving capability activation bits PB7"] pub type I2C_PB7_ANF_R = crate::BitReader; #[doc = "Field `I2C_PB7_ANF` writer - Analog filter enable control driving capability activation bits PB7"] pub type I2C_PB7_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PB8_ANF` reader - Analog filter enable control driving capability activation bits PB8"] pub type I2C_PB8_ANF_R = crate::BitReader; #[doc = "Field `I2C_PB8_ANF` writer - Analog filter enable control driving capability activation bits PB8"] pub type I2C_PB8_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PF0_ANF` reader - Analog filter enable control driving capability activation bits PF0"] pub type I2C_PF0_ANF_R = crate::BitReader; #[doc = "Field `I2C_PF0_ANF` writer - Analog filter enable control driving capability activation bits PF0"] pub type I2C_PF0_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; #[doc = "Field `I2C_PF1_ANF` reader - Analog filter enable control driving capability activation bits PF1"] pub type I2C_PF1_ANF_R = crate::BitReader; #[doc = "Field `I2C_PF1_ANF` writer - Analog filter enable control driving capability activation bits PF1"] pub type I2C_PF1_ANF_W<'a, const O: u8> = crate::BitWriter<'a, CFGR1_SPEC, O>; impl R { #[doc = "Bits 0:1 - Memory mapping selection bits"] #[inline(always)] pub fn mem_mode(&self) -> MEM_MODE_R { MEM_MODE_R::new((self.bits & 3) as u8) } #[doc = "Bit 18 - Analog filter enable control driving capability activation bits PA2"] #[inline(always)] pub fn i2c_pa2_anf(&self) -> I2C_PA2_ANF_R { I2C_PA2_ANF_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - Analog filter enable control driving capability activation bits PA3"] #[inline(always)] pub fn i2c_pa3_anf(&self) -> I2C_PA3_ANF_R { I2C_PA3_ANF_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - Analog filter enable control driving capability activation bits PA7"] #[inline(always)] pub fn i2c_pa7_anf(&self) -> I2C_PA7_ANF_R { I2C_PA7_ANF_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Analog filter enable control driving capability activation bits PA8"] #[inline(always)] pub fn i2c_pa8_anf(&self) -> I2C_PA8_ANF_R { I2C_PA8_ANF_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Analog filter enable control driving capability activation bits PA9"] #[inline(always)] pub fn i2c_pa9_anf(&self) -> I2C_PA9_ANF_R { I2C_PA9_ANF_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Analog filter enable control driving capability activation bits PA10"] #[inline(always)] pub fn i2c_pa10_anf(&self) -> I2C_PA10_ANF_R { I2C_PA10_ANF_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - Analog filter enable control driving capability activation bits PA11"] #[inline(always)] pub fn i2c_pa11_anf(&self) -> I2C_PA11_ANF_R { I2C_PA11_ANF_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - Analog filter enable control driving capability activation bits PA12"] #[inline(always)] pub fn i2c_pa12_anf(&self) -> I2C_PA12_ANF_R { I2C_PA12_ANF_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - Analog filter enable control driving capability activation bits PB6"] #[inline(always)] pub fn i2c_pb6_anf(&self) -> I2C_PB6_ANF_R { I2C_PB6_ANF_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - Analog filter enable control driving capability activation bits PB7"] #[inline(always)] pub fn i2c_pb7_anf(&self) -> I2C_PB7_ANF_R { I2C_PB7_ANF_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - Analog filter enable control driving capability activation bits PB8"] #[inline(always)] pub fn i2c_pb8_anf(&self) -> I2C_PB8_ANF_R { I2C_PB8_ANF_R::new(((self.bits >> 28) & 1) != 0) } #[doc = "Bit 29 - Analog filter enable control driving capability activation bits PF0"] #[inline(always)] pub fn i2c_pf0_anf(&self) -> I2C_PF0_ANF_R { I2C_PF0_ANF_R::new(((self.bits >> 29) & 1) != 0) } #[doc = "Bit 30 - Analog filter enable control driving capability activation bits PF1"] #[inline(always)] pub fn i2c_pf1_anf(&self) -> I2C_PF1_ANF_R { I2C_PF1_ANF_R::new(((self.bits >> 30) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - Memory mapping selection bits"] #[inline(always)] #[must_use] pub fn mem_mode(&mut self) -> MEM_MODE_W<0> { MEM_MODE_W::new(self) } #[doc = "Bit 18 - Analog filter enable control driving capability activation bits PA2"] #[inline(always)] #[must_use] pub fn i2c_pa2_anf(&mut self) -> I2C_PA2_ANF_W<18> { I2C_PA2_ANF_W::new(self) } #[doc = "Bit 19 - Analog filter enable control driving capability activation bits PA3"] #[inline(always)] #[must_use] pub fn i2c_pa3_anf(&mut self) -> I2C_PA3_ANF_W<19> { I2C_PA3_ANF_W::new(self) } #[doc = "Bit 20 - Analog filter enable control driving capability activation bits PA7"] #[inline(always)] #[must_use] pub fn i2c_pa7_anf(&mut self) -> I2C_PA7_ANF_W<20> { I2C_PA7_ANF_W::new(self) } #[doc = "Bit 21 - Analog filter enable control driving capability activation bits PA8"] #[inline(always)] #[must_use] pub fn i2c_pa8_anf(&mut self) -> I2C_PA8_ANF_W<21> { I2C_PA8_ANF_W::new(self) } #[doc = "Bit 22 - Analog filter enable control driving capability activation bits PA9"] #[inline(always)] #[must_use] pub fn i2c_pa9_anf(&mut self) -> I2C_PA9_ANF_W<22> { I2C_PA9_ANF_W::new(self) } #[doc = "Bit 23 - Analog filter enable control driving capability activation bits PA10"] #[inline(always)] #[must_use] pub fn i2c_pa10_anf(&mut self) -> I2C_PA10_ANF_W<23> { I2C_PA10_ANF_W::new(self) } #[doc = "Bit 24 - Analog filter enable control driving capability activation bits PA11"] #[inline(always)] #[must_use] pub fn i2c_pa11_anf(&mut self) -> I2C_PA11_ANF_W<24> { I2C_PA11_ANF_W::new(self) } #[doc = "Bit 25 - Analog filter enable control driving capability activation bits PA12"] #[inline(always)] #[must_use] pub fn i2c_pa12_anf(&mut self) -> I2C_PA12_ANF_W<25> { I2C_PA12_ANF_W::new(self) } #[doc = "Bit 26 - Analog filter enable control driving capability activation bits PB6"] #[inline(always)] #[must_use] pub fn i2c_pb6_anf(&mut self) -> I2C_PB6_ANF_W<26> { I2C_PB6_ANF_W::new(self) } #[doc = "Bit 27 - Analog filter enable control driving capability activation bits PB7"] #[inline(always)] #[must_use] pub fn i2c_pb7_anf(&mut self) -> I2C_PB7_ANF_W<27> { I2C_PB7_ANF_W::new(self) } #[doc = "Bit 28 - Analog filter enable control driving capability activation bits PB8"] #[inline(always)] #[must_use] pub fn i2c_pb8_anf(&mut self) -> I2C_PB8_ANF_W<28> { I2C_PB8_ANF_W::new(self) } #[doc = "Bit 29 - Analog filter enable control driving capability activation bits PF0"] #[inline(always)] #[must_use] pub fn i2c_pf0_anf(&mut self) -> I2C_PF0_ANF_W<29> { I2C_PF0_ANF_W::new(self) } #[doc = "Bit 30 - Analog filter enable control driving capability activation bits PF1"] #[inline(always)] #[must_use] pub fn i2c_pf1_anf(&mut self) -> I2C_PF1_ANF_W<30> { I2C_PF1_ANF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "SYSCFG configuration register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr1](index.html) module"] pub struct CFGR1_SPEC; impl crate::RegisterSpec for CFGR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr1::R](R) reader structure"] impl crate::Readable for CFGR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr1::W](W) writer structure"] impl crate::Writable for CFGR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR1 to value 0"] impl crate::Resettable for CFGR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CFGR2 (rw) register accessor: an alias for `Reg`"] pub type CFGR2 = crate::Reg; #[doc = "SYSCFG configuration register 2"] pub mod cfgr2 { #[doc = "Register `CFGR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LOCKUP_LOCK` reader - Cortex-M0+ LOCKUP bit enable bit"] pub type LOCKUP_LOCK_R = crate::BitReader; #[doc = "Field `LOCKUP_LOCK` writer - Cortex-M0+ LOCKUP bit enable bit"] pub type LOCKUP_LOCK_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `PVD_LOCK` reader - PVD lock enable bit"] pub type PVD_LOCK_R = crate::BitReader; #[doc = "Field `PVD_LOCK` writer - PVD lock enable bit"] pub type PVD_LOCK_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `COMP1_BRK_TIM1` reader - COMP1 is enable to input of TIM1 break"] pub type COMP1_BRK_TIM1_R = crate::BitReader; #[doc = "Field `COMP1_BRK_TIM1` writer - COMP1 is enable to input of TIM1 break"] pub type COMP1_BRK_TIM1_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `COMP2_BRK_TIM1` reader - COMP2 is enable to input of TIM1 break"] pub type COMP2_BRK_TIM1_R = crate::BitReader; #[doc = "Field `COMP2_BRK_TIM1` writer - COMP2 is enable to input of TIM1 break"] pub type COMP2_BRK_TIM1_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `COMP1_BRK_TIM16` reader - COMP1 is enable to input of TIM16 break"] pub type COMP1_BRK_TIM16_R = crate::BitReader; #[doc = "Field `COMP1_BRK_TIM16` writer - COMP1 is enable to input of TIM16 break"] pub type COMP1_BRK_TIM16_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `COMP2_BRK_TIM16` reader - COMP2 is enable to input of TIM16 break"] pub type COMP2_BRK_TIM16_R = crate::BitReader; #[doc = "Field `COMP2_BRK_TIM16` writer - COMP2 is enable to input of TIM16 break"] pub type COMP2_BRK_TIM16_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `COMP1_BRK_TIM17` reader - COMP1 is enable to input of TIM17 break"] pub type COMP1_BRK_TIM17_R = crate::BitReader; #[doc = "Field `COMP1_BRK_TIM17` writer - COMP1 is enable to input of TIM17 break"] pub type COMP1_BRK_TIM17_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `COMP2_BRK_TIM17` reader - COMP2 is enable to input of TIM17 break"] pub type COMP2_BRK_TIM17_R = crate::BitReader; #[doc = "Field `COMP2_BRK_TIM17` writer - COMP2 is enable to input of TIM17 break"] pub type COMP2_BRK_TIM17_W<'a, const O: u8> = crate::BitWriter<'a, CFGR2_SPEC, O>; #[doc = "Field `ETR_SRC_TIM1` reader - TIM1 ETR source selection"] pub type ETR_SRC_TIM1_R = crate::FieldReader; #[doc = "Field `ETR_SRC_TIM1` writer - TIM1 ETR source selection"] pub type ETR_SRC_TIM1_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR2_SPEC, 2, O>; impl R { #[doc = "Bit 0 - Cortex-M0+ LOCKUP bit enable bit"] #[inline(always)] pub fn lockup_lock(&self) -> LOCKUP_LOCK_R { LOCKUP_LOCK_R::new((self.bits & 1) != 0) } #[doc = "Bit 2 - PVD lock enable bit"] #[inline(always)] pub fn pvd_lock(&self) -> PVD_LOCK_R { PVD_LOCK_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - COMP1 is enable to input of TIM1 break"] #[inline(always)] pub fn comp1_brk_tim1(&self) -> COMP1_BRK_TIM1_R { COMP1_BRK_TIM1_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - COMP2 is enable to input of TIM1 break"] #[inline(always)] pub fn comp2_brk_tim1(&self) -> COMP2_BRK_TIM1_R { COMP2_BRK_TIM1_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - COMP1 is enable to input of TIM16 break"] #[inline(always)] pub fn comp1_brk_tim16(&self) -> COMP1_BRK_TIM16_R { COMP1_BRK_TIM16_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - COMP2 is enable to input of TIM16 break"] #[inline(always)] pub fn comp2_brk_tim16(&self) -> COMP2_BRK_TIM16_R { COMP2_BRK_TIM16_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - COMP1 is enable to input of TIM17 break"] #[inline(always)] pub fn comp1_brk_tim17(&self) -> COMP1_BRK_TIM17_R { COMP1_BRK_TIM17_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - COMP2 is enable to input of TIM17 break"] #[inline(always)] pub fn comp2_brk_tim17(&self) -> COMP2_BRK_TIM17_R { COMP2_BRK_TIM17_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bits 9:10 - TIM1 ETR source selection"] #[inline(always)] pub fn etr_src_tim1(&self) -> ETR_SRC_TIM1_R { ETR_SRC_TIM1_R::new(((self.bits >> 9) & 3) as u8) } } impl W { #[doc = "Bit 0 - Cortex-M0+ LOCKUP bit enable bit"] #[inline(always)] #[must_use] pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<0> { LOCKUP_LOCK_W::new(self) } #[doc = "Bit 2 - PVD lock enable bit"] #[inline(always)] #[must_use] pub fn pvd_lock(&mut self) -> PVD_LOCK_W<2> { PVD_LOCK_W::new(self) } #[doc = "Bit 3 - COMP1 is enable to input of TIM1 break"] #[inline(always)] #[must_use] pub fn comp1_brk_tim1(&mut self) -> COMP1_BRK_TIM1_W<3> { COMP1_BRK_TIM1_W::new(self) } #[doc = "Bit 4 - COMP2 is enable to input of TIM1 break"] #[inline(always)] #[must_use] pub fn comp2_brk_tim1(&mut self) -> COMP2_BRK_TIM1_W<4> { COMP2_BRK_TIM1_W::new(self) } #[doc = "Bit 5 - COMP1 is enable to input of TIM16 break"] #[inline(always)] #[must_use] pub fn comp1_brk_tim16(&mut self) -> COMP1_BRK_TIM16_W<5> { COMP1_BRK_TIM16_W::new(self) } #[doc = "Bit 6 - COMP2 is enable to input of TIM16 break"] #[inline(always)] #[must_use] pub fn comp2_brk_tim16(&mut self) -> COMP2_BRK_TIM16_W<6> { COMP2_BRK_TIM16_W::new(self) } #[doc = "Bit 7 - COMP1 is enable to input of TIM17 break"] #[inline(always)] #[must_use] pub fn comp1_brk_tim17(&mut self) -> COMP1_BRK_TIM17_W<7> { COMP1_BRK_TIM17_W::new(self) } #[doc = "Bit 8 - COMP2 is enable to input of TIM17 break"] #[inline(always)] #[must_use] pub fn comp2_brk_tim17(&mut self) -> COMP2_BRK_TIM17_W<8> { COMP2_BRK_TIM17_W::new(self) } #[doc = "Bits 9:10 - TIM1 ETR source selection"] #[inline(always)] #[must_use] pub fn etr_src_tim1(&mut self) -> ETR_SRC_TIM1_W<9> { ETR_SRC_TIM1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "SYSCFG configuration register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"] pub struct CFGR2_SPEC; impl crate::RegisterSpec for CFGR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr2::R](R) reader structure"] impl crate::Readable for CFGR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"] impl crate::Writable for CFGR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR2 to value 0"] impl crate::Resettable for CFGR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CFGR3 (rw) register accessor: an alias for `Reg`"] pub type CFGR3 = crate::Reg; #[doc = "SYSCFG configuration register 3"] pub mod cfgr3 { #[doc = "Register `CFGR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CFGR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DMA1_MAP` reader - DMA channel1 requeset selection"] pub type DMA1_MAP_R = crate::FieldReader; #[doc = "Field `DMA1_MAP` writer - DMA channel1 requeset selection"] pub type DMA1_MAP_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR3_SPEC, 5, O>; #[doc = "Field `DMA2_MAP` reader - DMA channel2 requeset selection"] pub type DMA2_MAP_R = crate::FieldReader; #[doc = "Field `DMA2_MAP` writer - DMA channel2 requeset selection"] pub type DMA2_MAP_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR3_SPEC, 5, O>; #[doc = "Field `DMA3_MAP` reader - DMA channel3 requeset selection"] pub type DMA3_MAP_R = crate::FieldReader; #[doc = "Field `DMA3_MAP` writer - DMA channel3 requeset selection"] pub type DMA3_MAP_W<'a, const O: u8> = crate::FieldWriter<'a, CFGR3_SPEC, 5, O>; impl R { #[doc = "Bits 0:4 - DMA channel1 requeset selection"] #[inline(always)] pub fn dma1_map(&self) -> DMA1_MAP_R { DMA1_MAP_R::new((self.bits & 0x1f) as u8) } #[doc = "Bits 8:12 - DMA channel2 requeset selection"] #[inline(always)] pub fn dma2_map(&self) -> DMA2_MAP_R { DMA2_MAP_R::new(((self.bits >> 8) & 0x1f) as u8) } #[doc = "Bits 16:20 - DMA channel3 requeset selection"] #[inline(always)] pub fn dma3_map(&self) -> DMA3_MAP_R { DMA3_MAP_R::new(((self.bits >> 16) & 0x1f) as u8) } } impl W { #[doc = "Bits 0:4 - DMA channel1 requeset selection"] #[inline(always)] #[must_use] pub fn dma1_map(&mut self) -> DMA1_MAP_W<0> { DMA1_MAP_W::new(self) } #[doc = "Bits 8:12 - DMA channel2 requeset selection"] #[inline(always)] #[must_use] pub fn dma2_map(&mut self) -> DMA2_MAP_W<8> { DMA2_MAP_W::new(self) } #[doc = "Bits 16:20 - DMA channel3 requeset selection"] #[inline(always)] #[must_use] pub fn dma3_map(&mut self) -> DMA3_MAP_W<16> { DMA3_MAP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "SYSCFG configuration register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr3](index.html) module"] pub struct CFGR3_SPEC; impl crate::RegisterSpec for CFGR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cfgr3::R](R) reader structure"] impl crate::Readable for CFGR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cfgr3::W](W) writer structure"] impl crate::Writable for CFGR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CFGR3 to value 0"] impl crate::Resettable for CFGR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Direct memory access"] pub struct DMA { _marker: PhantomData<*const ()>, } unsafe impl Send for DMA {} impl DMA { #[doc = r"Pointer to the register block"] pub const PTR: *const dma::RegisterBlock = 0x4002_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const dma::RegisterBlock { Self::PTR } } impl Deref for DMA { type Target = dma::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for DMA { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DMA").finish() } } #[doc = "Direct memory access"] pub mod dma { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - DMA interrupt status register (DMA_ISR)"] pub isr: ISR, #[doc = "0x04 - DMA interrupt flag clear register (DMA_IFCR)"] pub ifcr: IFCR, #[doc = "0x08 - DMA channel configuration register (DMA_CCR)"] pub ccr1: CCR1, #[doc = "0x0c - DMA channel 1 number of data register"] pub cndtr1: CNDTR1, #[doc = "0x10 - DMA channel 1 peripheral address register"] pub cpar1: CPAR1, #[doc = "0x14 - DMA channel 1 memory address register"] pub cmar1: CMAR1, _reserved6: [u8; 0x04], #[doc = "0x1c - DMA channel configuration register (DMA_CCR)"] pub ccr2: CCR2, #[doc = "0x20 - DMA channel 2 number of data register"] pub cndtr2: CNDTR2, #[doc = "0x24 - DMA channel 2 peripheral address register"] pub cpar2: CPAR2, #[doc = "0x28 - DMA channel 2 memory address register"] pub cmar2: CMAR2, _reserved10: [u8; 0x04], #[doc = "0x30 - DMA channel configuration register (DMA_CCR)"] pub ccr3: CCR3, #[doc = "0x34 - DMA channel 3 number of data register"] pub cndtr3: CNDTR3, #[doc = "0x38 - DMA channel 3 peripheral address register"] pub cpar3: CPAR3, #[doc = "0x3c - DMA channel 3 memory address register"] pub cmar3: CMAR3, } #[doc = "ISR (r) register accessor: an alias for `Reg`"] pub type ISR = crate::Reg; #[doc = "DMA interrupt status register (DMA_ISR)"] pub mod isr { #[doc = "Register `ISR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `GIF1` reader - Channel 1 Global interrupt flag"] pub type GIF1_R = crate::BitReader; #[doc = "Field `TCIF1` reader - Channel 1 Transfer Complete flag"] pub type TCIF1_R = crate::BitReader; #[doc = "Field `HTIF1` reader - Channel 1 Half Transfer Complete flag"] pub type HTIF1_R = crate::BitReader; #[doc = "Field `TEIF1` reader - Channel 1 Transfer Error flag"] pub type TEIF1_R = crate::BitReader; #[doc = "Field `GIF2` reader - Channel 2 Global interrupt flag"] pub type GIF2_R = crate::BitReader; #[doc = "Field `TCIF2` reader - Channel 2 Transfer Complete flag"] pub type TCIF2_R = crate::BitReader; #[doc = "Field `HTIF2` reader - Channel 2 Half Transfer Complete flag"] pub type HTIF2_R = crate::BitReader; #[doc = "Field `TEIF2` reader - Channel 2 Transfer Error flag"] pub type TEIF2_R = crate::BitReader; #[doc = "Field `GIF3` reader - Channel 3 Global interrupt flag"] pub type GIF3_R = crate::BitReader; #[doc = "Field `TCIF3` reader - Channel 3 Transfer Complete flag"] pub type TCIF3_R = crate::BitReader; #[doc = "Field `HTIF3` reader - Channel 3 Half Transfer Complete flag"] pub type HTIF3_R = crate::BitReader; #[doc = "Field `TEIF3` reader - Channel 3 Transfer Error flag"] pub type TEIF3_R = crate::BitReader; impl R { #[doc = "Bit 0 - Channel 1 Global interrupt flag"] #[inline(always)] pub fn gif1(&self) -> GIF1_R { GIF1_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Channel 1 Transfer Complete flag"] #[inline(always)] pub fn tcif1(&self) -> TCIF1_R { TCIF1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Channel 1 Half Transfer Complete flag"] #[inline(always)] pub fn htif1(&self) -> HTIF1_R { HTIF1_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Channel 1 Transfer Error flag"] #[inline(always)] pub fn teif1(&self) -> TEIF1_R { TEIF1_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Channel 2 Global interrupt flag"] #[inline(always)] pub fn gif2(&self) -> GIF2_R { GIF2_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Channel 2 Transfer Complete flag"] #[inline(always)] pub fn tcif2(&self) -> TCIF2_R { TCIF2_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Channel 2 Half Transfer Complete flag"] #[inline(always)] pub fn htif2(&self) -> HTIF2_R { HTIF2_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Channel 2 Transfer Error flag"] #[inline(always)] pub fn teif2(&self) -> TEIF2_R { TEIF2_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Channel 3 Global interrupt flag"] #[inline(always)] pub fn gif3(&self) -> GIF3_R { GIF3_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Channel 3 Transfer Complete flag"] #[inline(always)] pub fn tcif3(&self) -> TCIF3_R { TCIF3_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Channel 3 Half Transfer Complete flag"] #[inline(always)] pub fn htif3(&self) -> HTIF3_R { HTIF3_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Channel 3 Transfer Error flag"] #[inline(always)] pub fn teif3(&self) -> TEIF3_R { TEIF3_R::new(((self.bits >> 11) & 1) != 0) } } #[doc = "DMA interrupt status register (DMA_ISR)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [isr::R](R) reader structure"] impl crate::Readable for ISR_SPEC { type Reader = R; } #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IFCR (w) register accessor: an alias for `Reg`"] pub type IFCR = crate::Reg; #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] pub mod ifcr { #[doc = "Register `IFCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CGIF1` writer - Channel 1 Global interrupt clear"] pub type CGIF1_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CTCIF1` writer - Channel 1 Transfer Complete clear"] pub type CTCIF1_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CHTIF1` writer - Channel 1 Half Transfer clear"] pub type CHTIF1_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CTEIF1` writer - Channel 1 Transfer Error clear"] pub type CTEIF1_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CGIF2` writer - Channel 2 Global interrupt clear"] pub type CGIF2_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CTCIF2` writer - Channel 2 Transfer Complete clear"] pub type CTCIF2_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CHTIF2` writer - Channel 2 Half Transfer clear"] pub type CHTIF2_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CTEIF2` writer - Channel 2 Transfer Error clear"] pub type CTEIF2_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CGIF3` writer - Channel 3 Global interrupt clear"] pub type CGIF3_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CTCIF3` writer - Channel 3 Transfer Complete clear"] pub type CTCIF3_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CHTIF3` writer - Channel 3 Half Transfer clear"] pub type CHTIF3_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; #[doc = "Field `CTEIF3` writer - Channel 3 Transfer Error clear"] pub type CTEIF3_W<'a, const O: u8> = crate::BitWriter<'a, IFCR_SPEC, O>; impl W { #[doc = "Bit 0 - Channel 1 Global interrupt clear"] #[inline(always)] #[must_use] pub fn cgif1(&mut self) -> CGIF1_W<0> { CGIF1_W::new(self) } #[doc = "Bit 1 - Channel 1 Transfer Complete clear"] #[inline(always)] #[must_use] pub fn ctcif1(&mut self) -> CTCIF1_W<1> { CTCIF1_W::new(self) } #[doc = "Bit 2 - Channel 1 Half Transfer clear"] #[inline(always)] #[must_use] pub fn chtif1(&mut self) -> CHTIF1_W<2> { CHTIF1_W::new(self) } #[doc = "Bit 3 - Channel 1 Transfer Error clear"] #[inline(always)] #[must_use] pub fn cteif1(&mut self) -> CTEIF1_W<3> { CTEIF1_W::new(self) } #[doc = "Bit 4 - Channel 2 Global interrupt clear"] #[inline(always)] #[must_use] pub fn cgif2(&mut self) -> CGIF2_W<4> { CGIF2_W::new(self) } #[doc = "Bit 5 - Channel 2 Transfer Complete clear"] #[inline(always)] #[must_use] pub fn ctcif2(&mut self) -> CTCIF2_W<5> { CTCIF2_W::new(self) } #[doc = "Bit 6 - Channel 2 Half Transfer clear"] #[inline(always)] #[must_use] pub fn chtif2(&mut self) -> CHTIF2_W<6> { CHTIF2_W::new(self) } #[doc = "Bit 7 - Channel 2 Transfer Error clear"] #[inline(always)] #[must_use] pub fn cteif2(&mut self) -> CTEIF2_W<7> { CTEIF2_W::new(self) } #[doc = "Bit 8 - Channel 3 Global interrupt clear"] #[inline(always)] #[must_use] pub fn cgif3(&mut self) -> CGIF3_W<8> { CGIF3_W::new(self) } #[doc = "Bit 9 - Channel 3 Transfer Complete clear"] #[inline(always)] #[must_use] pub fn ctcif3(&mut self) -> CTCIF3_W<9> { CTCIF3_W::new(self) } #[doc = "Bit 10 - Channel 3 Half Transfer clear"] #[inline(always)] #[must_use] pub fn chtif3(&mut self) -> CHTIF3_W<10> { CHTIF3_W::new(self) } #[doc = "Bit 11 - Channel 3 Transfer Error clear"] #[inline(always)] #[must_use] pub fn cteif3(&mut self) -> CTEIF3_W<11> { CTEIF3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA interrupt flag clear register (DMA_IFCR)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifcr](index.html) module"] pub struct IFCR_SPEC; impl crate::RegisterSpec for IFCR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [ifcr::W](W) writer structure"] impl crate::Writable for IFCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IFCR to value 0"] impl crate::Resettable for IFCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR1 (rw) register accessor: an alias for `Reg`"] pub type CCR1 = crate::Reg; #[doc = "DMA channel configuration register (DMA_CCR)"] pub mod ccr1 { #[doc = "Register `CCR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EN` reader - Channel enable"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Channel enable"] pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TCIE_R = crate::BitReader; #[doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `HTIE` reader - Half Transfer interrupt enable"] pub type HTIE_R = crate::BitReader; #[doc = "Field `HTIE` writer - Half Transfer interrupt enable"] pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TEIE_R = crate::BitReader; #[doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `DIR` reader - Data transfer direction"] pub type DIR_R = crate::BitReader; #[doc = "Field `DIR` writer - Data transfer direction"] pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `CIRC` reader - Circular mode"] pub type CIRC_R = crate::BitReader; #[doc = "Field `CIRC` writer - Circular mode"] pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `PINC` reader - Peripheral increment mode"] pub type PINC_R = crate::BitReader; #[doc = "Field `PINC` writer - Peripheral increment mode"] pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `MINC` reader - Memory increment mode"] pub type MINC_R = crate::BitReader; #[doc = "Field `MINC` writer - Memory increment mode"] pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; #[doc = "Field `PSIZE` reader - Peripheral size"] pub type PSIZE_R = crate::FieldReader; #[doc = "Field `PSIZE` writer - Peripheral size"] pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 2, O>; #[doc = "Field `MSIZE` reader - Memory size"] pub type MSIZE_R = crate::FieldReader; #[doc = "Field `MSIZE` writer - Memory size"] pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 2, O>; #[doc = "Field `PL` reader - Channel Priority level"] pub type PL_R = crate::FieldReader; #[doc = "Field `PL` writer - Channel Priority level"] pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, CCR1_SPEC, 2, O>; #[doc = "Field `MEM2MEM` reader - Memory to memory mode"] pub type MEM2MEM_R = crate::BitReader; #[doc = "Field `MEM2MEM` writer - Memory to memory mode"] pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, CCR1_SPEC, O>; impl R { #[doc = "Bit 0 - Channel enable"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Transfer complete interrupt enable"] #[inline(always)] pub fn tcie(&self) -> TCIE_R { TCIE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Half Transfer interrupt enable"] #[inline(always)] pub fn htie(&self) -> HTIE_R { HTIE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Transfer error interrupt enable"] #[inline(always)] pub fn teie(&self) -> TEIE_R { TEIE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Data transfer direction"] #[inline(always)] pub fn dir(&self) -> DIR_R { DIR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Circular mode"] #[inline(always)] pub fn circ(&self) -> CIRC_R { CIRC_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Peripheral increment mode"] #[inline(always)] pub fn pinc(&self) -> PINC_R { PINC_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Memory increment mode"] #[inline(always)] pub fn minc(&self) -> MINC_R { MINC_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Peripheral size"] #[inline(always)] pub fn psize(&self) -> PSIZE_R { PSIZE_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Memory size"] #[inline(always)] pub fn msize(&self) -> MSIZE_R { MSIZE_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Channel Priority level"] #[inline(always)] pub fn pl(&self) -> PL_R { PL_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bit 14 - Memory to memory mode"] #[inline(always)] pub fn mem2mem(&self) -> MEM2MEM_R { MEM2MEM_R::new(((self.bits >> 14) & 1) != 0) } } impl W { #[doc = "Bit 0 - Channel enable"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W<0> { EN_W::new(self) } #[doc = "Bit 1 - Transfer complete interrupt enable"] #[inline(always)] #[must_use] pub fn tcie(&mut self) -> TCIE_W<1> { TCIE_W::new(self) } #[doc = "Bit 2 - Half Transfer interrupt enable"] #[inline(always)] #[must_use] pub fn htie(&mut self) -> HTIE_W<2> { HTIE_W::new(self) } #[doc = "Bit 3 - Transfer error interrupt enable"] #[inline(always)] #[must_use] pub fn teie(&mut self) -> TEIE_W<3> { TEIE_W::new(self) } #[doc = "Bit 4 - Data transfer direction"] #[inline(always)] #[must_use] pub fn dir(&mut self) -> DIR_W<4> { DIR_W::new(self) } #[doc = "Bit 5 - Circular mode"] #[inline(always)] #[must_use] pub fn circ(&mut self) -> CIRC_W<5> { CIRC_W::new(self) } #[doc = "Bit 6 - Peripheral increment mode"] #[inline(always)] #[must_use] pub fn pinc(&mut self) -> PINC_W<6> { PINC_W::new(self) } #[doc = "Bit 7 - Memory increment mode"] #[inline(always)] #[must_use] pub fn minc(&mut self) -> MINC_W<7> { MINC_W::new(self) } #[doc = "Bits 8:9 - Peripheral size"] #[inline(always)] #[must_use] pub fn psize(&mut self) -> PSIZE_W<8> { PSIZE_W::new(self) } #[doc = "Bits 10:11 - Memory size"] #[inline(always)] #[must_use] pub fn msize(&mut self) -> MSIZE_W<10> { MSIZE_W::new(self) } #[doc = "Bits 12:13 - Channel Priority level"] #[inline(always)] #[must_use] pub fn pl(&mut self) -> PL_W<12> { PL_W::new(self) } #[doc = "Bit 14 - Memory to memory mode"] #[inline(always)] #[must_use] pub fn mem2mem(&mut self) -> MEM2MEM_W<14> { MEM2MEM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel configuration register (DMA_CCR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"] pub struct CCR1_SPEC; impl crate::RegisterSpec for CCR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr1::R](R) reader structure"] impl crate::Readable for CCR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"] impl crate::Writable for CCR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR1 to value 0"] impl crate::Resettable for CCR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNDTR1 (rw) register accessor: an alias for `Reg`"] pub type CNDTR1 = crate::Reg; #[doc = "DMA channel 1 number of data register"] pub mod cndtr1 { #[doc = "Register `CNDTR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNDTR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `NDT` reader - Number of data to transfer"] pub type NDT_R = crate::FieldReader; #[doc = "Field `NDT` writer - Number of data to transfer"] pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, CNDTR1_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of data to transfer"] #[inline(always)] pub fn ndt(&self) -> NDT_R { NDT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Number of data to transfer"] #[inline(always)] #[must_use] pub fn ndt(&mut self) -> NDT_W<0> { NDT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 1 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cndtr1](index.html) module"] pub struct CNDTR1_SPEC; impl crate::RegisterSpec for CNDTR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cndtr1::R](R) reader structure"] impl crate::Readable for CNDTR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cndtr1::W](W) writer structure"] impl crate::Writable for CNDTR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNDTR1 to value 0"] impl crate::Resettable for CNDTR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CPAR1 (rw) register accessor: an alias for `Reg`"] pub type CPAR1 = crate::Reg; #[doc = "DMA channel 1 peripheral address register"] pub mod cpar1 { #[doc = "Register `CPAR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CPAR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PA` reader - Peripheral address"] pub type PA_R = crate::FieldReader; #[doc = "Field `PA` writer - Peripheral address"] pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, CPAR1_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Peripheral address"] #[inline(always)] pub fn pa(&self) -> PA_R { PA_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Peripheral address"] #[inline(always)] #[must_use] pub fn pa(&mut self) -> PA_W<0> { PA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 1 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpar1](index.html) module"] pub struct CPAR1_SPEC; impl crate::RegisterSpec for CPAR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cpar1::R](R) reader structure"] impl crate::Readable for CPAR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cpar1::W](W) writer structure"] impl crate::Writable for CPAR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CPAR1 to value 0"] impl crate::Resettable for CPAR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CMAR1 (rw) register accessor: an alias for `Reg`"] pub type CMAR1 = crate::Reg; #[doc = "DMA channel 1 memory address register"] pub mod cmar1 { #[doc = "Register `CMAR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CMAR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `MA` reader - Memory address"] pub type MA_R = crate::FieldReader; #[doc = "Field `MA` writer - Memory address"] pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, CMAR1_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Memory address"] #[inline(always)] pub fn ma(&self) -> MA_R { MA_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Memory address"] #[inline(always)] #[must_use] pub fn ma(&mut self) -> MA_W<0> { MA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 1 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmar1](index.html) module"] pub struct CMAR1_SPEC; impl crate::RegisterSpec for CMAR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cmar1::R](R) reader structure"] impl crate::Readable for CMAR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cmar1::W](W) writer structure"] impl crate::Writable for CMAR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CMAR1 to value 0"] impl crate::Resettable for CMAR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR2 (rw) register accessor: an alias for `Reg`"] pub type CCR2 = crate::Reg; #[doc = "DMA channel configuration register (DMA_CCR)"] pub mod ccr2 { #[doc = "Register `CCR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EN` reader - Channel enable"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Channel enable"] pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TCIE_R = crate::BitReader; #[doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `HTIE` reader - Half Transfer interrupt enable"] pub type HTIE_R = crate::BitReader; #[doc = "Field `HTIE` writer - Half Transfer interrupt enable"] pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TEIE_R = crate::BitReader; #[doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `DIR` reader - Data transfer direction"] pub type DIR_R = crate::BitReader; #[doc = "Field `DIR` writer - Data transfer direction"] pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `CIRC` reader - Circular mode"] pub type CIRC_R = crate::BitReader; #[doc = "Field `CIRC` writer - Circular mode"] pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `PINC` reader - Peripheral increment mode"] pub type PINC_R = crate::BitReader; #[doc = "Field `PINC` writer - Peripheral increment mode"] pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `MINC` reader - Memory increment mode"] pub type MINC_R = crate::BitReader; #[doc = "Field `MINC` writer - Memory increment mode"] pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; #[doc = "Field `PSIZE` reader - Peripheral size"] pub type PSIZE_R = crate::FieldReader; #[doc = "Field `PSIZE` writer - Peripheral size"] pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CCR2_SPEC, 2, O>; #[doc = "Field `MSIZE` reader - Memory size"] pub type MSIZE_R = crate::FieldReader; #[doc = "Field `MSIZE` writer - Memory size"] pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CCR2_SPEC, 2, O>; #[doc = "Field `PL` reader - Channel Priority level"] pub type PL_R = crate::FieldReader; #[doc = "Field `PL` writer - Channel Priority level"] pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, CCR2_SPEC, 2, O>; #[doc = "Field `MEM2MEM` reader - Memory to memory mode"] pub type MEM2MEM_R = crate::BitReader; #[doc = "Field `MEM2MEM` writer - Memory to memory mode"] pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, CCR2_SPEC, O>; impl R { #[doc = "Bit 0 - Channel enable"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Transfer complete interrupt enable"] #[inline(always)] pub fn tcie(&self) -> TCIE_R { TCIE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Half Transfer interrupt enable"] #[inline(always)] pub fn htie(&self) -> HTIE_R { HTIE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Transfer error interrupt enable"] #[inline(always)] pub fn teie(&self) -> TEIE_R { TEIE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Data transfer direction"] #[inline(always)] pub fn dir(&self) -> DIR_R { DIR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Circular mode"] #[inline(always)] pub fn circ(&self) -> CIRC_R { CIRC_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Peripheral increment mode"] #[inline(always)] pub fn pinc(&self) -> PINC_R { PINC_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Memory increment mode"] #[inline(always)] pub fn minc(&self) -> MINC_R { MINC_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Peripheral size"] #[inline(always)] pub fn psize(&self) -> PSIZE_R { PSIZE_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Memory size"] #[inline(always)] pub fn msize(&self) -> MSIZE_R { MSIZE_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Channel Priority level"] #[inline(always)] pub fn pl(&self) -> PL_R { PL_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bit 14 - Memory to memory mode"] #[inline(always)] pub fn mem2mem(&self) -> MEM2MEM_R { MEM2MEM_R::new(((self.bits >> 14) & 1) != 0) } } impl W { #[doc = "Bit 0 - Channel enable"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W<0> { EN_W::new(self) } #[doc = "Bit 1 - Transfer complete interrupt enable"] #[inline(always)] #[must_use] pub fn tcie(&mut self) -> TCIE_W<1> { TCIE_W::new(self) } #[doc = "Bit 2 - Half Transfer interrupt enable"] #[inline(always)] #[must_use] pub fn htie(&mut self) -> HTIE_W<2> { HTIE_W::new(self) } #[doc = "Bit 3 - Transfer error interrupt enable"] #[inline(always)] #[must_use] pub fn teie(&mut self) -> TEIE_W<3> { TEIE_W::new(self) } #[doc = "Bit 4 - Data transfer direction"] #[inline(always)] #[must_use] pub fn dir(&mut self) -> DIR_W<4> { DIR_W::new(self) } #[doc = "Bit 5 - Circular mode"] #[inline(always)] #[must_use] pub fn circ(&mut self) -> CIRC_W<5> { CIRC_W::new(self) } #[doc = "Bit 6 - Peripheral increment mode"] #[inline(always)] #[must_use] pub fn pinc(&mut self) -> PINC_W<6> { PINC_W::new(self) } #[doc = "Bit 7 - Memory increment mode"] #[inline(always)] #[must_use] pub fn minc(&mut self) -> MINC_W<7> { MINC_W::new(self) } #[doc = "Bits 8:9 - Peripheral size"] #[inline(always)] #[must_use] pub fn psize(&mut self) -> PSIZE_W<8> { PSIZE_W::new(self) } #[doc = "Bits 10:11 - Memory size"] #[inline(always)] #[must_use] pub fn msize(&mut self) -> MSIZE_W<10> { MSIZE_W::new(self) } #[doc = "Bits 12:13 - Channel Priority level"] #[inline(always)] #[must_use] pub fn pl(&mut self) -> PL_W<12> { PL_W::new(self) } #[doc = "Bit 14 - Memory to memory mode"] #[inline(always)] #[must_use] pub fn mem2mem(&mut self) -> MEM2MEM_W<14> { MEM2MEM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel configuration register (DMA_CCR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr2](index.html) module"] pub struct CCR2_SPEC; impl crate::RegisterSpec for CCR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr2::R](R) reader structure"] impl crate::Readable for CCR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr2::W](W) writer structure"] impl crate::Writable for CCR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR2 to value 0"] impl crate::Resettable for CCR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNDTR2 (rw) register accessor: an alias for `Reg`"] pub type CNDTR2 = crate::Reg; #[doc = "DMA channel 2 number of data register"] pub mod cndtr2 { #[doc = "Register `CNDTR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNDTR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `NDT` reader - Number of data to transfer"] pub type NDT_R = crate::FieldReader; #[doc = "Field `NDT` writer - Number of data to transfer"] pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, CNDTR2_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of data to transfer"] #[inline(always)] pub fn ndt(&self) -> NDT_R { NDT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Number of data to transfer"] #[inline(always)] #[must_use] pub fn ndt(&mut self) -> NDT_W<0> { NDT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 2 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cndtr2](index.html) module"] pub struct CNDTR2_SPEC; impl crate::RegisterSpec for CNDTR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cndtr2::R](R) reader structure"] impl crate::Readable for CNDTR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cndtr2::W](W) writer structure"] impl crate::Writable for CNDTR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNDTR2 to value 0"] impl crate::Resettable for CNDTR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CPAR2 (rw) register accessor: an alias for `Reg`"] pub type CPAR2 = crate::Reg; #[doc = "DMA channel 2 peripheral address register"] pub mod cpar2 { #[doc = "Register `CPAR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CPAR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PA` reader - Peripheral address"] pub type PA_R = crate::FieldReader; #[doc = "Field `PA` writer - Peripheral address"] pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, CPAR2_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Peripheral address"] #[inline(always)] pub fn pa(&self) -> PA_R { PA_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Peripheral address"] #[inline(always)] #[must_use] pub fn pa(&mut self) -> PA_W<0> { PA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 2 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpar2](index.html) module"] pub struct CPAR2_SPEC; impl crate::RegisterSpec for CPAR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cpar2::R](R) reader structure"] impl crate::Readable for CPAR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cpar2::W](W) writer structure"] impl crate::Writable for CPAR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CPAR2 to value 0"] impl crate::Resettable for CPAR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CMAR2 (rw) register accessor: an alias for `Reg`"] pub type CMAR2 = crate::Reg; #[doc = "DMA channel 2 memory address register"] pub mod cmar2 { #[doc = "Register `CMAR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CMAR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `MA` reader - Memory address"] pub type MA_R = crate::FieldReader; #[doc = "Field `MA` writer - Memory address"] pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, CMAR2_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Memory address"] #[inline(always)] pub fn ma(&self) -> MA_R { MA_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Memory address"] #[inline(always)] #[must_use] pub fn ma(&mut self) -> MA_W<0> { MA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 2 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmar2](index.html) module"] pub struct CMAR2_SPEC; impl crate::RegisterSpec for CMAR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cmar2::R](R) reader structure"] impl crate::Readable for CMAR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cmar2::W](W) writer structure"] impl crate::Writable for CMAR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CMAR2 to value 0"] impl crate::Resettable for CMAR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR3 (rw) register accessor: an alias for `Reg`"] pub type CCR3 = crate::Reg; #[doc = "DMA channel configuration register (DMA_CCR)"] pub mod ccr3 { #[doc = "Register `CCR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EN` reader - Channel enable"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Channel enable"] pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `TCIE` reader - Transfer complete interrupt enable"] pub type TCIE_R = crate::BitReader; #[doc = "Field `TCIE` writer - Transfer complete interrupt enable"] pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `HTIE` reader - Half Transfer interrupt enable"] pub type HTIE_R = crate::BitReader; #[doc = "Field `HTIE` writer - Half Transfer interrupt enable"] pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `TEIE` reader - Transfer error interrupt enable"] pub type TEIE_R = crate::BitReader; #[doc = "Field `TEIE` writer - Transfer error interrupt enable"] pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `DIR` reader - Data transfer direction"] pub type DIR_R = crate::BitReader; #[doc = "Field `DIR` writer - Data transfer direction"] pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `CIRC` reader - Circular mode"] pub type CIRC_R = crate::BitReader; #[doc = "Field `CIRC` writer - Circular mode"] pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `PINC` reader - Peripheral increment mode"] pub type PINC_R = crate::BitReader; #[doc = "Field `PINC` writer - Peripheral increment mode"] pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `MINC` reader - Memory increment mode"] pub type MINC_R = crate::BitReader; #[doc = "Field `MINC` writer - Memory increment mode"] pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; #[doc = "Field `PSIZE` reader - Peripheral size"] pub type PSIZE_R = crate::FieldReader; #[doc = "Field `PSIZE` writer - Peripheral size"] pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CCR3_SPEC, 2, O>; #[doc = "Field `MSIZE` reader - Memory size"] pub type MSIZE_R = crate::FieldReader; #[doc = "Field `MSIZE` writer - Memory size"] pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CCR3_SPEC, 2, O>; #[doc = "Field `PL` reader - Channel Priority level"] pub type PL_R = crate::FieldReader; #[doc = "Field `PL` writer - Channel Priority level"] pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, CCR3_SPEC, 2, O>; #[doc = "Field `MEM2MEM` reader - Memory to memory mode"] pub type MEM2MEM_R = crate::BitReader; #[doc = "Field `MEM2MEM` writer - Memory to memory mode"] pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, CCR3_SPEC, O>; impl R { #[doc = "Bit 0 - Channel enable"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Transfer complete interrupt enable"] #[inline(always)] pub fn tcie(&self) -> TCIE_R { TCIE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Half Transfer interrupt enable"] #[inline(always)] pub fn htie(&self) -> HTIE_R { HTIE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Transfer error interrupt enable"] #[inline(always)] pub fn teie(&self) -> TEIE_R { TEIE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Data transfer direction"] #[inline(always)] pub fn dir(&self) -> DIR_R { DIR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Circular mode"] #[inline(always)] pub fn circ(&self) -> CIRC_R { CIRC_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Peripheral increment mode"] #[inline(always)] pub fn pinc(&self) -> PINC_R { PINC_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Memory increment mode"] #[inline(always)] pub fn minc(&self) -> MINC_R { MINC_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Peripheral size"] #[inline(always)] pub fn psize(&self) -> PSIZE_R { PSIZE_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Memory size"] #[inline(always)] pub fn msize(&self) -> MSIZE_R { MSIZE_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Channel Priority level"] #[inline(always)] pub fn pl(&self) -> PL_R { PL_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bit 14 - Memory to memory mode"] #[inline(always)] pub fn mem2mem(&self) -> MEM2MEM_R { MEM2MEM_R::new(((self.bits >> 14) & 1) != 0) } } impl W { #[doc = "Bit 0 - Channel enable"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W<0> { EN_W::new(self) } #[doc = "Bit 1 - Transfer complete interrupt enable"] #[inline(always)] #[must_use] pub fn tcie(&mut self) -> TCIE_W<1> { TCIE_W::new(self) } #[doc = "Bit 2 - Half Transfer interrupt enable"] #[inline(always)] #[must_use] pub fn htie(&mut self) -> HTIE_W<2> { HTIE_W::new(self) } #[doc = "Bit 3 - Transfer error interrupt enable"] #[inline(always)] #[must_use] pub fn teie(&mut self) -> TEIE_W<3> { TEIE_W::new(self) } #[doc = "Bit 4 - Data transfer direction"] #[inline(always)] #[must_use] pub fn dir(&mut self) -> DIR_W<4> { DIR_W::new(self) } #[doc = "Bit 5 - Circular mode"] #[inline(always)] #[must_use] pub fn circ(&mut self) -> CIRC_W<5> { CIRC_W::new(self) } #[doc = "Bit 6 - Peripheral increment mode"] #[inline(always)] #[must_use] pub fn pinc(&mut self) -> PINC_W<6> { PINC_W::new(self) } #[doc = "Bit 7 - Memory increment mode"] #[inline(always)] #[must_use] pub fn minc(&mut self) -> MINC_W<7> { MINC_W::new(self) } #[doc = "Bits 8:9 - Peripheral size"] #[inline(always)] #[must_use] pub fn psize(&mut self) -> PSIZE_W<8> { PSIZE_W::new(self) } #[doc = "Bits 10:11 - Memory size"] #[inline(always)] #[must_use] pub fn msize(&mut self) -> MSIZE_W<10> { MSIZE_W::new(self) } #[doc = "Bits 12:13 - Channel Priority level"] #[inline(always)] #[must_use] pub fn pl(&mut self) -> PL_W<12> { PL_W::new(self) } #[doc = "Bit 14 - Memory to memory mode"] #[inline(always)] #[must_use] pub fn mem2mem(&mut self) -> MEM2MEM_W<14> { MEM2MEM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel configuration register (DMA_CCR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr3](index.html) module"] pub struct CCR3_SPEC; impl crate::RegisterSpec for CCR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr3::R](R) reader structure"] impl crate::Readable for CCR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr3::W](W) writer structure"] impl crate::Writable for CCR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR3 to value 0"] impl crate::Resettable for CCR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CNDTR3 (rw) register accessor: an alias for `Reg`"] pub type CNDTR3 = crate::Reg; #[doc = "DMA channel 3 number of data register"] pub mod cndtr3 { #[doc = "Register `CNDTR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CNDTR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `NDT` reader - Number of data to transfer"] pub type NDT_R = crate::FieldReader; #[doc = "Field `NDT` writer - Number of data to transfer"] pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, CNDTR3_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of data to transfer"] #[inline(always)] pub fn ndt(&self) -> NDT_R { NDT_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Number of data to transfer"] #[inline(always)] #[must_use] pub fn ndt(&mut self) -> NDT_W<0> { NDT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 3 number of data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cndtr3](index.html) module"] pub struct CNDTR3_SPEC; impl crate::RegisterSpec for CNDTR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cndtr3::R](R) reader structure"] impl crate::Readable for CNDTR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cndtr3::W](W) writer structure"] impl crate::Writable for CNDTR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CNDTR3 to value 0"] impl crate::Resettable for CNDTR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CPAR3 (rw) register accessor: an alias for `Reg`"] pub type CPAR3 = crate::Reg; #[doc = "DMA channel 3 peripheral address register"] pub mod cpar3 { #[doc = "Register `CPAR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CPAR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PA` reader - Peripheral address"] pub type PA_R = crate::FieldReader; #[doc = "Field `PA` writer - Peripheral address"] pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, CPAR3_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Peripheral address"] #[inline(always)] pub fn pa(&self) -> PA_R { PA_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Peripheral address"] #[inline(always)] #[must_use] pub fn pa(&mut self) -> PA_W<0> { PA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 3 peripheral address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpar3](index.html) module"] pub struct CPAR3_SPEC; impl crate::RegisterSpec for CPAR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cpar3::R](R) reader structure"] impl crate::Readable for CPAR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cpar3::W](W) writer structure"] impl crate::Writable for CPAR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CPAR3 to value 0"] impl crate::Resettable for CPAR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CMAR3 (rw) register accessor: an alias for `Reg`"] pub type CMAR3 = crate::Reg; #[doc = "DMA channel 3 memory address register"] pub mod cmar3 { #[doc = "Register `CMAR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CMAR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `MA` reader - Memory address"] pub type MA_R = crate::FieldReader; #[doc = "Field `MA` writer - Memory address"] pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, CMAR3_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Memory address"] #[inline(always)] pub fn ma(&self) -> MA_R { MA_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Memory address"] #[inline(always)] #[must_use] pub fn ma(&mut self) -> MA_W<0> { MA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA channel 3 memory address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmar3](index.html) module"] pub struct CMAR3_SPEC; impl crate::RegisterSpec for CMAR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cmar3::R](R) reader structure"] impl crate::Readable for CMAR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cmar3::W](W) writer structure"] impl crate::Writable for CMAR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CMAR3 to value 0"] impl crate::Resettable for CMAR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Flash"] pub struct FLASH { _marker: PhantomData<*const ()>, } unsafe impl Send for FLASH {} impl FLASH { #[doc = r"Pointer to the register block"] pub const PTR: *const flash::RegisterBlock = 0x4002_2000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const flash::RegisterBlock { Self::PTR } } impl Deref for FLASH { type Target = flash::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for FLASH { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FLASH").finish() } } #[doc = "Flash"] pub mod flash { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Access control register"] pub acr: ACR, _reserved1: [u8; 0x04], #[doc = "0x08 - Flash key register"] pub keyr: KEYR, #[doc = "0x0c - Option byte key register"] pub optkeyr: OPTKEYR, #[doc = "0x10 - Status register"] pub sr: SR, #[doc = "0x14 - Flash control register"] pub cr: CR, _reserved5: [u8; 0x08], #[doc = "0x20 - Flash option register"] pub optr: OPTR, #[doc = "0x24 - Flash SDK address register"] pub sdkr: SDKR, _reserved7: [u8; 0x04], #[doc = "0x2c - Flash WRP address register"] pub wrpr: WRPR, _reserved8: [u8; 0x60], #[doc = "0x90 - Flash sleep time config register"] pub stcr: STCR, _reserved9: [u8; 0x6c], #[doc = "0x100 - Flash TS0 register"] pub ts0: TS0, #[doc = "0x104 - Flash TS1 register"] pub ts1: TS1, #[doc = "0x108 - Flash TS2P register"] pub ts2p: TS2P, #[doc = "0x10c - Flash TPS3 register"] pub tps3: TPS3, #[doc = "0x110 - Flash TS3 register"] pub ts3: TS3, #[doc = "0x114 - Flash PERTPE register"] pub pertpe: PERTPE, #[doc = "0x118 - Flash SMERTPE register"] pub smertpe: SMERTPE, #[doc = "0x11c - Flash PRGTPE register"] pub prgtpe: PRGTPE, #[doc = "0x120 - Flash PRETPE register"] pub pretpe: PRETPE, } #[doc = "ACR (rw) register accessor: an alias for `Reg`"] pub type ACR = crate::Reg; #[doc = "Access control register"] pub mod acr { #[doc = "Register `ACR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `ACR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LATENCY` reader - Latency"] pub type LATENCY_R = crate::BitReader; #[doc = "Field `LATENCY` writer - Latency"] pub type LATENCY_W<'a, const O: u8> = crate::BitWriter<'a, ACR_SPEC, O>; impl R { #[doc = "Bit 0 - Latency"] #[inline(always)] pub fn latency(&self) -> LATENCY_R { LATENCY_R::new((self.bits & 1) != 0) } } impl W { #[doc = "Bit 0 - Latency"] #[inline(always)] #[must_use] pub fn latency(&mut self) -> LATENCY_W<0> { LATENCY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Access control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acr](index.html) module"] pub struct ACR_SPEC; impl crate::RegisterSpec for ACR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [acr::R](R) reader structure"] impl crate::Readable for ACR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [acr::W](W) writer structure"] impl crate::Writable for ACR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets ACR to value 0x0600"] impl crate::Resettable for ACR_SPEC { const RESET_VALUE: Self::Ux = 0x0600; } } #[doc = "KEYR (w) register accessor: an alias for `Reg`"] pub type KEYR = crate::Reg; #[doc = "Flash key register"] pub mod keyr { #[doc = "Register `KEYR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `KEY` writer - Flash key"] pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, KEYR_SPEC, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Flash key"] #[inline(always)] #[must_use] pub fn key(&mut self) -> KEY_W<0> { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [keyr](index.html) module"] pub struct KEYR_SPEC; impl crate::RegisterSpec for KEYR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [keyr::W](W) writer structure"] impl crate::Writable for KEYR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets KEYR to value 0"] impl crate::Resettable for KEYR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "OPTKEYR (w) register accessor: an alias for `Reg`"] pub type OPTKEYR = crate::Reg; #[doc = "Option byte key register"] pub mod optkeyr { #[doc = "Register `OPTKEYR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `OPTKEY` writer - Option byte key"] pub type OPTKEY_W<'a, const O: u8> = crate::FieldWriter<'a, OPTKEYR_SPEC, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Option byte key"] #[inline(always)] #[must_use] pub fn optkey(&mut self) -> OPTKEY_W<0> { OPTKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Option byte key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [optkeyr](index.html) module"] pub struct OPTKEYR_SPEC; impl crate::RegisterSpec for OPTKEYR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [optkeyr::W](W) writer structure"] impl crate::Writable for OPTKEYR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OPTKEYR to value 0"] impl crate::Resettable for OPTKEYR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "Status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `EOP` reader - End of operation"] pub type EOP_R = crate::BitReader; #[doc = "Field `EOP` writer - End of operation"] pub type EOP_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `WRPERR` reader - Write protected error"] pub type WRPERR_R = crate::BitReader; #[doc = "Field `WRPERR` writer - Write protected error"] pub type WRPERR_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `OPTVERR` reader - Option and Engineering bits loading validity error"] pub type OPTVERR_R = crate::BitReader; #[doc = "Field `OPTVERR` writer - Option and Engineering bits loading validity error"] pub type OPTVERR_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; #[doc = "Field `BSY` reader - Busy"] pub type BSY_R = crate::BitReader; #[doc = "Field `BSY` writer - Busy"] pub type BSY_W<'a, const O: u8> = crate::BitWriter<'a, SR_SPEC, O>; impl R { #[doc = "Bit 0 - End of operation"] #[inline(always)] pub fn eop(&self) -> EOP_R { EOP_R::new((self.bits & 1) != 0) } #[doc = "Bit 4 - Write protected error"] #[inline(always)] pub fn wrperr(&self) -> WRPERR_R { WRPERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 15 - Option and Engineering bits loading validity error"] #[inline(always)] pub fn optverr(&self) -> OPTVERR_R { OPTVERR_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Busy"] #[inline(always)] pub fn bsy(&self) -> BSY_R { BSY_R::new(((self.bits >> 16) & 1) != 0) } } impl W { #[doc = "Bit 0 - End of operation"] #[inline(always)] #[must_use] pub fn eop(&mut self) -> EOP_W<0> { EOP_W::new(self) } #[doc = "Bit 4 - Write protected error"] #[inline(always)] #[must_use] pub fn wrperr(&mut self) -> WRPERR_W<4> { WRPERR_W::new(self) } #[doc = "Bit 15 - Option and Engineering bits loading validity error"] #[inline(always)] #[must_use] pub fn optverr(&mut self) -> OPTVERR_W<15> { OPTVERR_W::new(self) } #[doc = "Bit 16 - Busy"] #[inline(always)] #[must_use] pub fn bsy(&mut self) -> BSY_W<16> { BSY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Flash control register"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PG` reader - Programming"] pub type PG_R = crate::BitReader; #[doc = "Field `PG` writer - Programming"] pub type PG_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `PER` reader - Page erase"] pub type PER_R = crate::BitReader; #[doc = "Field `PER` writer - Page erase"] pub type PER_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `MER` reader - Mass erase"] pub type MER_R = crate::BitReader; #[doc = "Field `MER` writer - Mass erase"] pub type MER_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `SER` reader - Sector erase"] pub type SER_R = crate::BitReader; #[doc = "Field `SER` writer - Sector erase"] pub type SER_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `OPTSTRT` reader - Option byte program start"] pub type OPTSTRT_R = crate::BitReader; #[doc = "Field `OPTSTRT` writer - Option byte program start"] pub type OPTSTRT_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `PGTSTRT` reader - Flash main memory program start"] pub type PGTSTRT_R = crate::BitReader; #[doc = "Field `PGTSTRT` writer - Flash main memory program start"] pub type PGTSTRT_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `EOPIE` reader - End of operation interrupt enable"] pub type EOPIE_R = crate::BitReader; #[doc = "Field `EOPIE` writer - End of operation interrupt enable"] pub type EOPIE_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `ERRIE` reader - Error interrupt enable"] pub type ERRIE_R = crate::BitReader; #[doc = "Field `ERRIE` writer - Error interrupt enable"] pub type ERRIE_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `OBL_LAUNCH` reader - Force the option byte loading"] pub type OBL_LAUNCH_R = crate::BitReader; #[doc = "Field `OBL_LAUNCH` writer - Force the option byte loading"] pub type OBL_LAUNCH_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `OPTLOCK` reader - Options Lock"] pub type OPTLOCK_R = crate::BitReader; #[doc = "Field `OPTLOCK` writer - Options Lock"] pub type OPTLOCK_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `LOCK` reader - FLASH_CR Lock"] pub type LOCK_R = crate::BitReader; #[doc = "Field `LOCK` writer - FLASH_CR Lock"] pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl R { #[doc = "Bit 0 - Programming"] #[inline(always)] pub fn pg(&self) -> PG_R { PG_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Page erase"] #[inline(always)] pub fn per(&self) -> PER_R { PER_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Mass erase"] #[inline(always)] pub fn mer(&self) -> MER_R { MER_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 11 - Sector erase"] #[inline(always)] pub fn ser(&self) -> SER_R { SER_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 17 - Option byte program start"] #[inline(always)] pub fn optstrt(&self) -> OPTSTRT_R { OPTSTRT_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 19 - Flash main memory program start"] #[inline(always)] pub fn pgtstrt(&self) -> PGTSTRT_R { PGTSTRT_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 24 - End of operation interrupt enable"] #[inline(always)] pub fn eopie(&self) -> EOPIE_R { EOPIE_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - Error interrupt enable"] #[inline(always)] pub fn errie(&self) -> ERRIE_R { ERRIE_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 27 - Force the option byte loading"] #[inline(always)] pub fn obl_launch(&self) -> OBL_LAUNCH_R { OBL_LAUNCH_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 30 - Options Lock"] #[inline(always)] pub fn optlock(&self) -> OPTLOCK_R { OPTLOCK_R::new(((self.bits >> 30) & 1) != 0) } #[doc = "Bit 31 - FLASH_CR Lock"] #[inline(always)] pub fn lock(&self) -> LOCK_R { LOCK_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 0 - Programming"] #[inline(always)] #[must_use] pub fn pg(&mut self) -> PG_W<0> { PG_W::new(self) } #[doc = "Bit 1 - Page erase"] #[inline(always)] #[must_use] pub fn per(&mut self) -> PER_W<1> { PER_W::new(self) } #[doc = "Bit 2 - Mass erase"] #[inline(always)] #[must_use] pub fn mer(&mut self) -> MER_W<2> { MER_W::new(self) } #[doc = "Bit 11 - Sector erase"] #[inline(always)] #[must_use] pub fn ser(&mut self) -> SER_W<11> { SER_W::new(self) } #[doc = "Bit 17 - Option byte program start"] #[inline(always)] #[must_use] pub fn optstrt(&mut self) -> OPTSTRT_W<17> { OPTSTRT_W::new(self) } #[doc = "Bit 19 - Flash main memory program start"] #[inline(always)] #[must_use] pub fn pgtstrt(&mut self) -> PGTSTRT_W<19> { PGTSTRT_W::new(self) } #[doc = "Bit 24 - End of operation interrupt enable"] #[inline(always)] #[must_use] pub fn eopie(&mut self) -> EOPIE_W<24> { EOPIE_W::new(self) } #[doc = "Bit 25 - Error interrupt enable"] #[inline(always)] #[must_use] pub fn errie(&mut self) -> ERRIE_W<25> { ERRIE_W::new(self) } #[doc = "Bit 27 - Force the option byte loading"] #[inline(always)] #[must_use] pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<27> { OBL_LAUNCH_W::new(self) } #[doc = "Bit 30 - Options Lock"] #[inline(always)] #[must_use] pub fn optlock(&mut self) -> OPTLOCK_W<30> { OPTLOCK_W::new(self) } #[doc = "Bit 31 - FLASH_CR Lock"] #[inline(always)] #[must_use] pub fn lock(&mut self) -> LOCK_W<31> { LOCK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0xc000_0000"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0xc000_0000; } } #[doc = "OPTR (rw) register accessor: an alias for `Reg`"] pub type OPTR = crate::Reg; #[doc = "Flash option register"] pub mod optr { #[doc = "Register `OPTR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OPTR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RDP` reader - Read Protection"] pub type RDP_R = crate::FieldReader; #[doc = "Field `RDP` writer - Read Protection"] pub type RDP_W<'a, const O: u8> = crate::FieldWriter<'a, OPTR_SPEC, 8, O>; #[doc = "Field `BOREN` reader - BOR reset Level"] pub type BOREN_R = crate::BitReader; #[doc = "Field `BOREN` writer - BOR reset Level"] pub type BOREN_W<'a, const O: u8> = crate::BitWriter<'a, OPTR_SPEC, O>; #[doc = "Field `BORF_LEV` reader - These bits contain the VDD supply level threshold that activates the reset"] pub type BORF_LEV_R = crate::FieldReader; #[doc = "Field `BORF_LEV` writer - These bits contain the VDD supply level threshold that activates the reset"] pub type BORF_LEV_W<'a, const O: u8> = crate::FieldWriter<'a, OPTR_SPEC, 3, O>; #[doc = "Field `IDWG_SW` reader - Independent watchdog selection"] pub type IDWG_SW_R = crate::BitReader; #[doc = "Field `IDWG_SW` writer - Independent watchdog selection"] pub type IDWG_SW_W<'a, const O: u8> = crate::BitWriter<'a, OPTR_SPEC, O>; #[doc = "Field `WWDG_SW` reader - Window watchdog selection"] pub type WWDG_SW_R = crate::BitReader; #[doc = "Field `WWDG_SW` writer - Window watchdog selection"] pub type WWDG_SW_W<'a, const O: u8> = crate::BitWriter<'a, OPTR_SPEC, O>; #[doc = "Field `NRST_MODE` reader - NRST_MODE"] pub type NRST_MODE_R = crate::BitReader; #[doc = "Field `NRST_MODE` writer - NRST_MODE"] pub type NRST_MODE_W<'a, const O: u8> = crate::BitWriter<'a, OPTR_SPEC, O>; #[doc = "Field `nBOOT1` reader - Boot configuration"] pub type N_BOOT1_R = crate::BitReader; #[doc = "Field `nBOOT1` writer - Boot configuration"] pub type N_BOOT1_W<'a, const O: u8> = crate::BitWriter<'a, OPTR_SPEC, O>; impl R { #[doc = "Bits 0:7 - Read Protection"] #[inline(always)] pub fn rdp(&self) -> RDP_R { RDP_R::new((self.bits & 0xff) as u8) } #[doc = "Bit 8 - BOR reset Level"] #[inline(always)] pub fn boren(&self) -> BOREN_R { BOREN_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bits 9:11 - These bits contain the VDD supply level threshold that activates the reset"] #[inline(always)] pub fn borf_lev(&self) -> BORF_LEV_R { BORF_LEV_R::new(((self.bits >> 9) & 7) as u8) } #[doc = "Bit 12 - Independent watchdog selection"] #[inline(always)] pub fn idwg_sw(&self) -> IDWG_SW_R { IDWG_SW_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Window watchdog selection"] #[inline(always)] pub fn wwdg_sw(&self) -> WWDG_SW_R { WWDG_SW_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - NRST_MODE"] #[inline(always)] pub fn nrst_mode(&self) -> NRST_MODE_R { NRST_MODE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Boot configuration"] #[inline(always)] pub fn n_boot1(&self) -> N_BOOT1_R { N_BOOT1_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:7 - Read Protection"] #[inline(always)] #[must_use] pub fn rdp(&mut self) -> RDP_W<0> { RDP_W::new(self) } #[doc = "Bit 8 - BOR reset Level"] #[inline(always)] #[must_use] pub fn boren(&mut self) -> BOREN_W<8> { BOREN_W::new(self) } #[doc = "Bits 9:11 - These bits contain the VDD supply level threshold that activates the reset"] #[inline(always)] #[must_use] pub fn borf_lev(&mut self) -> BORF_LEV_W<9> { BORF_LEV_W::new(self) } #[doc = "Bit 12 - Independent watchdog selection"] #[inline(always)] #[must_use] pub fn idwg_sw(&mut self) -> IDWG_SW_W<12> { IDWG_SW_W::new(self) } #[doc = "Bit 13 - Window watchdog selection"] #[inline(always)] #[must_use] pub fn wwdg_sw(&mut self) -> WWDG_SW_W<13> { WWDG_SW_W::new(self) } #[doc = "Bit 14 - NRST_MODE"] #[inline(always)] #[must_use] pub fn nrst_mode(&mut self) -> NRST_MODE_W<14> { NRST_MODE_W::new(self) } #[doc = "Bit 15 - Boot configuration"] #[inline(always)] #[must_use] pub fn n_boot1(&mut self) -> N_BOOT1_W<15> { N_BOOT1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash option register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [optr](index.html) module"] pub struct OPTR_SPEC; impl crate::RegisterSpec for OPTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [optr::R](R) reader structure"] impl crate::Readable for OPTR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [optr::W](W) writer structure"] impl crate::Writable for OPTR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OPTR to value 0x4f55_b0aa"] impl crate::Resettable for OPTR_SPEC { const RESET_VALUE: Self::Ux = 0x4f55_b0aa; } } #[doc = "SDKR (rw) register accessor: an alias for `Reg`"] pub type SDKR = crate::Reg; #[doc = "Flash SDK address register"] pub mod sdkr { #[doc = "Register `SDKR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SDKR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SDK_STRT` reader - SDK area start address"] pub type SDK_STRT_R = crate::FieldReader; #[doc = "Field `SDK_STRT` writer - SDK area start address"] pub type SDK_STRT_W<'a, const O: u8> = crate::FieldWriter<'a, SDKR_SPEC, 5, O>; #[doc = "Field `SDK_END` reader - SDK area end address"] pub type SDK_END_R = crate::FieldReader; #[doc = "Field `SDK_END` writer - SDK area end address"] pub type SDK_END_W<'a, const O: u8> = crate::FieldWriter<'a, SDKR_SPEC, 5, O>; impl R { #[doc = "Bits 0:4 - SDK area start address"] #[inline(always)] pub fn sdk_strt(&self) -> SDK_STRT_R { SDK_STRT_R::new((self.bits & 0x1f) as u8) } #[doc = "Bits 8:12 - SDK area end address"] #[inline(always)] pub fn sdk_end(&self) -> SDK_END_R { SDK_END_R::new(((self.bits >> 8) & 0x1f) as u8) } } impl W { #[doc = "Bits 0:4 - SDK area start address"] #[inline(always)] #[must_use] pub fn sdk_strt(&mut self) -> SDK_STRT_W<0> { SDK_STRT_W::new(self) } #[doc = "Bits 8:12 - SDK area end address"] #[inline(always)] #[must_use] pub fn sdk_end(&mut self) -> SDK_END_W<8> { SDK_END_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash SDK address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdkr](index.html) module"] pub struct SDKR_SPEC; impl crate::RegisterSpec for SDKR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sdkr::R](R) reader structure"] impl crate::Readable for SDKR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sdkr::W](W) writer structure"] impl crate::Writable for SDKR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SDKR to value 0xffe0_001f"] impl crate::Resettable for SDKR_SPEC { const RESET_VALUE: Self::Ux = 0xffe0_001f; } } #[doc = "WRPR (rw) register accessor: an alias for `Reg`"] pub type WRPR = crate::Reg; #[doc = "Flash WRP address register"] pub mod wrpr { #[doc = "Register `WRPR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `WRPR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `WRP` reader - WRP address"] pub type WRP_R = crate::FieldReader; #[doc = "Field `WRP` writer - WRP address"] pub type WRP_W<'a, const O: u8> = crate::FieldWriter<'a, WRPR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - WRP address"] #[inline(always)] pub fn wrp(&self) -> WRP_R { WRP_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - WRP address"] #[inline(always)] #[must_use] pub fn wrp(&mut self) -> WRP_W<0> { WRP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash WRP address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrpr](index.html) module"] pub struct WRPR_SPEC; impl crate::RegisterSpec for WRPR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [wrpr::R](R) reader structure"] impl crate::Readable for WRPR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [wrpr::W](W) writer structure"] impl crate::Writable for WRPR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets WRPR to value 0xffff"] impl crate::Resettable for WRPR_SPEC { const RESET_VALUE: Self::Ux = 0xffff; } } #[doc = "STCR (rw) register accessor: an alias for `Reg`"] pub type STCR = crate::Reg; #[doc = "Flash sleep time config register"] pub mod stcr { #[doc = "Register `STCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `STCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SLEEP_EN` reader - FLash sleep enable"] pub type SLEEP_EN_R = crate::BitReader; #[doc = "Field `SLEEP_EN` writer - FLash sleep enable"] pub type SLEEP_EN_W<'a, const O: u8> = crate::BitWriter<'a, STCR_SPEC, O>; #[doc = "Field `SLEEP_TIME` reader - FLash sleep time configuration(counter based on HSI_10M)"] pub type SLEEP_TIME_R = crate::FieldReader; #[doc = "Field `SLEEP_TIME` writer - FLash sleep time configuration(counter based on HSI_10M)"] pub type SLEEP_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, STCR_SPEC, 8, O>; impl R { #[doc = "Bit 0 - FLash sleep enable"] #[inline(always)] pub fn sleep_en(&self) -> SLEEP_EN_R { SLEEP_EN_R::new((self.bits & 1) != 0) } #[doc = "Bits 8:15 - FLash sleep time configuration(counter based on HSI_10M)"] #[inline(always)] pub fn sleep_time(&self) -> SLEEP_TIME_R { SLEEP_TIME_R::new(((self.bits >> 8) & 0xff) as u8) } } impl W { #[doc = "Bit 0 - FLash sleep enable"] #[inline(always)] #[must_use] pub fn sleep_en(&mut self) -> SLEEP_EN_W<0> { SLEEP_EN_W::new(self) } #[doc = "Bits 8:15 - FLash sleep time configuration(counter based on HSI_10M)"] #[inline(always)] #[must_use] pub fn sleep_time(&mut self) -> SLEEP_TIME_W<8> { SLEEP_TIME_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash sleep time config register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stcr](index.html) module"] pub struct STCR_SPEC; impl crate::RegisterSpec for STCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [stcr::R](R) reader structure"] impl crate::Readable for STCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [stcr::W](W) writer structure"] impl crate::Writable for STCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets STCR to value 0x6400"] impl crate::Resettable for STCR_SPEC { const RESET_VALUE: Self::Ux = 0x6400; } } #[doc = "TS0 (rw) register accessor: an alias for `Reg`"] pub type TS0 = crate::Reg; #[doc = "Flash TS0 register"] pub mod ts0 { #[doc = "Register `TS0` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TS0` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TS0` reader - FLash TS0 register"] pub type TS0_R = crate::FieldReader; #[doc = "Field `TS0` writer - FLash TS0 register"] pub type TS0_W<'a, const O: u8> = crate::FieldWriter<'a, TS0_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - FLash TS0 register"] #[inline(always)] pub fn ts0(&self) -> TS0_R { TS0_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - FLash TS0 register"] #[inline(always)] #[must_use] pub fn ts0(&mut self) -> TS0_W<0> { TS0_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash TS0 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ts0](index.html) module"] pub struct TS0_SPEC; impl crate::RegisterSpec for TS0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ts0::R](R) reader structure"] impl crate::Readable for TS0_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ts0::W](W) writer structure"] impl crate::Writable for TS0_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TS0 to value 0xb4"] impl crate::Resettable for TS0_SPEC { const RESET_VALUE: Self::Ux = 0xb4; } } #[doc = "TS1 (rw) register accessor: an alias for `Reg`"] pub type TS1 = crate::Reg; #[doc = "Flash TS1 register"] pub mod ts1 { #[doc = "Register `TS1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TS1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TS1` reader - FLash TS1 register"] pub type TS1_R = crate::FieldReader; #[doc = "Field `TS1` writer - FLash TS1 register"] pub type TS1_W<'a, const O: u8> = crate::FieldWriter<'a, TS1_SPEC, 9, O, u16>; impl R { #[doc = "Bits 0:8 - FLash TS1 register"] #[inline(always)] pub fn ts1(&self) -> TS1_R { TS1_R::new((self.bits & 0x01ff) as u16) } } impl W { #[doc = "Bits 0:8 - FLash TS1 register"] #[inline(always)] #[must_use] pub fn ts1(&mut self) -> TS1_W<0> { TS1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash TS1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ts1](index.html) module"] pub struct TS1_SPEC; impl crate::RegisterSpec for TS1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ts1::R](R) reader structure"] impl crate::Readable for TS1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ts1::W](W) writer structure"] impl crate::Writable for TS1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TS1 to value 0x01b0"] impl crate::Resettable for TS1_SPEC { const RESET_VALUE: Self::Ux = 0x01b0; } } #[doc = "TS2P (rw) register accessor: an alias for `Reg`"] pub type TS2P = crate::Reg; #[doc = "Flash TS2P register"] pub mod ts2p { #[doc = "Register `TS2P` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TS2P` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TS2P` reader - FLash TS2P register"] pub type TS2P_R = crate::FieldReader; #[doc = "Field `TS2P` writer - FLash TS2P register"] pub type TS2P_W<'a, const O: u8> = crate::FieldWriter<'a, TS2P_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - FLash TS2P register"] #[inline(always)] pub fn ts2p(&self) -> TS2P_R { TS2P_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - FLash TS2P register"] #[inline(always)] #[must_use] pub fn ts2p(&mut self) -> TS2P_W<0> { TS2P_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash TS2P register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ts2p](index.html) module"] pub struct TS2P_SPEC; impl crate::RegisterSpec for TS2P_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ts2p::R](R) reader structure"] impl crate::Readable for TS2P_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ts2p::W](W) writer structure"] impl crate::Writable for TS2P_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TS2P to value 0xb4"] impl crate::Resettable for TS2P_SPEC { const RESET_VALUE: Self::Ux = 0xb4; } } #[doc = "TPS3 (rw) register accessor: an alias for `Reg`"] pub type TPS3 = crate::Reg; #[doc = "Flash TPS3 register"] pub mod tps3 { #[doc = "Register `TPS3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TPS3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TPS3` reader - FLash TPS3 register"] pub type TPS3_R = crate::FieldReader; #[doc = "Field `TPS3` writer - FLash TPS3 register"] pub type TPS3_W<'a, const O: u8> = crate::FieldWriter<'a, TPS3_SPEC, 11, O, u16>; impl R { #[doc = "Bits 0:10 - FLash TPS3 register"] #[inline(always)] pub fn tps3(&self) -> TPS3_R { TPS3_R::new((self.bits & 0x07ff) as u16) } } impl W { #[doc = "Bits 0:10 - FLash TPS3 register"] #[inline(always)] #[must_use] pub fn tps3(&mut self) -> TPS3_W<0> { TPS3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash TPS3 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tps3](index.html) module"] pub struct TPS3_SPEC; impl crate::RegisterSpec for TPS3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [tps3::R](R) reader structure"] impl crate::Readable for TPS3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [tps3::W](W) writer structure"] impl crate::Writable for TPS3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TPS3 to value 0x06c0"] impl crate::Resettable for TPS3_SPEC { const RESET_VALUE: Self::Ux = 0x06c0; } } #[doc = "TS3 (rw) register accessor: an alias for `Reg`"] pub type TS3 = crate::Reg; #[doc = "Flash TS3 register"] pub mod ts3 { #[doc = "Register `TS3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TS3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TS3` reader - FLash TS3 register"] pub type TS3_R = crate::FieldReader; #[doc = "Field `TS3` writer - FLash TS3 register"] pub type TS3_W<'a, const O: u8> = crate::FieldWriter<'a, TS3_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - FLash TS3 register"] #[inline(always)] pub fn ts3(&self) -> TS3_R { TS3_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - FLash TS3 register"] #[inline(always)] #[must_use] pub fn ts3(&mut self) -> TS3_W<0> { TS3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash TS3 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ts3](index.html) module"] pub struct TS3_SPEC; impl crate::RegisterSpec for TS3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ts3::R](R) reader structure"] impl crate::Readable for TS3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ts3::W](W) writer structure"] impl crate::Writable for TS3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TS3 to value 0xb4"] impl crate::Resettable for TS3_SPEC { const RESET_VALUE: Self::Ux = 0xb4; } } #[doc = "PERTPE (rw) register accessor: an alias for `Reg`"] pub type PERTPE = crate::Reg; #[doc = "Flash PERTPE register"] pub mod pertpe { #[doc = "Register `PERTPE` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PERTPE` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PERTPE` reader - FLash PERTPE register"] pub type PERTPE_R = crate::FieldReader; #[doc = "Field `PERTPE` writer - FLash PERTPE register"] pub type PERTPE_W<'a, const O: u8> = crate::FieldWriter<'a, PERTPE_SPEC, 17, O, u32>; impl R { #[doc = "Bits 0:16 - FLash PERTPE register"] #[inline(always)] pub fn pertpe(&self) -> PERTPE_R { PERTPE_R::new(self.bits & 0x0001_ffff) } } impl W { #[doc = "Bits 0:16 - FLash PERTPE register"] #[inline(always)] #[must_use] pub fn pertpe(&mut self) -> PERTPE_W<0> { PERTPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash PERTPE register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pertpe](index.html) module"] pub struct PERTPE_SPEC; impl crate::RegisterSpec for PERTPE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pertpe::R](R) reader structure"] impl crate::Readable for PERTPE_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pertpe::W](W) writer structure"] impl crate::Writable for PERTPE_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PERTPE to value 0xea60"] impl crate::Resettable for PERTPE_SPEC { const RESET_VALUE: Self::Ux = 0xea60; } } #[doc = "SMERTPE (rw) register accessor: an alias for `Reg`"] pub type SMERTPE = crate::Reg; #[doc = "Flash SMERTPE register"] pub mod smertpe { #[doc = "Register `SMERTPE` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SMERTPE` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SMERTPE` reader - FLash SMERTPE register"] pub type SMERTPE_R = crate::FieldReader; #[doc = "Field `SMERTPE` writer - FLash SMERTPE register"] pub type SMERTPE_W<'a, const O: u8> = crate::FieldWriter<'a, SMERTPE_SPEC, 17, O, u32>; impl R { #[doc = "Bits 0:16 - FLash SMERTPE register"] #[inline(always)] pub fn smertpe(&self) -> SMERTPE_R { SMERTPE_R::new(self.bits & 0x0001_ffff) } } impl W { #[doc = "Bits 0:16 - FLash SMERTPE register"] #[inline(always)] #[must_use] pub fn smertpe(&mut self) -> SMERTPE_W<0> { SMERTPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash SMERTPE register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smertpe](index.html) module"] pub struct SMERTPE_SPEC; impl crate::RegisterSpec for SMERTPE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [smertpe::R](R) reader structure"] impl crate::Readable for SMERTPE_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [smertpe::W](W) writer structure"] impl crate::Writable for SMERTPE_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SMERTPE to value 0xfd20"] impl crate::Resettable for SMERTPE_SPEC { const RESET_VALUE: Self::Ux = 0xfd20; } } #[doc = "PRGTPE (rw) register accessor: an alias for `Reg`"] pub type PRGTPE = crate::Reg; #[doc = "Flash PRGTPE register"] pub mod prgtpe { #[doc = "Register `PRGTPE` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PRGTPE` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PRGTPE` reader - FLash PRGTPE register"] pub type PRGTPE_R = crate::FieldReader; #[doc = "Field `PRGTPE` writer - FLash PRGTPE register"] pub type PRGTPE_W<'a, const O: u8> = crate::FieldWriter<'a, PRGTPE_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FLash PRGTPE register"] #[inline(always)] pub fn prgtpe(&self) -> PRGTPE_R { PRGTPE_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - FLash PRGTPE register"] #[inline(always)] #[must_use] pub fn prgtpe(&mut self) -> PRGTPE_W<0> { PRGTPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash PRGTPE register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prgtpe](index.html) module"] pub struct PRGTPE_SPEC; impl crate::RegisterSpec for PRGTPE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [prgtpe::R](R) reader structure"] impl crate::Readable for PRGTPE_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [prgtpe::W](W) writer structure"] impl crate::Writable for PRGTPE_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PRGTPE to value 0x8ca0"] impl crate::Resettable for PRGTPE_SPEC { const RESET_VALUE: Self::Ux = 0x8ca0; } } #[doc = "PRETPE (rw) register accessor: an alias for `Reg`"] pub type PRETPE = crate::Reg; #[doc = "Flash PRETPE register"] pub mod pretpe { #[doc = "Register `PRETPE` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PRETPE` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PRETPE` reader - FLash PRETPE register"] pub type PRETPE_R = crate::FieldReader; #[doc = "Field `PRETPE` writer - FLash PRETPE register"] pub type PRETPE_W<'a, const O: u8> = crate::FieldWriter<'a, PRETPE_SPEC, 13, O, u16>; impl R { #[doc = "Bits 0:12 - FLash PRETPE register"] #[inline(always)] pub fn pretpe(&self) -> PRETPE_R { PRETPE_R::new((self.bits & 0x1fff) as u16) } } impl W { #[doc = "Bits 0:12 - FLash PRETPE register"] #[inline(always)] #[must_use] pub fn pretpe(&mut self) -> PRETPE_W<0> { PRETPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Flash PRETPE register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pretpe](index.html) module"] pub struct PRETPE_SPEC; impl crate::RegisterSpec for PRETPE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pretpe::R](R) reader structure"] impl crate::Readable for PRETPE_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pretpe::W](W) writer structure"] impl crate::Writable for PRETPE_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PRETPE to value 0x12c0"] impl crate::Resettable for PRETPE_SPEC { const RESET_VALUE: Self::Ux = 0x12c0; } } } #[doc = "CRC calculation unit"] pub struct CRC { _marker: PhantomData<*const ()>, } unsafe impl Send for CRC {} impl CRC { #[doc = r"Pointer to the register block"] pub const PTR: *const crc::RegisterBlock = 0x4002_3000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const crc::RegisterBlock { Self::PTR } } impl Deref for CRC { type Target = crc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for CRC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("CRC").finish() } } #[doc = "CRC calculation unit"] pub mod crc { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Data register"] pub dr: DR, #[doc = "0x04 - Independent Data register"] pub idr: IDR, #[doc = "0x08 - Control register"] pub cr: CR, } #[doc = "DR (rw) register accessor: an alias for `Reg`"] pub type DR = crate::Reg; #[doc = "Data register"] pub mod dr { #[doc = "Register `DR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DR` reader - Data Register"] pub type DR_R = crate::FieldReader; #[doc = "Field `DR` writer - Data Register"] pub type DR_W<'a, const O: u8> = crate::FieldWriter<'a, DR_SPEC, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Data Register"] #[inline(always)] pub fn dr(&self) -> DR_R { DR_R::new(self.bits) } } impl W { #[doc = "Bits 0:31 - Data Register"] #[inline(always)] #[must_use] pub fn dr(&mut self) -> DR_W<0> { DR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr::R](R) reader structure"] impl crate::Readable for DR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] impl crate::Writable for DR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR to value 0xffff_ffff"] impl crate::Resettable for DR_SPEC { const RESET_VALUE: Self::Ux = 0xffff_ffff; } } #[doc = "IDR (rw) register accessor: an alias for `Reg`"] pub type IDR = crate::Reg; #[doc = "Independent Data register"] pub mod idr { #[doc = "Register `IDR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IDR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `IDR` reader - Independent Data register"] pub type IDR_R = crate::FieldReader; #[doc = "Field `IDR` writer - Independent Data register"] pub type IDR_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - Independent Data register"] #[inline(always)] pub fn idr(&self) -> IDR_R { IDR_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - Independent Data register"] #[inline(always)] #[must_use] pub fn idr(&mut self) -> IDR_W<0> { IDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Independent Data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [idr::R](R) reader structure"] impl crate::Readable for IDR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] impl crate::Writable for IDR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IDR to value 0"] impl crate::Resettable for IDR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR (w) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Control register"] pub mod cr { #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RESET` writer - Reset bit"] pub type RESET_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl W { #[doc = "Bit 0 - Reset bit"] #[inline(always)] #[must_use] pub fn reset(&mut self) -> RESET_W<0> { RESET_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Serial peripheral interface"] pub struct SPI1 { _marker: PhantomData<*const ()>, } unsafe impl Send for SPI1 {} impl SPI1 { #[doc = r"Pointer to the register block"] pub const PTR: *const spi1::RegisterBlock = 0x4001_3000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } } impl Deref for SPI1 { type Target = spi1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for SPI1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("SPI1").finish() } } #[doc = "Serial peripheral interface"] pub mod spi1 { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - control register 1"] pub cr1: CR1, #[doc = "0x04 - control register 2"] pub cr2: CR2, #[doc = "0x08 - status register"] pub sr: SR, #[doc = "0x0c - data register"] pub dr: DR, } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "control register 1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CPHA` reader - Clock phase"] pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - Clock phase"] pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `CPOL` reader - Clock polarity"] pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - Clock polarity"] pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `MSTR` reader - Master selection"] pub type MSTR_R = crate::BitReader; #[doc = "Field `MSTR` writer - Master selection"] pub type MSTR_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `BR` reader - Baud rate control"] pub type BR_R = crate::FieldReader; #[doc = "Field `BR` writer - Baud rate control"] pub type BR_W<'a, const O: u8> = crate::FieldWriter<'a, CR1_SPEC, 3, O>; #[doc = "Field `SPE` reader - SPI enable"] pub type SPE_R = crate::BitReader; #[doc = "Field `SPE` writer - SPI enable"] pub type SPE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `LSBFIRST` reader - Frame format"] pub type LSBFIRST_R = crate::BitReader; #[doc = "Field `LSBFIRST` writer - Frame format"] pub type LSBFIRST_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `SSI` reader - Internal slave selection"] pub type SSI_R = crate::BitReader; #[doc = "Field `SSI` writer - Internal slave selection"] pub type SSI_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `SSM` reader - Software slave management"] pub type SSM_R = crate::BitReader; #[doc = "Field `SSM` writer - Software slave management"] pub type SSM_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `RXONLY` reader - Receive only"] pub type RXONLY_R = crate::BitReader; #[doc = "Field `RXONLY` writer - Receive only"] pub type RXONLY_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `BIDIOE` reader - Output enable in bidirectional mode"] pub type BIDIOE_R = crate::BitReader; #[doc = "Field `BIDIOE` writer - Output enable in bidirectional mode"] pub type BIDIOE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `BIDIMODE` reader - Bidirectional data mode enable"] pub type BIDIMODE_R = crate::BitReader; #[doc = "Field `BIDIMODE` writer - Bidirectional data mode enable"] pub type BIDIMODE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; impl R { #[doc = "Bit 0 - Clock phase"] #[inline(always)] pub fn cpha(&self) -> CPHA_R { CPHA_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Clock polarity"] #[inline(always)] pub fn cpol(&self) -> CPOL_R { CPOL_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Master selection"] #[inline(always)] pub fn mstr(&self) -> MSTR_R { MSTR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bits 3:5 - Baud rate control"] #[inline(always)] pub fn br(&self) -> BR_R { BR_R::new(((self.bits >> 3) & 7) as u8) } #[doc = "Bit 6 - SPI enable"] #[inline(always)] pub fn spe(&self) -> SPE_R { SPE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Frame format"] #[inline(always)] pub fn lsbfirst(&self) -> LSBFIRST_R { LSBFIRST_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Internal slave selection"] #[inline(always)] pub fn ssi(&self) -> SSI_R { SSI_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Software slave management"] #[inline(always)] pub fn ssm(&self) -> SSM_R { SSM_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Receive only"] #[inline(always)] pub fn rxonly(&self) -> RXONLY_R { RXONLY_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 14 - Output enable in bidirectional mode"] #[inline(always)] pub fn bidioe(&self) -> BIDIOE_R { BIDIOE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Bidirectional data mode enable"] #[inline(always)] pub fn bidimode(&self) -> BIDIMODE_R { BIDIMODE_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bit 0 - Clock phase"] #[inline(always)] #[must_use] pub fn cpha(&mut self) -> CPHA_W<0> { CPHA_W::new(self) } #[doc = "Bit 1 - Clock polarity"] #[inline(always)] #[must_use] pub fn cpol(&mut self) -> CPOL_W<1> { CPOL_W::new(self) } #[doc = "Bit 2 - Master selection"] #[inline(always)] #[must_use] pub fn mstr(&mut self) -> MSTR_W<2> { MSTR_W::new(self) } #[doc = "Bits 3:5 - Baud rate control"] #[inline(always)] #[must_use] pub fn br(&mut self) -> BR_W<3> { BR_W::new(self) } #[doc = "Bit 6 - SPI enable"] #[inline(always)] #[must_use] pub fn spe(&mut self) -> SPE_W<6> { SPE_W::new(self) } #[doc = "Bit 7 - Frame format"] #[inline(always)] #[must_use] pub fn lsbfirst(&mut self) -> LSBFIRST_W<7> { LSBFIRST_W::new(self) } #[doc = "Bit 8 - Internal slave selection"] #[inline(always)] #[must_use] pub fn ssi(&mut self) -> SSI_W<8> { SSI_W::new(self) } #[doc = "Bit 9 - Software slave management"] #[inline(always)] #[must_use] pub fn ssm(&mut self) -> SSM_W<9> { SSM_W::new(self) } #[doc = "Bit 10 - Receive only"] #[inline(always)] #[must_use] pub fn rxonly(&mut self) -> RXONLY_W<10> { RXONLY_W::new(self) } #[doc = "Bit 14 - Output enable in bidirectional mode"] #[inline(always)] #[must_use] pub fn bidioe(&mut self) -> BIDIOE_W<14> { BIDIOE_W::new(self) } #[doc = "Bit 15 - Bidirectional data mode enable"] #[inline(always)] #[must_use] pub fn bidimode(&mut self) -> BIDIMODE_W<15> { BIDIMODE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RXDMAEN` reader - Rx buffer DMA enable"] pub type RXDMAEN_R = crate::BitReader; #[doc = "Field `RXDMAEN` writer - Rx buffer DMA enable"] pub type RXDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `TXDMAEN` reader - Tx buffer DMA enable"] pub type TXDMAEN_R = crate::BitReader; #[doc = "Field `TXDMAEN` writer - Tx buffer DMA enable"] pub type TXDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `SSOE` reader - SS output enable"] pub type SSOE_R = crate::BitReader; #[doc = "Field `SSOE` writer - SS output enable"] pub type SSOE_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `ERRIE` reader - Error interrupt enable"] pub type ERRIE_R = crate::BitReader; #[doc = "Field `ERRIE` writer - Error interrupt enable"] pub type ERRIE_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `RXNEIE` reader - RX buffer not empty interrupt enable"] pub type RXNEIE_R = crate::BitReader; #[doc = "Field `RXNEIE` writer - RX buffer not empty interrupt enable"] pub type RXNEIE_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `TXEIE` reader - Tx buffer empty interrupt enable"] pub type TXEIE_R = crate::BitReader; #[doc = "Field `TXEIE` writer - Tx buffer empty interrupt enable"] pub type TXEIE_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `DS` reader - Data length"] pub type DS_R = crate::BitReader; #[doc = "Field `DS` writer - Data length"] pub type DS_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `FRXTH` reader - FIFO reception threshold"] pub type FRXTH_R = crate::BitReader; #[doc = "Field `FRXTH` writer - FIFO reception threshold"] pub type FRXTH_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `LDMA_RX` reader - Last DAM Transmit(RX)"] pub type LDMA_RX_R = crate::BitReader; #[doc = "Field `LDMA_RX` writer - Last DAM Transmit(RX)"] pub type LDMA_RX_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `LDMA_TX` reader - Last DAM Transmit(TX)"] pub type LDMA_TX_R = crate::BitReader; #[doc = "Field `LDMA_TX` writer - Last DAM Transmit(TX)"] pub type LDMA_TX_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `SLVFM` reader - Slave fast mode enable"] pub type SLVFM_R = crate::BitReader; #[doc = "Field `SLVFM` writer - Slave fast mode enable"] pub type SLVFM_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; impl R { #[doc = "Bit 0 - Rx buffer DMA enable"] #[inline(always)] pub fn rxdmaen(&self) -> RXDMAEN_R { RXDMAEN_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Tx buffer DMA enable"] #[inline(always)] pub fn txdmaen(&self) -> TXDMAEN_R { TXDMAEN_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - SS output enable"] #[inline(always)] pub fn ssoe(&self) -> SSOE_R { SSOE_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 5 - Error interrupt enable"] #[inline(always)] pub fn errie(&self) -> ERRIE_R { ERRIE_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - RX buffer not empty interrupt enable"] #[inline(always)] pub fn rxneie(&self) -> RXNEIE_R { RXNEIE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Tx buffer empty interrupt enable"] #[inline(always)] pub fn txeie(&self) -> TXEIE_R { TXEIE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 11 - Data length"] #[inline(always)] pub fn ds(&self) -> DS_R { DS_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - FIFO reception threshold"] #[inline(always)] pub fn frxth(&self) -> FRXTH_R { FRXTH_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Last DAM Transmit(RX)"] #[inline(always)] pub fn ldma_rx(&self) -> LDMA_RX_R { LDMA_RX_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Last DAM Transmit(TX)"] #[inline(always)] pub fn ldma_tx(&self) -> LDMA_TX_R { LDMA_TX_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Slave fast mode enable"] #[inline(always)] pub fn slvfm(&self) -> SLVFM_R { SLVFM_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bit 0 - Rx buffer DMA enable"] #[inline(always)] #[must_use] pub fn rxdmaen(&mut self) -> RXDMAEN_W<0> { RXDMAEN_W::new(self) } #[doc = "Bit 1 - Tx buffer DMA enable"] #[inline(always)] #[must_use] pub fn txdmaen(&mut self) -> TXDMAEN_W<1> { TXDMAEN_W::new(self) } #[doc = "Bit 2 - SS output enable"] #[inline(always)] #[must_use] pub fn ssoe(&mut self) -> SSOE_W<2> { SSOE_W::new(self) } #[doc = "Bit 5 - Error interrupt enable"] #[inline(always)] #[must_use] pub fn errie(&mut self) -> ERRIE_W<5> { ERRIE_W::new(self) } #[doc = "Bit 6 - RX buffer not empty interrupt enable"] #[inline(always)] #[must_use] pub fn rxneie(&mut self) -> RXNEIE_W<6> { RXNEIE_W::new(self) } #[doc = "Bit 7 - Tx buffer empty interrupt enable"] #[inline(always)] #[must_use] pub fn txeie(&mut self) -> TXEIE_W<7> { TXEIE_W::new(self) } #[doc = "Bit 11 - Data length"] #[inline(always)] #[must_use] pub fn ds(&mut self) -> DS_W<11> { DS_W::new(self) } #[doc = "Bit 12 - FIFO reception threshold"] #[inline(always)] #[must_use] pub fn frxth(&mut self) -> FRXTH_W<12> { FRXTH_W::new(self) } #[doc = "Bit 13 - Last DAM Transmit(RX)"] #[inline(always)] #[must_use] pub fn ldma_rx(&mut self) -> LDMA_RX_W<13> { LDMA_RX_W::new(self) } #[doc = "Bit 14 - Last DAM Transmit(TX)"] #[inline(always)] #[must_use] pub fn ldma_tx(&mut self) -> LDMA_TX_W<14> { LDMA_TX_W::new(self) } #[doc = "Bit 15 - Slave fast mode enable"] #[inline(always)] #[must_use] pub fn slvfm(&mut self) -> SLVFM_W<15> { SLVFM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR (rw) register accessor: an alias for `Reg`"] pub type SR = crate::Reg; #[doc = "status register"] pub mod sr { #[doc = "Register `SR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RXNE` reader - Receive buffer not empty"] pub type RXNE_R = crate::BitReader; #[doc = "Field `TXE` reader - Transmit buffer empty"] pub type TXE_R = crate::BitReader; #[doc = "Field `MODF` reader - Mode fault"] pub type MODF_R = crate::BitReader; #[doc = "Field `OVR` reader - Overrun flag"] pub type OVR_R = crate::BitReader; #[doc = "Field `BSY` reader - Busy flag"] pub type BSY_R = crate::BitReader; #[doc = "Field `FRLVL` reader - FIFO reception level"] pub type FRLVL_R = crate::FieldReader; #[doc = "Field `FTLVL` reader - FIFO transmission level"] pub type FTLVL_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Receive buffer not empty"] #[inline(always)] pub fn rxne(&self) -> RXNE_R { RXNE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Transmit buffer empty"] #[inline(always)] pub fn txe(&self) -> TXE_R { TXE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 5 - Mode fault"] #[inline(always)] pub fn modf(&self) -> MODF_R { MODF_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Overrun flag"] #[inline(always)] pub fn ovr(&self) -> OVR_R { OVR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Busy flag"] #[inline(always)] pub fn bsy(&self) -> BSY_R { BSY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 9:10 - FIFO reception level"] #[inline(always)] pub fn frlvl(&self) -> FRLVL_R { FRLVL_R::new(((self.bits >> 9) & 3) as u8) } #[doc = "Bits 11:12 - FIFO transmission level"] #[inline(always)] pub fn ftlvl(&self) -> FTLVL_R { FTLVL_R::new(((self.bits >> 11) & 3) as u8) } } impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr::R](R) reader structure"] impl crate::Readable for SR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] impl crate::Writable for SR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR to value 0x02"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0x02; } } #[doc = "DR (rw) register accessor: an alias for `Reg`"] pub type DR = crate::Reg; #[doc = "data register"] pub mod dr { #[doc = "Register `DR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DR` reader - Data register"] pub type DR_R = crate::FieldReader; #[doc = "Field `DR` writer - Data register"] pub type DR_W<'a, const O: u8> = crate::FieldWriter<'a, DR_SPEC, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data register"] #[inline(always)] pub fn dr(&self) -> DR_R { DR_R::new((self.bits & 0xffff) as u16) } } impl W { #[doc = "Bits 0:15 - Data register"] #[inline(always)] #[must_use] pub fn dr(&mut self) -> DR_W<0> { DR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr::R](R) reader structure"] impl crate::Readable for DR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] impl crate::Writable for DR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR to value 0"] impl crate::Resettable for DR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Serial peripheral interface"] pub struct SPI2 { _marker: PhantomData<*const ()>, } unsafe impl Send for SPI2 {} impl SPI2 { #[doc = r"Pointer to the register block"] pub const PTR: *const spi1::RegisterBlock = 0x4000_3800 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } } impl Deref for SPI2 { type Target = spi1::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for SPI2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("SPI2").finish() } } #[doc = "Serial peripheral interface"] pub use self::spi1 as spi2; #[doc = "Inter integrated circuit"] pub struct I2C { _marker: PhantomData<*const ()>, } unsafe impl Send for I2C {} impl I2C { #[doc = r"Pointer to the register block"] pub const PTR: *const i2c::RegisterBlock = 0x4000_5400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const i2c::RegisterBlock { Self::PTR } } impl Deref for I2C { type Target = i2c::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for I2C { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("I2C").finish() } } #[doc = "Inter integrated circuit"] pub mod i2c { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Control register 1"] pub cr1: CR1, #[doc = "0x04 - Control register 2"] pub cr2: CR2, #[doc = "0x08 - Own address register 1"] pub oar1: OAR1, _reserved3: [u8; 0x04], #[doc = "0x10 - Data register"] pub dr: DR, #[doc = "0x14 - Status register 1"] pub sr1: SR1, #[doc = "0x18 - Status register 2"] pub sr2: SR2, #[doc = "0x1c - Clock control register"] pub ccr: CCR, #[doc = "0x20 - TRISE register"] pub trise: TRISE, } #[doc = "CR1 (rw) register accessor: an alias for `Reg`"] pub type CR1 = crate::Reg; #[doc = "Control register 1"] pub mod cr1 { #[doc = "Register `CR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PE` reader - Peripheral enable"] pub type PE_R = crate::BitReader; #[doc = "Field `PE` writer - Peripheral enable"] pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `ENPEC` reader - PEC enable"] pub type ENPEC_R = crate::BitReader; #[doc = "Field `ENPEC` writer - PEC enable"] pub type ENPEC_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `ENGC` reader - General call enable"] pub type ENGC_R = crate::BitReader; #[doc = "Field `ENGC` writer - General call enable"] pub type ENGC_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `NOSTRETCH` reader - Clock stretching disable (Slave mode)"] pub type NOSTRETCH_R = crate::BitReader; #[doc = "Field `NOSTRETCH` writer - Clock stretching disable (Slave mode)"] pub type NOSTRETCH_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `START` reader - Start generation"] pub type START_R = crate::BitReader; #[doc = "Field `START` writer - Start generation"] pub type START_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `STOP` reader - Stop generation"] pub type STOP_R = crate::BitReader; #[doc = "Field `STOP` writer - Stop generation"] pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `ACK` reader - Acknowledge enable"] pub type ACK_R = crate::BitReader; #[doc = "Field `ACK` writer - Acknowledge enable"] pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `POS` reader - Acknowledge/PEC Position (for data reception)"] pub type POS_R = crate::BitReader; #[doc = "Field `POS` writer - Acknowledge/PEC Position (for data reception)"] pub type POS_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `PEC` reader - Packet error checking"] pub type PEC_R = crate::BitReader; #[doc = "Field `PEC` writer - Packet error checking"] pub type PEC_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; #[doc = "Field `SWRST` reader - Software reset"] pub type SWRST_R = crate::BitReader; #[doc = "Field `SWRST` writer - Software reset"] pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR1_SPEC, O>; impl R { #[doc = "Bit 0 - Peripheral enable"] #[inline(always)] pub fn pe(&self) -> PE_R { PE_R::new((self.bits & 1) != 0) } #[doc = "Bit 5 - PEC enable"] #[inline(always)] pub fn enpec(&self) -> ENPEC_R { ENPEC_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - General call enable"] #[inline(always)] pub fn engc(&self) -> ENGC_R { ENGC_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Clock stretching disable (Slave mode)"] #[inline(always)] pub fn nostretch(&self) -> NOSTRETCH_R { NOSTRETCH_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Start generation"] #[inline(always)] pub fn start(&self) -> START_R { START_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Stop generation"] #[inline(always)] pub fn stop(&self) -> STOP_R { STOP_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Acknowledge enable"] #[inline(always)] pub fn ack(&self) -> ACK_R { ACK_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Acknowledge/PEC Position (for data reception)"] #[inline(always)] pub fn pos(&self) -> POS_R { POS_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Packet error checking"] #[inline(always)] pub fn pec(&self) -> PEC_R { PEC_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 15 - Software reset"] #[inline(always)] pub fn swrst(&self) -> SWRST_R { SWRST_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bit 0 - Peripheral enable"] #[inline(always)] #[must_use] pub fn pe(&mut self) -> PE_W<0> { PE_W::new(self) } #[doc = "Bit 5 - PEC enable"] #[inline(always)] #[must_use] pub fn enpec(&mut self) -> ENPEC_W<5> { ENPEC_W::new(self) } #[doc = "Bit 6 - General call enable"] #[inline(always)] #[must_use] pub fn engc(&mut self) -> ENGC_W<6> { ENGC_W::new(self) } #[doc = "Bit 7 - Clock stretching disable (Slave mode)"] #[inline(always)] #[must_use] pub fn nostretch(&mut self) -> NOSTRETCH_W<7> { NOSTRETCH_W::new(self) } #[doc = "Bit 8 - Start generation"] #[inline(always)] #[must_use] pub fn start(&mut self) -> START_W<8> { START_W::new(self) } #[doc = "Bit 9 - Stop generation"] #[inline(always)] #[must_use] pub fn stop(&mut self) -> STOP_W<9> { STOP_W::new(self) } #[doc = "Bit 10 - Acknowledge enable"] #[inline(always)] #[must_use] pub fn ack(&mut self) -> ACK_W<10> { ACK_W::new(self) } #[doc = "Bit 11 - Acknowledge/PEC Position (for data reception)"] #[inline(always)] #[must_use] pub fn pos(&mut self) -> POS_W<11> { POS_W::new(self) } #[doc = "Bit 12 - Packet error checking"] #[inline(always)] #[must_use] pub fn pec(&mut self) -> PEC_W<12> { PEC_W::new(self) } #[doc = "Bit 15 - Software reset"] #[inline(always)] #[must_use] pub fn swrst(&mut self) -> SWRST_W<15> { SWRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"] pub struct CR1_SPEC; impl crate::RegisterSpec for CR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr1::R](R) reader structure"] impl crate::Readable for CR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"] impl crate::Writable for CR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR1 to value 0"] impl crate::Resettable for CR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR2 (rw) register accessor: an alias for `Reg`"] pub type CR2 = crate::Reg; #[doc = "Control register 2"] pub mod cr2 { #[doc = "Register `CR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `FREQ` reader - Peripheral clock frequency"] pub type FREQ_R = crate::FieldReader; #[doc = "Field `FREQ` writer - Peripheral clock frequency"] pub type FREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CR2_SPEC, 6, O>; #[doc = "Field `ITERREN` reader - Error interrupt enable"] pub type ITERREN_R = crate::BitReader; #[doc = "Field `ITERREN` writer - Error interrupt enable"] pub type ITERREN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `ITEVTEN` reader - Event interrupt enable"] pub type ITEVTEN_R = crate::BitReader; #[doc = "Field `ITEVTEN` writer - Event interrupt enable"] pub type ITEVTEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `ITBUFEN` reader - Buffer interrupt enable"] pub type ITBUFEN_R = crate::BitReader; #[doc = "Field `ITBUFEN` writer - Buffer interrupt enable"] pub type ITBUFEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `DMAEN` reader - DMA requests enable"] pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - DMA requests enable"] pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; #[doc = "Field `LAST` reader - DMA last transfer"] pub type LAST_R = crate::BitReader; #[doc = "Field `LAST` writer - DMA last transfer"] pub type LAST_W<'a, const O: u8> = crate::BitWriter<'a, CR2_SPEC, O>; impl R { #[doc = "Bits 0:5 - Peripheral clock frequency"] #[inline(always)] pub fn freq(&self) -> FREQ_R { FREQ_R::new((self.bits & 0x3f) as u8) } #[doc = "Bit 8 - Error interrupt enable"] #[inline(always)] pub fn iterren(&self) -> ITERREN_R { ITERREN_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Event interrupt enable"] #[inline(always)] pub fn itevten(&self) -> ITEVTEN_R { ITEVTEN_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Buffer interrupt enable"] #[inline(always)] pub fn itbufen(&self) -> ITBUFEN_R { ITBUFEN_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - DMA requests enable"] #[inline(always)] pub fn dmaen(&self) -> DMAEN_R { DMAEN_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - DMA last transfer"] #[inline(always)] pub fn last(&self) -> LAST_R { LAST_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bits 0:5 - Peripheral clock frequency"] #[inline(always)] #[must_use] pub fn freq(&mut self) -> FREQ_W<0> { FREQ_W::new(self) } #[doc = "Bit 8 - Error interrupt enable"] #[inline(always)] #[must_use] pub fn iterren(&mut self) -> ITERREN_W<8> { ITERREN_W::new(self) } #[doc = "Bit 9 - Event interrupt enable"] #[inline(always)] #[must_use] pub fn itevten(&mut self) -> ITEVTEN_W<9> { ITEVTEN_W::new(self) } #[doc = "Bit 10 - Buffer interrupt enable"] #[inline(always)] #[must_use] pub fn itbufen(&mut self) -> ITBUFEN_W<10> { ITBUFEN_W::new(self) } #[doc = "Bit 11 - DMA requests enable"] #[inline(always)] #[must_use] pub fn dmaen(&mut self) -> DMAEN_W<11> { DMAEN_W::new(self) } #[doc = "Bit 12 - DMA last transfer"] #[inline(always)] #[must_use] pub fn last(&mut self) -> LAST_W<12> { LAST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"] pub struct CR2_SPEC; impl crate::RegisterSpec for CR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr2::R](R) reader structure"] impl crate::Readable for CR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"] impl crate::Writable for CR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR2 to value 0"] impl crate::Resettable for CR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "OAR1 (rw) register accessor: an alias for `Reg`"] pub type OAR1 = crate::Reg; #[doc = "Own address register 1"] pub mod oar1 { #[doc = "Register `OAR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OAR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ADD` reader - Interface address"] pub type ADD_R = crate::FieldReader; #[doc = "Field `ADD` writer - Interface address"] pub type ADD_W<'a, const O: u8> = crate::FieldWriter<'a, OAR1_SPEC, 7, O>; impl R { #[doc = "Bits 1:7 - Interface address"] #[inline(always)] pub fn add(&self) -> ADD_R { ADD_R::new(((self.bits >> 1) & 0x7f) as u8) } } impl W { #[doc = "Bits 1:7 - Interface address"] #[inline(always)] #[must_use] pub fn add(&mut self) -> ADD_W<1> { ADD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Own address register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oar1](index.html) module"] pub struct OAR1_SPEC; impl crate::RegisterSpec for OAR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [oar1::R](R) reader structure"] impl crate::Readable for OAR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [oar1::W](W) writer structure"] impl crate::Writable for OAR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets OAR1 to value 0"] impl crate::Resettable for OAR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DR (rw) register accessor: an alias for `Reg`"] pub type DR = crate::Reg; #[doc = "Data register"] pub mod dr { #[doc = "Register `DR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DR` reader - 8-bit data register"] pub type DR_R = crate::FieldReader; #[doc = "Field `DR` writer - 8-bit data register"] pub type DR_W<'a, const O: u8> = crate::FieldWriter<'a, DR_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - 8-bit data register"] #[inline(always)] pub fn dr(&self) -> DR_R { DR_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - 8-bit data register"] #[inline(always)] #[must_use] pub fn dr(&mut self) -> DR_W<0> { DR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr::R](R) reader structure"] impl crate::Readable for DR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] impl crate::Writable for DR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR to value 0"] impl crate::Resettable for DR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR1 (rw) register accessor: an alias for `Reg`"] pub type SR1 = crate::Reg; #[doc = "Status register 1"] pub mod sr1 { #[doc = "Register `SR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `SR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `SB` reader - Start bit (Master mode)"] pub type SB_R = crate::BitReader; #[doc = "Field `ADDR` reader - Address sent (master mode)/matched (slave mode)"] pub type ADDR_R = crate::BitReader; #[doc = "Field `BTF` reader - Byte transfer finished"] pub type BTF_R = crate::BitReader; #[doc = "Field `STOPF` reader - Stop detection (slave mode)"] pub type STOPF_R = crate::BitReader; #[doc = "Field `RxNE` reader - Data register not empty (receivers)"] pub type RX_NE_R = crate::BitReader; #[doc = "Field `TxE` reader - Data register empty (transmitters)"] pub type TX_E_R = crate::BitReader; #[doc = "Field `BERR` reader - Bus error"] pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Bus error"] pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, SR1_SPEC, O>; #[doc = "Field `ARLO` reader - Arbitration lost (master mode)"] pub type ARLO_R = crate::BitReader; #[doc = "Field `ARLO` writer - Arbitration lost (master mode)"] pub type ARLO_W<'a, const O: u8> = crate::BitWriter<'a, SR1_SPEC, O>; #[doc = "Field `AF` reader - Acknowledge failure"] pub type AF_R = crate::BitReader; #[doc = "Field `AF` writer - Acknowledge failure"] pub type AF_W<'a, const O: u8> = crate::BitWriter<'a, SR1_SPEC, O>; #[doc = "Field `OVR` reader - Overrun/Underrun"] pub type OVR_R = crate::BitReader; #[doc = "Field `OVR` writer - Overrun/Underrun"] pub type OVR_W<'a, const O: u8> = crate::BitWriter<'a, SR1_SPEC, O>; #[doc = "Field `PECERR` reader - PEC Error in reception"] pub type PECERR_R = crate::BitReader; #[doc = "Field `PECERR` writer - PEC Error in reception"] pub type PECERR_W<'a, const O: u8> = crate::BitWriter<'a, SR1_SPEC, O>; impl R { #[doc = "Bit 0 - Start bit (Master mode)"] #[inline(always)] pub fn sb(&self) -> SB_R { SB_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Address sent (master mode)/matched (slave mode)"] #[inline(always)] pub fn addr(&self) -> ADDR_R { ADDR_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Byte transfer finished"] #[inline(always)] pub fn btf(&self) -> BTF_R { BTF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 4 - Stop detection (slave mode)"] #[inline(always)] pub fn stopf(&self) -> STOPF_R { STOPF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 6 - Data register not empty (receivers)"] #[inline(always)] pub fn rx_ne(&self) -> RX_NE_R { RX_NE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Data register empty (transmitters)"] #[inline(always)] pub fn tx_e(&self) -> TX_E_R { TX_E_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Bus error"] #[inline(always)] pub fn berr(&self) -> BERR_R { BERR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Arbitration lost (master mode)"] #[inline(always)] pub fn arlo(&self) -> ARLO_R { ARLO_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Acknowledge failure"] #[inline(always)] pub fn af(&self) -> AF_R { AF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Overrun/Underrun"] #[inline(always)] pub fn ovr(&self) -> OVR_R { OVR_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - PEC Error in reception"] #[inline(always)] pub fn pecerr(&self) -> PECERR_R { PECERR_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 8 - Bus error"] #[inline(always)] #[must_use] pub fn berr(&mut self) -> BERR_W<8> { BERR_W::new(self) } #[doc = "Bit 9 - Arbitration lost (master mode)"] #[inline(always)] #[must_use] pub fn arlo(&mut self) -> ARLO_W<9> { ARLO_W::new(self) } #[doc = "Bit 10 - Acknowledge failure"] #[inline(always)] #[must_use] pub fn af(&mut self) -> AF_W<10> { AF_W::new(self) } #[doc = "Bit 11 - Overrun/Underrun"] #[inline(always)] #[must_use] pub fn ovr(&mut self) -> OVR_W<11> { OVR_W::new(self) } #[doc = "Bit 12 - PEC Error in reception"] #[inline(always)] #[must_use] pub fn pecerr(&mut self) -> PECERR_W<12> { PECERR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Status register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr1](index.html) module"] pub struct SR1_SPEC; impl crate::RegisterSpec for SR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr1::R](R) reader structure"] impl crate::Readable for SR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [sr1::W](W) writer structure"] impl crate::Writable for SR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets SR1 to value 0"] impl crate::Resettable for SR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "SR2 (r) register accessor: an alias for `Reg`"] pub type SR2 = crate::Reg; #[doc = "Status register 2"] pub mod sr2 { #[doc = "Register `SR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Field `MSL` reader - Master/slave"] pub type MSL_R = crate::BitReader; #[doc = "Field `BUSY` reader - Bus busy"] pub type BUSY_R = crate::BitReader; #[doc = "Field `TRA` reader - Transmitter/receiver"] pub type TRA_R = crate::BitReader; #[doc = "Field `GENCALL` reader - General call address (Slave mode)"] pub type GENCALL_R = crate::BitReader; #[doc = "Field `DUALF` reader - Dual flag (Slave mode)"] pub type DUALF_R = crate::BitReader; #[doc = "Field `PEC` reader - acket error checking register"] pub type PEC_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Master/slave"] #[inline(always)] pub fn msl(&self) -> MSL_R { MSL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Bus busy"] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Transmitter/receiver"] #[inline(always)] pub fn tra(&self) -> TRA_R { TRA_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 4 - General call address (Slave mode)"] #[inline(always)] pub fn gencall(&self) -> GENCALL_R { GENCALL_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 7 - Dual flag (Slave mode)"] #[inline(always)] pub fn dualf(&self) -> DUALF_R { DUALF_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:15 - acket error checking register"] #[inline(always)] pub fn pec(&self) -> PEC_R { PEC_R::new(((self.bits >> 8) & 0xff) as u8) } } #[doc = "Status register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr2](index.html) module"] pub struct SR2_SPEC; impl crate::RegisterSpec for SR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [sr2::R](R) reader structure"] impl crate::Readable for SR2_SPEC { type Reader = R; } #[doc = "`reset()` method sets SR2 to value 0"] impl crate::Resettable for SR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CCR (rw) register accessor: an alias for `Reg`"] pub type CCR = crate::Reg; #[doc = "Clock control register"] pub mod ccr { #[doc = "Register `CCR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CCR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `CCR` reader - Clock control register in Fast/Standard mode (Master mode)"] pub type CCR_R = crate::FieldReader; #[doc = "Field `CCR` writer - Clock control register in Fast/Standard mode (Master mode)"] pub type CCR_W<'a, const O: u8> = crate::FieldWriter<'a, CCR_SPEC, 12, O, u16>; #[doc = "Field `DUTY` reader - Fast mode duty cycle"] pub type DUTY_R = crate::BitReader; #[doc = "Field `DUTY` writer - Fast mode duty cycle"] pub type DUTY_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; #[doc = "Field `F_S` reader - I2C master mode selection"] pub type F_S_R = crate::BitReader; #[doc = "Field `F_S` writer - I2C master mode selection"] pub type F_S_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; impl R { #[doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"] #[inline(always)] pub fn ccr(&self) -> CCR_R { CCR_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 14 - Fast mode duty cycle"] #[inline(always)] pub fn duty(&self) -> DUTY_R { DUTY_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - I2C master mode selection"] #[inline(always)] pub fn f_s(&self) -> F_S_R { F_S_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"] #[inline(always)] #[must_use] pub fn ccr(&mut self) -> CCR_W<0> { CCR_W::new(self) } #[doc = "Bit 14 - Fast mode duty cycle"] #[inline(always)] #[must_use] pub fn duty(&mut self) -> DUTY_W<14> { DUTY_W::new(self) } #[doc = "Bit 15 - I2C master mode selection"] #[inline(always)] #[must_use] pub fn f_s(&mut self) -> F_S_W<15> { F_S_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Clock control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] pub struct CCR_SPEC; impl crate::RegisterSpec for CCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ccr::R](R) reader structure"] impl crate::Readable for CCR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ccr::W](W) writer structure"] impl crate::Writable for CCR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CCR to value 0"] impl crate::Resettable for CCR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "TRISE (rw) register accessor: an alias for `Reg`"] pub type TRISE = crate::Reg; #[doc = "TRISE register"] pub mod trise { #[doc = "Register `TRISE` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TRISE` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `TRISE` reader - Maximum rise time in Fast/Standard mode (Master mode)"] pub type TRISE_R = crate::FieldReader; #[doc = "Field `TRISE` writer - Maximum rise time in Fast/Standard mode (Master mode)"] pub type TRISE_W<'a, const O: u8> = crate::FieldWriter<'a, TRISE_SPEC, 6, O>; impl R { #[doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"] #[inline(always)] pub fn trise(&self) -> TRISE_R { TRISE_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"] #[inline(always)] #[must_use] pub fn trise(&mut self) -> TRISE_W<0> { TRISE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "TRISE register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trise](index.html) module"] pub struct TRISE_SPEC; impl crate::RegisterSpec for TRISE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [trise::R](R) reader structure"] impl crate::Readable for TRISE_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [trise::W](W) writer structure"] impl crate::Writable for TRISE_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TRISE to value 0x02"] impl crate::Resettable for TRISE_SPEC { const RESET_VALUE: Self::Ux = 0x02; } } } #[doc = "LED CONTROLLER"] pub struct LED { _marker: PhantomData<*const ()>, } unsafe impl Send for LED {} impl LED { #[doc = r"Pointer to the register block"] pub const PTR: *const led::RegisterBlock = 0x4000_2400 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const led::RegisterBlock { Self::PTR } } impl Deref for LED { type Target = led::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for LED { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("LED").finish() } } #[doc = "LED CONTROLLER"] pub mod led { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - Control register"] pub cr: CR, #[doc = "0x04 - Prescaler register"] pub pr: PR, #[doc = "0x08 - Time register"] pub tr: TR, #[doc = "0x0c - Data0 register"] pub dr0: DR0, #[doc = "0x10 - Data1 register"] pub dr1: DR1, #[doc = "0x14 - Data2 register"] pub dr2: DR2, #[doc = "0x18 - Data3 register"] pub dr3: DR3, #[doc = "0x1c - Interrupt register 1"] pub ir: IR, } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Control register"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `LEDON` reader - LED enable"] pub type LEDON_R = crate::BitReader; #[doc = "Field `LEDON` writer - LED enable"] pub type LEDON_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `LED_COM_SEL` reader - LED COM Selection"] pub type LED_COM_SEL_R = crate::FieldReader; #[doc = "Field `LED_COM_SEL` writer - LED COM Selection"] pub type LED_COM_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 2, O>; #[doc = "Field `IE` reader - LED interrupt enable"] pub type IE_R = crate::BitReader; #[doc = "Field `IE` writer - LED interrupt enable"] pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; #[doc = "Field `EHS` reader - Light control"] pub type EHS_R = crate::FieldReader; #[doc = "Field `EHS` writer - Light control"] pub type EHS_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 2, O>; impl R { #[doc = "Bit 0 - LED enable"] #[inline(always)] pub fn ledon(&self) -> LEDON_R { LEDON_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:2 - LED COM Selection"] #[inline(always)] pub fn led_com_sel(&self) -> LED_COM_SEL_R { LED_COM_SEL_R::new(((self.bits >> 1) & 3) as u8) } #[doc = "Bit 3 - LED interrupt enable"] #[inline(always)] pub fn ie(&self) -> IE_R { IE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 12:13 - Light control"] #[inline(always)] pub fn ehs(&self) -> EHS_R { EHS_R::new(((self.bits >> 12) & 3) as u8) } } impl W { #[doc = "Bit 0 - LED enable"] #[inline(always)] #[must_use] pub fn ledon(&mut self) -> LEDON_W<0> { LEDON_W::new(self) } #[doc = "Bits 1:2 - LED COM Selection"] #[inline(always)] #[must_use] pub fn led_com_sel(&mut self) -> LED_COM_SEL_W<1> { LED_COM_SEL_W::new(self) } #[doc = "Bit 3 - LED interrupt enable"] #[inline(always)] #[must_use] pub fn ie(&mut self) -> IE_W<3> { IE_W::new(self) } #[doc = "Bits 12:13 - Light control"] #[inline(always)] #[must_use] pub fn ehs(&mut self) -> EHS_W<12> { EHS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "PR (rw) register accessor: an alias for `Reg`"] pub type PR = crate::Reg; #[doc = "Prescaler register"] pub mod pr { #[doc = "Register `PR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `PR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `PR` reader - Prescaler control"] pub type PR_R = crate::FieldReader; #[doc = "Field `PR` writer - Prescaler control"] pub type PR_W<'a, const O: u8> = crate::FieldWriter<'a, PR_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - Prescaler control"] #[inline(always)] pub fn pr(&self) -> PR_R { PR_R::new((self.bits & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - Prescaler control"] #[inline(always)] #[must_use] pub fn pr(&mut self) -> PR_W<0> { PR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Prescaler register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](index.html) module"] pub struct PR_SPEC; impl crate::RegisterSpec for PR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pr::R](R) reader structure"] impl crate::Readable for PR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pr::W](W) writer structure"] impl crate::Writable for PR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets PR to value 0"] impl crate::Resettable for PR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "TR (rw) register accessor: an alias for `Reg`"] pub type TR = crate::Reg; #[doc = "Time register"] pub mod tr { #[doc = "Register `TR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `TR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `T1` reader - Light on time"] pub type T1_R = crate::FieldReader; #[doc = "Field `T1` writer - Light on time"] pub type T1_W<'a, const O: u8> = crate::FieldWriter<'a, TR_SPEC, 8, O>; #[doc = "Field `T2` reader - Switch time"] pub type T2_R = crate::FieldReader; #[doc = "Field `T2` writer - Switch time"] pub type T2_W<'a, const O: u8> = crate::FieldWriter<'a, TR_SPEC, 8, O>; impl R { #[doc = "Bits 0:7 - Light on time"] #[inline(always)] pub fn t1(&self) -> T1_R { T1_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - Switch time"] #[inline(always)] pub fn t2(&self) -> T2_R { T2_R::new(((self.bits >> 8) & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - Light on time"] #[inline(always)] #[must_use] pub fn t1(&mut self) -> T1_W<0> { T1_W::new(self) } #[doc = "Bits 8:15 - Switch time"] #[inline(always)] #[must_use] pub fn t2(&mut self) -> T2_W<8> { T2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tr](index.html) module"] pub struct TR_SPEC; impl crate::RegisterSpec for TR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [tr::R](R) reader structure"] impl crate::Readable for TR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [tr::W](W) writer structure"] impl crate::Writable for TR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets TR to value 0"] impl crate::Resettable for TR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DR0 (rw) register accessor: an alias for `Reg`"] pub type DR0 = crate::Reg; #[doc = "Data0 register"] pub mod dr0 { #[doc = "Register `DR0` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR0` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DATA0_A` reader - 8-bit data register"] pub type DATA0_A_R = crate::BitReader; #[doc = "Field `DATA0_A` writer - 8-bit data register"] pub type DATA0_A_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_B` reader - 8-bit data register"] pub type DATA0_B_R = crate::BitReader; #[doc = "Field `DATA0_B` writer - 8-bit data register"] pub type DATA0_B_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_C` reader - 8-bit data register"] pub type DATA0_C_R = crate::BitReader; #[doc = "Field `DATA0_C` writer - 8-bit data register"] pub type DATA0_C_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_D` reader - 8-bit data register"] pub type DATA0_D_R = crate::BitReader; #[doc = "Field `DATA0_D` writer - 8-bit data register"] pub type DATA0_D_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_E` reader - 8-bit data register"] pub type DATA0_E_R = crate::BitReader; #[doc = "Field `DATA0_E` writer - 8-bit data register"] pub type DATA0_E_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_F` reader - 8-bit data register"] pub type DATA0_F_R = crate::BitReader; #[doc = "Field `DATA0_F` writer - 8-bit data register"] pub type DATA0_F_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_G` reader - 8-bit data register"] pub type DATA0_G_R = crate::BitReader; #[doc = "Field `DATA0_G` writer - 8-bit data register"] pub type DATA0_G_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; #[doc = "Field `DATA0_DP` reader - 8-bit data register"] pub type DATA0_DP_R = crate::BitReader; #[doc = "Field `DATA0_DP` writer - 8-bit data register"] pub type DATA0_DP_W<'a, const O: u8> = crate::BitWriter<'a, DR0_SPEC, O>; impl R { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] pub fn data0_a(&self) -> DATA0_A_R { DATA0_A_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] pub fn data0_b(&self) -> DATA0_B_R { DATA0_B_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] pub fn data0_c(&self) -> DATA0_C_R { DATA0_C_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] pub fn data0_d(&self) -> DATA0_D_R { DATA0_D_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] pub fn data0_e(&self) -> DATA0_E_R { DATA0_E_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] pub fn data0_f(&self) -> DATA0_F_R { DATA0_F_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] pub fn data0_g(&self) -> DATA0_G_R { DATA0_G_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] pub fn data0_dp(&self) -> DATA0_DP_R { DATA0_DP_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_a(&mut self) -> DATA0_A_W<0> { DATA0_A_W::new(self) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_b(&mut self) -> DATA0_B_W<1> { DATA0_B_W::new(self) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_c(&mut self) -> DATA0_C_W<2> { DATA0_C_W::new(self) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_d(&mut self) -> DATA0_D_W<3> { DATA0_D_W::new(self) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_e(&mut self) -> DATA0_E_W<4> { DATA0_E_W::new(self) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_f(&mut self) -> DATA0_F_W<5> { DATA0_F_W::new(self) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_g(&mut self) -> DATA0_G_W<6> { DATA0_G_W::new(self) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data0_dp(&mut self) -> DATA0_DP_W<7> { DATA0_DP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data0 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr0](index.html) module"] pub struct DR0_SPEC; impl crate::RegisterSpec for DR0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr0::R](R) reader structure"] impl crate::Readable for DR0_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr0::W](W) writer structure"] impl crate::Writable for DR0_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR0 to value 0"] impl crate::Resettable for DR0_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DR1 (rw) register accessor: an alias for `Reg`"] pub type DR1 = crate::Reg; #[doc = "Data1 register"] pub mod dr1 { #[doc = "Register `DR1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DATA1_A` reader - 8-bit data register"] pub type DATA1_A_R = crate::BitReader; #[doc = "Field `DATA1_A` writer - 8-bit data register"] pub type DATA1_A_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_B` reader - 8-bit data register"] pub type DATA1_B_R = crate::BitReader; #[doc = "Field `DATA1_B` writer - 8-bit data register"] pub type DATA1_B_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_C` reader - 8-bit data register"] pub type DATA1_C_R = crate::BitReader; #[doc = "Field `DATA1_C` writer - 8-bit data register"] pub type DATA1_C_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_D` reader - 8-bit data register"] pub type DATA1_D_R = crate::BitReader; #[doc = "Field `DATA1_D` writer - 8-bit data register"] pub type DATA1_D_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_E` reader - 8-bit data register"] pub type DATA1_E_R = crate::BitReader; #[doc = "Field `DATA1_E` writer - 8-bit data register"] pub type DATA1_E_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_F` reader - 8-bit data register"] pub type DATA1_F_R = crate::BitReader; #[doc = "Field `DATA1_F` writer - 8-bit data register"] pub type DATA1_F_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_G` reader - 8-bit data register"] pub type DATA1_G_R = crate::BitReader; #[doc = "Field `DATA1_G` writer - 8-bit data register"] pub type DATA1_G_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; #[doc = "Field `DATA1_DP` reader - 8-bit data register"] pub type DATA1_DP_R = crate::BitReader; #[doc = "Field `DATA1_DP` writer - 8-bit data register"] pub type DATA1_DP_W<'a, const O: u8> = crate::BitWriter<'a, DR1_SPEC, O>; impl R { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] pub fn data1_a(&self) -> DATA1_A_R { DATA1_A_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] pub fn data1_b(&self) -> DATA1_B_R { DATA1_B_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] pub fn data1_c(&self) -> DATA1_C_R { DATA1_C_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] pub fn data1_d(&self) -> DATA1_D_R { DATA1_D_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] pub fn data1_e(&self) -> DATA1_E_R { DATA1_E_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] pub fn data1_f(&self) -> DATA1_F_R { DATA1_F_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] pub fn data1_g(&self) -> DATA1_G_R { DATA1_G_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] pub fn data1_dp(&self) -> DATA1_DP_R { DATA1_DP_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_a(&mut self) -> DATA1_A_W<0> { DATA1_A_W::new(self) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_b(&mut self) -> DATA1_B_W<1> { DATA1_B_W::new(self) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_c(&mut self) -> DATA1_C_W<2> { DATA1_C_W::new(self) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_d(&mut self) -> DATA1_D_W<3> { DATA1_D_W::new(self) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_e(&mut self) -> DATA1_E_W<4> { DATA1_E_W::new(self) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_f(&mut self) -> DATA1_F_W<5> { DATA1_F_W::new(self) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_g(&mut self) -> DATA1_G_W<6> { DATA1_G_W::new(self) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data1_dp(&mut self) -> DATA1_DP_W<7> { DATA1_DP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr1](index.html) module"] pub struct DR1_SPEC; impl crate::RegisterSpec for DR1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr1::R](R) reader structure"] impl crate::Readable for DR1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr1::W](W) writer structure"] impl crate::Writable for DR1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR1 to value 0"] impl crate::Resettable for DR1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DR2 (rw) register accessor: an alias for `Reg`"] pub type DR2 = crate::Reg; #[doc = "Data2 register"] pub mod dr2 { #[doc = "Register `DR2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DATA2_A` reader - 8-bit data register"] pub type DATA2_A_R = crate::BitReader; #[doc = "Field `DATA2_A` writer - 8-bit data register"] pub type DATA2_A_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_B` reader - 8-bit data register"] pub type DATA2_B_R = crate::BitReader; #[doc = "Field `DATA2_B` writer - 8-bit data register"] pub type DATA2_B_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_C` reader - 8-bit data register"] pub type DATA2_C_R = crate::BitReader; #[doc = "Field `DATA2_C` writer - 8-bit data register"] pub type DATA2_C_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_D` reader - 8-bit data register"] pub type DATA2_D_R = crate::BitReader; #[doc = "Field `DATA2_D` writer - 8-bit data register"] pub type DATA2_D_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_E` reader - 8-bit data register"] pub type DATA2_E_R = crate::BitReader; #[doc = "Field `DATA2_E` writer - 8-bit data register"] pub type DATA2_E_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_F` reader - 8-bit data register"] pub type DATA2_F_R = crate::BitReader; #[doc = "Field `DATA2_F` writer - 8-bit data register"] pub type DATA2_F_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_G` reader - 8-bit data register"] pub type DATA2_G_R = crate::BitReader; #[doc = "Field `DATA2_G` writer - 8-bit data register"] pub type DATA2_G_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; #[doc = "Field `DATA2_DP` reader - 8-bit data register"] pub type DATA2_DP_R = crate::BitReader; #[doc = "Field `DATA2_DP` writer - 8-bit data register"] pub type DATA2_DP_W<'a, const O: u8> = crate::BitWriter<'a, DR2_SPEC, O>; impl R { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] pub fn data2_a(&self) -> DATA2_A_R { DATA2_A_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] pub fn data2_b(&self) -> DATA2_B_R { DATA2_B_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] pub fn data2_c(&self) -> DATA2_C_R { DATA2_C_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] pub fn data2_d(&self) -> DATA2_D_R { DATA2_D_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] pub fn data2_e(&self) -> DATA2_E_R { DATA2_E_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] pub fn data2_f(&self) -> DATA2_F_R { DATA2_F_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] pub fn data2_g(&self) -> DATA2_G_R { DATA2_G_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] pub fn data2_dp(&self) -> DATA2_DP_R { DATA2_DP_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_a(&mut self) -> DATA2_A_W<0> { DATA2_A_W::new(self) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_b(&mut self) -> DATA2_B_W<1> { DATA2_B_W::new(self) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_c(&mut self) -> DATA2_C_W<2> { DATA2_C_W::new(self) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_d(&mut self) -> DATA2_D_W<3> { DATA2_D_W::new(self) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_e(&mut self) -> DATA2_E_W<4> { DATA2_E_W::new(self) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_f(&mut self) -> DATA2_F_W<5> { DATA2_F_W::new(self) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_g(&mut self) -> DATA2_G_W<6> { DATA2_G_W::new(self) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data2_dp(&mut self) -> DATA2_DP_W<7> { DATA2_DP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data2 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr2](index.html) module"] pub struct DR2_SPEC; impl crate::RegisterSpec for DR2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr2::R](R) reader structure"] impl crate::Readable for DR2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr2::W](W) writer structure"] impl crate::Writable for DR2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR2 to value 0"] impl crate::Resettable for DR2_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "DR3 (rw) register accessor: an alias for `Reg`"] pub type DR3 = crate::Reg; #[doc = "Data3 register"] pub mod dr3 { #[doc = "Register `DR3` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `DR3` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DATA3_A` reader - 8-bit data register"] pub type DATA3_A_R = crate::BitReader; #[doc = "Field `DATA3_A` writer - 8-bit data register"] pub type DATA3_A_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_B` reader - 8-bit data register"] pub type DATA3_B_R = crate::BitReader; #[doc = "Field `DATA3_B` writer - 8-bit data register"] pub type DATA3_B_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_C` reader - 8-bit data register"] pub type DATA3_C_R = crate::BitReader; #[doc = "Field `DATA3_C` writer - 8-bit data register"] pub type DATA3_C_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_D` reader - 8-bit data register"] pub type DATA3_D_R = crate::BitReader; #[doc = "Field `DATA3_D` writer - 8-bit data register"] pub type DATA3_D_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_E` reader - 8-bit data register"] pub type DATA3_E_R = crate::BitReader; #[doc = "Field `DATA3_E` writer - 8-bit data register"] pub type DATA3_E_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_F` reader - 8-bit data register"] pub type DATA3_F_R = crate::BitReader; #[doc = "Field `DATA3_F` writer - 8-bit data register"] pub type DATA3_F_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_G` reader - 8-bit data register"] pub type DATA3_G_R = crate::BitReader; #[doc = "Field `DATA3_G` writer - 8-bit data register"] pub type DATA3_G_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; #[doc = "Field `DATA3_DP` reader - 8-bit data register"] pub type DATA3_DP_R = crate::BitReader; #[doc = "Field `DATA3_DP` writer - 8-bit data register"] pub type DATA3_DP_W<'a, const O: u8> = crate::BitWriter<'a, DR3_SPEC, O>; impl R { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] pub fn data3_a(&self) -> DATA3_A_R { DATA3_A_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] pub fn data3_b(&self) -> DATA3_B_R { DATA3_B_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] pub fn data3_c(&self) -> DATA3_C_R { DATA3_C_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] pub fn data3_d(&self) -> DATA3_D_R { DATA3_D_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] pub fn data3_e(&self) -> DATA3_E_R { DATA3_E_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] pub fn data3_f(&self) -> DATA3_F_R { DATA3_F_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] pub fn data3_g(&self) -> DATA3_G_R { DATA3_G_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] pub fn data3_dp(&self) -> DATA3_DP_R { DATA3_DP_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 0 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_a(&mut self) -> DATA3_A_W<0> { DATA3_A_W::new(self) } #[doc = "Bit 1 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_b(&mut self) -> DATA3_B_W<1> { DATA3_B_W::new(self) } #[doc = "Bit 2 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_c(&mut self) -> DATA3_C_W<2> { DATA3_C_W::new(self) } #[doc = "Bit 3 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_d(&mut self) -> DATA3_D_W<3> { DATA3_D_W::new(self) } #[doc = "Bit 4 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_e(&mut self) -> DATA3_E_W<4> { DATA3_E_W::new(self) } #[doc = "Bit 5 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_f(&mut self) -> DATA3_F_W<5> { DATA3_F_W::new(self) } #[doc = "Bit 6 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_g(&mut self) -> DATA3_G_W<6> { DATA3_G_W::new(self) } #[doc = "Bit 7 - 8-bit data register"] #[inline(always)] #[must_use] pub fn data3_dp(&mut self) -> DATA3_DP_W<7> { DATA3_DP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Data3 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr3](index.html) module"] pub struct DR3_SPEC; impl crate::RegisterSpec for DR3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dr3::R](R) reader structure"] impl crate::Readable for DR3_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dr3::W](W) writer structure"] impl crate::Writable for DR3_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets DR3 to value 0"] impl crate::Resettable for DR3_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "IR (rw) register accessor: an alias for `Reg`"] pub type IR = crate::Reg; #[doc = "Interrupt register 1"] pub mod ir { #[doc = "Register `IR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `IR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `FLAG` reader - interrupt flag"] pub type FLAG_R = crate::BitReader; #[doc = "Field `FLAG` writer - interrupt flag"] pub type FLAG_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; impl R { #[doc = "Bit 0 - interrupt flag"] #[inline(always)] pub fn flag(&self) -> FLAG_R { FLAG_R::new((self.bits & 1) != 0) } } impl W { #[doc = "Bit 0 - interrupt flag"] #[inline(always)] #[must_use] pub fn flag(&mut self) -> FLAG_W<0> { FLAG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Interrupt register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"] pub struct IR_SPEC; impl crate::RegisterSpec for IR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [ir::R](R) reader structure"] impl crate::Readable for IR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [ir::W](W) writer structure"] impl crate::Writable for IR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets IR to value 0"] impl crate::Resettable for IR_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[doc = "Debug support"] pub struct DBGMCU { _marker: PhantomData<*const ()>, } unsafe impl Send for DBGMCU {} impl DBGMCU { #[doc = r"Pointer to the register block"] pub const PTR: *const dbgmcu::RegisterBlock = 0x4001_5800 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const dbgmcu::RegisterBlock { Self::PTR } } impl Deref for DBGMCU { type Target = dbgmcu::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } impl core::fmt::Debug for DBGMCU { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DBGMCU").finish() } } #[doc = "Debug support"] pub mod dbgmcu { #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - MCU Device ID Code Register"] pub idcode: IDCODE, #[doc = "0x04 - Debug MCU Configuration Register"] pub cr: CR, #[doc = "0x08 - APB Freeze Register1"] pub apb_fz1: APB_FZ1, #[doc = "0x0c - APB Freeze Register2"] pub apb_fz2: APB_FZ2, } #[doc = "IDCODE (r) register accessor: an alias for `Reg`"] pub type IDCODE = crate::Reg; #[doc = "MCU Device ID Code Register"] pub mod idcode { #[doc = "Register `IDCODE` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "MCU Device ID Code Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idcode](index.html) module"] pub struct IDCODE_SPEC; impl crate::RegisterSpec for IDCODE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [idcode::R](R) reader structure"] impl crate::Readable for IDCODE_SPEC { type Reader = R; } #[doc = "`reset()` method sets IDCODE to value 0"] impl crate::Resettable for IDCODE_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "CR (rw) register accessor: an alias for `Reg`"] pub type CR = crate::Reg; #[doc = "Debug MCU Configuration Register"] pub mod cr { #[doc = "Register `CR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `CR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DBG_STOP` reader - Debug Stop Mode"] pub type DBG_STOP_R = crate::BitReader; #[doc = "Field `DBG_STOP` writer - Debug Stop Mode"] pub type DBG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; impl R { #[doc = "Bit 1 - Debug Stop Mode"] #[inline(always)] pub fn dbg_stop(&self) -> DBG_STOP_R { DBG_STOP_R::new(((self.bits >> 1) & 1) != 0) } } impl W { #[doc = "Bit 1 - Debug Stop Mode"] #[inline(always)] #[must_use] pub fn dbg_stop(&mut self) -> DBG_STOP_W<1> { DBG_STOP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Debug MCU Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [cr::R](R) reader structure"] impl crate::Readable for CR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] impl crate::Writable for CR_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets CR to value 0"] impl crate::Resettable for CR_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "APB_FZ1 (rw) register accessor: an alias for `Reg`"] pub type APB_FZ1 = crate::Reg; #[doc = "APB Freeze Register1"] pub mod apb_fz1 { #[doc = "Register `APB_FZ1` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `APB_FZ1` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DBG_TIMER3_STOP` reader - Debug Timer 3 stopped when Core is halted"] pub type DBG_TIMER3_STOP_R = crate::BitReader; #[doc = "Field `DBG_TIMER3_STOP` writer - Debug Timer 3 stopped when Core is halted"] pub type DBG_TIMER3_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ1_SPEC, O>; #[doc = "Field `DBG_RTC_STOP` reader - Debug RTC stopped when Core is halted"] pub type DBG_RTC_STOP_R = crate::BitReader; #[doc = "Field `DBG_RTC_STOP` writer - Debug RTC stopped when Core is halted"] pub type DBG_RTC_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ1_SPEC, O>; #[doc = "Field `DBG_WWDG_STOP` reader - Debug Window Wachdog stopped when Core is halted"] pub type DBG_WWDG_STOP_R = crate::BitReader; #[doc = "Field `DBG_WWDG_STOP` writer - Debug Window Wachdog stopped when Core is halted"] pub type DBG_WWDG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ1_SPEC, O>; #[doc = "Field `DBG_IWDG_STOP` reader - Debug Independent Wachdog stopped when Core is halted"] pub type DBG_IWDG_STOP_R = crate::BitReader; #[doc = "Field `DBG_IWDG_STOP` writer - Debug Independent Wachdog stopped when Core is halted"] pub type DBG_IWDG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ1_SPEC, O>; #[doc = "Field `DBG_LPTIM_STOP` reader - Debug LPTIM stopped when Core is halted"] pub type DBG_LPTIM_STOP_R = crate::BitReader; #[doc = "Field `DBG_LPTIM_STOP` writer - Debug LPTIM stopped when Core is halted"] pub type DBG_LPTIM_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ1_SPEC, O>; impl R { #[doc = "Bit 1 - Debug Timer 3 stopped when Core is halted"] #[inline(always)] pub fn dbg_timer3_stop(&self) -> DBG_TIMER3_STOP_R { DBG_TIMER3_STOP_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 10 - Debug RTC stopped when Core is halted"] #[inline(always)] pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R { DBG_RTC_STOP_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted"] #[inline(always)] pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R { DBG_WWDG_STOP_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted"] #[inline(always)] pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R { DBG_IWDG_STOP_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 31 - Debug LPTIM stopped when Core is halted"] #[inline(always)] pub fn dbg_lptim_stop(&self) -> DBG_LPTIM_STOP_R { DBG_LPTIM_STOP_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 1 - Debug Timer 3 stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_timer3_stop(&mut self) -> DBG_TIMER3_STOP_W<1> { DBG_TIMER3_STOP_W::new(self) } #[doc = "Bit 10 - Debug RTC stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<10> { DBG_RTC_STOP_W::new(self) } #[doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<11> { DBG_WWDG_STOP_W::new(self) } #[doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<12> { DBG_IWDG_STOP_W::new(self) } #[doc = "Bit 31 - Debug LPTIM stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_lptim_stop(&mut self) -> DBG_LPTIM_STOP_W<31> { DBG_LPTIM_STOP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "APB Freeze Register1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb_fz1](index.html) module"] pub struct APB_FZ1_SPEC; impl crate::RegisterSpec for APB_FZ1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [apb_fz1::R](R) reader structure"] impl crate::Readable for APB_FZ1_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [apb_fz1::W](W) writer structure"] impl crate::Writable for APB_FZ1_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets APB_FZ1 to value 0"] impl crate::Resettable for APB_FZ1_SPEC { const RESET_VALUE: Self::Ux = 0; } } #[doc = "APB_FZ2 (rw) register accessor: an alias for `Reg`"] pub type APB_FZ2 = crate::Reg; #[doc = "APB Freeze Register2"] pub mod apb_fz2 { #[doc = "Register `APB_FZ2` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `APB_FZ2` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `DBG_TIMER1_STOP` reader - Debug Timer 1 stopped when Core is halted"] pub type DBG_TIMER1_STOP_R = crate::BitReader; #[doc = "Field `DBG_TIMER1_STOP` writer - Debug Timer 1 stopped when Core is halted"] pub type DBG_TIMER1_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ2_SPEC, O>; #[doc = "Field `DBG_TIMER14_STOP` reader - Debug Timer 14 stopped when Core is halted"] pub type DBG_TIMER14_STOP_R = crate::BitReader; #[doc = "Field `DBG_TIMER14_STOP` writer - Debug Timer 14 stopped when Core is halted"] pub type DBG_TIMER14_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ2_SPEC, O>; #[doc = "Field `DBG_TIMER16_STOP` reader - Debug Timer 16 stopped when Core is halted"] pub type DBG_TIMER16_STOP_R = crate::BitReader; #[doc = "Field `DBG_TIMER16_STOP` writer - Debug Timer 16 stopped when Core is halted"] pub type DBG_TIMER16_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ2_SPEC, O>; #[doc = "Field `DBG_TIMER17_STOP` reader - Debug Timer 17 stopped when Core is halted"] pub type DBG_TIMER17_STOP_R = crate::BitReader; #[doc = "Field `DBG_TIMER17_STOP` writer - Debug Timer 17 stopped when Core is halted"] pub type DBG_TIMER17_STOP_W<'a, const O: u8> = crate::BitWriter<'a, APB_FZ2_SPEC, O>; impl R { #[doc = "Bit 11 - Debug Timer 1 stopped when Core is halted"] #[inline(always)] pub fn dbg_timer1_stop(&self) -> DBG_TIMER1_STOP_R { DBG_TIMER1_STOP_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 15 - Debug Timer 14 stopped when Core is halted"] #[inline(always)] pub fn dbg_timer14_stop(&self) -> DBG_TIMER14_STOP_R { DBG_TIMER14_STOP_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 17 - Debug Timer 16 stopped when Core is halted"] #[inline(always)] pub fn dbg_timer16_stop(&self) -> DBG_TIMER16_STOP_R { DBG_TIMER16_STOP_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - Debug Timer 17 stopped when Core is halted"] #[inline(always)] pub fn dbg_timer17_stop(&self) -> DBG_TIMER17_STOP_R { DBG_TIMER17_STOP_R::new(((self.bits >> 18) & 1) != 0) } } impl W { #[doc = "Bit 11 - Debug Timer 1 stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_timer1_stop(&mut self) -> DBG_TIMER1_STOP_W<11> { DBG_TIMER1_STOP_W::new(self) } #[doc = "Bit 15 - Debug Timer 14 stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_timer14_stop(&mut self) -> DBG_TIMER14_STOP_W<15> { DBG_TIMER14_STOP_W::new(self) } #[doc = "Bit 17 - Debug Timer 16 stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_timer16_stop(&mut self) -> DBG_TIMER16_STOP_W<17> { DBG_TIMER16_STOP_W::new(self) } #[doc = "Bit 18 - Debug Timer 17 stopped when Core is halted"] #[inline(always)] #[must_use] pub fn dbg_timer17_stop(&mut self) -> DBG_TIMER17_STOP_W<18> { DBG_TIMER17_STOP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "APB Freeze Register2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb_fz2](index.html) module"] pub struct APB_FZ2_SPEC; impl crate::RegisterSpec for APB_FZ2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [apb_fz2::R](R) reader structure"] impl crate::Readable for APB_FZ2_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [apb_fz2::W](W) writer structure"] impl crate::Writable for APB_FZ2_SPEC { type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } #[doc = "`reset()` method sets APB_FZ2 to value 0"] impl crate::Resettable for APB_FZ2_SPEC { const RESET_VALUE: Self::Ux = 0; } } } #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] #[allow(non_snake_case)] pub struct Peripherals { #[doc = "ADC"] pub ADC: ADC, #[doc = "COMP1"] pub COMP1: COMP1, #[doc = "COMP2"] pub COMP2: COMP2, #[doc = "RCC"] pub RCC: RCC, #[doc = "PWR"] pub PWR: PWR, #[doc = "GPIOA"] pub GPIOA: GPIOA, #[doc = "GPIOB"] pub GPIOB: GPIOB, #[doc = "GPIOF"] pub GPIOF: GPIOF, #[doc = "EXTI"] pub EXTI: EXTI, #[doc = "LPTIM"] pub LPTIM: LPTIM, #[doc = "USART1"] pub USART1: USART1, #[doc = "USART2"] pub USART2: USART2, #[doc = "RTC"] pub RTC: RTC, #[doc = "IWDG"] pub IWDG: IWDG, #[doc = "WWDG"] pub WWDG: WWDG, #[doc = "TIM1"] pub TIM1: TIM1, #[doc = "TIM3"] pub TIM3: TIM3, #[doc = "TIM14"] pub TIM14: TIM14, #[doc = "TIM16"] pub TIM16: TIM16, #[doc = "TIM17"] pub TIM17: TIM17, #[doc = "SYSCFG"] pub SYSCFG: SYSCFG, #[doc = "DMA"] pub DMA: DMA, #[doc = "FLASH"] pub FLASH: FLASH, #[doc = "CRC"] pub CRC: CRC, #[doc = "SPI1"] pub SPI1: SPI1, #[doc = "SPI2"] pub SPI2: SPI2, #[doc = "I2C"] pub I2C: I2C, #[doc = "LED"] pub LED: LED, #[doc = "DBGMCU"] pub DBGMCU: DBGMCU, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] #[cfg(feature = "critical-section")] #[inline] pub fn take() -> Option { critical_section::with(|_| { if unsafe { DEVICE_PERIPHERALS } { return None; } Some(unsafe { Peripherals::steal() }) }) } #[doc = r" Unchecked version of `Peripherals::take`."] #[doc = r""] #[doc = r" # Safety"] #[doc = r""] #[doc = r" Each of the returned peripherals must be used at most once."] #[inline] pub unsafe fn steal() -> Self { DEVICE_PERIPHERALS = true; Peripherals { ADC: ADC { _marker: PhantomData, }, COMP1: COMP1 { _marker: PhantomData, }, COMP2: COMP2 { _marker: PhantomData, }, RCC: RCC { _marker: PhantomData, }, PWR: PWR { _marker: PhantomData, }, GPIOA: GPIOA { _marker: PhantomData, }, GPIOB: GPIOB { _marker: PhantomData, }, GPIOF: GPIOF { _marker: PhantomData, }, EXTI: EXTI { _marker: PhantomData, }, LPTIM: LPTIM { _marker: PhantomData, }, USART1: USART1 { _marker: PhantomData, }, USART2: USART2 { _marker: PhantomData, }, RTC: RTC { _marker: PhantomData, }, IWDG: IWDG { _marker: PhantomData, }, WWDG: WWDG { _marker: PhantomData, }, TIM1: TIM1 { _marker: PhantomData, }, TIM3: TIM3 { _marker: PhantomData, }, TIM14: TIM14 { _marker: PhantomData, }, TIM16: TIM16 { _marker: PhantomData, }, TIM17: TIM17 { _marker: PhantomData, }, SYSCFG: SYSCFG { _marker: PhantomData, }, DMA: DMA { _marker: PhantomData, }, FLASH: FLASH { _marker: PhantomData, }, CRC: CRC { _marker: PhantomData, }, SPI1: SPI1 { _marker: PhantomData, }, SPI2: SPI2 { _marker: PhantomData, }, I2C: I2C { _marker: PhantomData, }, LED: LED { _marker: PhantomData, }, DBGMCU: DBGMCU { _marker: PhantomData, }, } } }