ADD (immediate) Add immediate (unpredicated) Add an unsigned immediate to each element of the source vector, and destructively place the results in the corresponding elements of the source vector. This instruction is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8". Green False True True 0 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size:sh == '001' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer dn = UInt(Zdn); integer imm = UInt(imm8); if sh == '1' then imm = imm << 8; <Zdn> Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <imm> Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field. <shift> Is the optional left shift to apply to the immediate, defaulting to LSL #0 and sh <shift> 0 LSL #0 1 LSL #8 CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[dn, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize) element1 = Elem[operand1, e, esize]; Elem[result, e, esize] = element1 + imm; Z[dn, VL] = result;