ADDV Add across vector This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 0 0 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 0 ADDV <V><d>, <Vn>.<T> if size:Q == '100' then UNDEFINED; if size == '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); <V> Is the destination width specifier, size <V> 00 B 01 H 10 S 11 RESERVED <d> Is the number of the SIMD&FP destination register, encoded in the "Rd" field. <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 RESERVED 10 1 4S 11 x RESERVED CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; V[d, esize] = IntReduce(ReduceOp_ADD, operand, esize);