ADR
Compute vector address
Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
Green
False
True
SM_0_only
It has encodings from 3 classes:
Packed offsets
,
Unpacked 32-bit signed offsets
and
Unpacked 32-bit unsigned offsets
0
0
0
0
0
1
0
0
1
1
1
0
1
0
ADR <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant integer osize = esize;
constant boolean unsigned = TRUE;
constant integer mbytes = 1 << UInt(msz);
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
ADR <Zd>.D, [<Zn>.D, <Zm>.D, SXTW{ <amount>}]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer esize = 64;
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant integer osize = 32;
constant boolean unsigned = FALSE;
constant integer mbytes = 1 << UInt(msz);
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
ADR <Zd>.D, [<Zn>.D, <Zm>.D, UXTW{ <amount>}]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer esize = 64;
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant integer osize = 32;
constant boolean unsigned = TRUE;
constant integer mbytes = 1 << UInt(msz);
<Zd>
Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>
Is the size specifier,
<Zn>
Is the name of the base scalable vector register, encoded in the "Zn" field.
<Zm>
Is the name of the offset scalable vector register, encoded in the "Zm" field.
<mod>
Is the index extend and shift specifier,
msz
<mod>
00
[absent]
x1
LSL
10
LSL
<amount>
Is the index shift amount,
msz
<amount>
00
[absent]
01
#1
10
#2
11
#3
CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant bits(VL) base = Z[n, VL];
constant bits(VL) offs = Z[m, VL];
bits(VL) result;
for e = 0 to elements-1
constant bits(esize) addr = Elem[base, e, esize];
constant integer offset = Int(Elem[offs, e, esize]<osize-1:0>, unsigned);
Elem[result, e, esize] = addr + (offset * mbytes);
Z[d, VL] = result;