ANDS Bitwise AND predicates, setting the condition flags Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero. Green True True This instruction is used by the alias MOVS (predicated) S == '1' && Pn == Pm See below for details of when the alias is preferred. 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8; constant integer g = UInt(Pg); constant integer n = UInt(Pn); constant integer m = UInt(Pm); constant integer d = UInt(Pd); constant boolean setflags = TRUE; <Pd> Is the name of the destination scalable predicate register, encoded in the "Pd" field. <Pg> Is the name of the governing scalable predicate register, encoded in the "Pg" field. <Pn> Is the name of the first source scalable predicate register, encoded in the "Pn" field. <Pm> Is the name of the second source scalable predicate register, encoded in the "Pm" field. Alias Conditions CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(PL) operand1 = P[n, PL]; constant bits(PL) operand2 = P[m, PL]; bits(PL) result; constant integer psize = esize DIV 8; for e = 0 to elements-1 constant bit element1 = PredicateElement(operand1, e, esize); constant bit element2 = PredicateElement(operand2, e, esize); if ActivePredicateElement(mask, e, esize) then Elem[result, e, psize] = ZeroExtend(element1 AND element2, psize); else Elem[result, e, psize] = ZeroExtend('0', psize); if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d, PL] = result;