BEXT Gather lower bits from positions selected by bitmask This instruction gathers bits in each element of the first source vector from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, preserving their order, and sets the remaining higher-numbered bits to zero. This instruction is unpredicated. ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled. Green False True SM_0_only 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 BEXT <Zd>.<T>, <Zn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_SVE_BitPerm) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) data = Z[n, VL]; constant bits(VL) mask = Z[m, VL]; bits(VL) result; for e = 0 to elements - 1 Elem[result, e, esize] = BitExtract(Elem[data, e, esize], Elem[mask, e, esize]); Z[d, VL] = result;