BFADD (predicated) BFloat16 floating-point add vectors (predicated) Add active BFloat16 elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. This instruction follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented. Green True True True 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 BFADD <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H if !IsFeatureImplemented(FEAT_SVE_B16B16) then UNDEFINED; constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant integer m = UInt(Zm); <Zdn> Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 16; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = if AnyActiveElement(mask, 16) then Z[m, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 constant bits(16) element1 = Elem[operand1, e, 16]; if ActivePredicateElement(mask, e, 16) then constant bits(16) element2 = Elem[operand2, e, 16]; Elem[result, e, 16] = BFAdd(element1, element2, FPCR); else Elem[result, e, 16] = element1; Z[dn, VL] = result;