BFCVT Floating-point down convert to BFloat16 format (predicated) Convert to BFloat16 from single-precision in each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. Since the result type is smaller than the input type, the results are zero-extended to fill each destination element. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented. Green True True True 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 BFCVT <Zd>.H, <Pg>/M, <Zn>.S if ((!IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)) || !IsFeatureImplemented(FEAT_BF16)) then UNDEFINED; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 32; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, 32) then Z[n, VL] else Zeros(VL); bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, 32) then constant bits(32) element = Elem[operand, e, 32]; Elem[result, 2*e, 16] = FPConvertBF(element, FPCR); Elem[result, 2*e+1, 16] = Zeros(16); Z[d, VL] = result;