BFMLALT (vectors) BFloat16 floating-point multiply-add long to single-precision (top) This BFloat16 floating-point multiply-add long instruction widens the odd-numbered BFloat16 elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. This instruction is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented. Green False True 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1 BFMLALT <Zda>.S, <Zn>.H, <Zm>.H if ((!IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)) || !IsFeatureImplemented(FEAT_BF16)) then UNDEFINED; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); constant boolean op1_neg = FALSE; <Zda> Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 32; constant bits(VL) op1 = Z[n, VL]; constant bits(VL) op2 = Z[m, VL]; constant bits(VL) op3 = Z[da, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(16) elem1 = (if op1_neg then BFNeg(Elem[op1, 2*e + 1, 16]) else Elem[op1, 2*e + 1, 16]); constant bits(16) elem2 = Elem[op2, 2*e + 1, 16]; constant bits(32) elem3 = Elem[op3, e, 32]; Elem[result, e, 32] = BFMulAddH(elem3, elem1, elem2, FPCR); Z[da, VL] = result;