BFMLS (multiple and indexed vector) Multi-vector BFloat16 floating-point fused multiply-subtract by indexed element Multiply the indexed element of the second source vector by the corresponding BFloat16 floating-point elements of the two or four first source vectors and destructively subtract without intermediate rounding from the corresponding elements of the ZA single-vector groups. The elements within the second source vector are specified using an immediate element index which selects the same element position within each 128-bit vector segment. The index range is from 0 to 7, encoded in 3 bits. The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors. The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code. This instruction follows SME2 ZA-targeting non-widening BFloat16 numerical behaviors. This instruction is unpredicated. ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented. Green False SM_1_only It has encodings from 2 classes: Two ZA single-vectors and Four ZA single-vectors 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 BFMLS ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] if !IsFeatureImplemented(FEAT_SME_B16B16) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 16; constant integer n = UInt(Zn:'0'); constant integer m = UInt('0':Zm); constant integer offset = UInt(off3); constant integer index = UInt(i3h:i3l); constant integer nreg = 2; 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 BFMLS ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] if !IsFeatureImplemented(FEAT_SME_B16B16) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 16; constant integer n = UInt(Zn:'00'); constant integer m = UInt('0':Zm); constant integer offset = UInt(off3); constant integer index = UInt(i3h:i3l); constant integer nreg = 4; <Wv> Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. <offs> Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. <Zn1> For the two ZA single-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2. <Zn1> For the four ZA single-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4. <Zn4> Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3. <Zn2> Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1. <Zm> Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. <index> Is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 16; constant integer vectors = VL DIV 8; constant integer vstride = vectors DIV nreg; constant integer eltspersegment = 128 DIV 16; constant bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; for r = 0 to nreg-1 constant bits(VL) op1 = Z[n+r, VL]; constant bits(VL) op2 = Z[m, VL]; constant bits(VL) op3 = ZAvector[vec, VL]; for e = 0 to elements-1 constant bits(16) elem1 = BFNeg(Elem[op1, e, 16]); constant integer segmentbase = e - (e MOD eltspersegment); constant integer s = segmentbase + index; constant bits(16) elem2 = Elem[op2, s, 16]; constant bits(16) elem3 = Elem[op3, e, 16]; Elem[result, e, 16] = BFMulAdd_ZA(elem3, elem1, elem2, FPCR); ZAvector[vec, VL] = result; vec = vec + vstride;