BIC (vectors, unpredicated) Bitwise clear vectors (unpredicated) Bitwise AND inverted all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated. Green False True 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 0 0 BIC <Zd>.D, <Zn>.D, <Zm>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; Z[d, VL] = operand1 AND (NOT operand2);