BICS (shifted register)
Bitwise bit clear (shifted register), setting flags
This instruction performs a bitwise AND of a register
value and the complement of an optionally-shifted register value, and writes the result
to the destination register. It updates the condition flags based on the result.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
1
1
0
1
0
1
0
1
0
BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
1
BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
if sf == '0' && imm6<5> == '1' then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = 32 << UInt(sf);
constant ShiftType shift_type = DecodeShift(shift);
constant integer shift_amount = UInt(imm6);
<Wd>
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Wn>
Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.
<Wm>
Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.
<shift>
Is the optional shift to be applied to the final source, defaulting to LSL and
shift
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
<amount>
For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,
<Xd>
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Xn>
Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.
<Xm>
Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.
constant bits(datasize) operand1 = X[n, datasize];
constant bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
constant bits(datasize) result = operand1 AND NOT(operand2);
X[d, datasize] = result;
PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00';