CMP<cc> (immediate) Compare vector to immediate Compare active integer elements in the source vector with an immediate, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero. <cc> Comparison EQ equal GE signed greater than or equal GT signed greater than HI unsigned higher than HS unsigned higher than or same LE signed less than or equal LO unsigned lower than LS unsigned lower than or same LT signed less than NE not equal Green True True It has encodings from 10 classes: Equal , Greater than , Greater than or equal , Higher , Higher or same , Less than , Less than or equal , Lower , Lower or same and Not equal 0 0 1 0 0 1 0 1 0 1 0 0 0 CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_EQ; constant integer imm = SInt(imm5); constant boolean unsigned = FALSE; 0 0 1 0 0 1 0 1 0 0 0 0 1 CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_GT; constant integer imm = SInt(imm5); constant boolean unsigned = FALSE; 0 0 1 0 0 1 0 1 0 0 0 0 0 CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_GE; constant integer imm = SInt(imm5); constant boolean unsigned = FALSE; 0 0 1 0 0 1 0 0 1 0 1 CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_GT; constant integer imm = UInt(imm7); constant boolean unsigned = TRUE; 0 0 1 0 0 1 0 0 1 0 0 CMPHS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_GE; constant integer imm = UInt(imm7); constant boolean unsigned = TRUE; 0 0 1 0 0 1 0 1 0 0 0 1 0 CMPLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_LT; constant integer imm = SInt(imm5); constant boolean unsigned = FALSE; 0 0 1 0 0 1 0 1 0 0 0 1 1 CMPLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_LE; constant integer imm = SInt(imm5); constant boolean unsigned = FALSE; 0 0 1 0 0 1 0 0 1 1 0 CMPLO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_LT; constant integer imm = UInt(imm7); constant boolean unsigned = TRUE; 0 0 1 0 0 1 0 0 1 1 1 CMPLS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_LE; constant integer imm = UInt(imm7); constant boolean unsigned = TRUE; 0 0 1 0 0 1 0 1 0 1 0 0 1 CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant SVECmp cmp_op = Cmp_NE; constant integer imm = SInt(imm5); constant boolean unsigned = FALSE; <Pd> Is the name of the destination scalable predicate register, encoded in the "Pd" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. <imm> For the equal, greater than, greater than or equal, less than, less than or equal and not equal variant: is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. <imm> For the higher, higher or same, lower and lower or same variant: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(PL) result; constant integer psize = esize DIV 8; for e = 0 to elements-1 constant integer element1 = Int(Elem[operand1, e, esize], unsigned); if ActivePredicateElement(mask, e, esize) then boolean cond; case cmp_op of when Cmp_EQ cond = element1 == imm; when Cmp_NE cond = element1 != imm; when Cmp_GE cond = element1 >= imm; when Cmp_LT cond = element1 < imm; when Cmp_GT cond = element1 > imm; when Cmp_LE cond = element1 <= imm; constant bit pbit = if cond then '1' else '0'; Elem[result, e, psize] = ZeroExtend(pbit, psize); else Elem[result, e, psize] = ZeroExtend('0', psize); PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d, PL] = result;