DUP (element) Duplicate vector element to vector or scalar This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. This instruction is used by the alias MOV (scalar) Unconditionally The alias is always the preferred disassembly. It has encodings from 2 classes: Scalar and Vector 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 DUP <V><d>, <Vn>.<T>[<index>] if imm5 IN 'x0000' then UNDEFINED; constant integer size = LowestSetBitNZ(imm5<3:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>); constant integer esize = 8 << size; constant integer datasize = esize; constant integer elements = 1; 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 DUP <Vd>.<T>, <Vn>.<Ts>[<index>] if imm5 IN 'x0000' then UNDEFINED; if imm5 IN 'x1000' && Q == '0' then UNDEFINED; constant integer size = LowestSetBitNZ(imm5<3:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>); constant integer esize = 8 << size; constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; <V> Is the destination width specifier, imm5 <V> x0000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D <d> Is the number of the SIMD&FP destination register, encoded in the "Rd" field. <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <T> For the scalar variant: is the element width specifier, imm5 <T> x0000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D <T> For the vector variant: is an arrangement specifier, imm5 Q <T> x0000 x RESERVED xxxx1 0 8B xxxx1 1 16B xxx10 0 4H xxx10 1 8H xx100 0 2S xx100 1 4S x1000 0 RESERVED x1000 1 2D <index> Is the element index imm5 <index> x0000 RESERVED xxxx1 UInt(imm5<4:1>) xxx10 UInt(imm5<4:2>) xx100 UInt(imm5<4:3>) x1000 UInt(imm5<4>) <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Ts> Is an element size specifier, imm5 <Ts> x0000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D Alias Conditions CheckFPAdvSIMDEnabled64(); constant bits(idxdsize) operand = V[n, idxdsize]; bits(datasize) result; bits(esize) element; element = Elem[operand, index, esize]; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d, datasize] = result;