DUP (general) Duplicate general-purpose register to vector This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 DUP <Vd>.<T>, <R><n> if imm5 IN 'x0000' then UNDEFINED; if imm5 IN 'x1000' && Q == '0' then UNDEFINED; constant integer size = LowestSetBitNZ(imm5<3:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); // imm5<4:size+1> is IGNORED constant integer esize = 8 << size; constant integer datasize = 64 << UInt(Q); <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, imm5 Q <T> x0000 x RESERVED xxxx1 0 8B xxxx1 1 16B xxx10 0 4H xxx10 1 8H xx100 0 2S xx100 1 4S x1000 0 RESERVED x1000 1 2D <R> Is the width specifier for the general-purpose source register, imm5 <R> x0000 RESERVED xxxx1 W xxx10 W xx100 W x1000 X Unspecified bits in "imm5" are ignored but should be set to zero by an assembler. <n> Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(esize) element = X[n, esize]; constant integer elements = datasize DIV esize; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d, datasize] = result;