F1CVT, F2CVT Multi-vector floating-point convert from 8-bit floating-point to half-precision (in-order) Convert each 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the results in the corresponding 16-bit elements of the destination vectors. F1CVT scales the values by 2^{-UInt(FPMR.LSCALE[3:0])}. F2CVT scales the values by 2^{-UInt(FPMR.LSCALE2[3:0])}. The 8-bit floating-point encoding format for F1CVT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVT is selected by FPMR.F8S2. This instruction is unpredicated. Green False SM_1_only It has encodings from 2 classes: F1CVT and F2CVT 1 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 0 F1CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd: '0'); constant boolean issrc2 = FALSE; 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 F2CVT { <Zd1>.H-<Zd2>.H }, <Zn>.B if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd: '0'); constant boolean issrc2 = TRUE; <Zd1> Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. <Zd2> Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. CheckFPMREnabled(); CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 8; constant bits(VL) operand = Z[n, VL]; bits(2*VL) result; for e = 0 to elements-1 constant bits(8) element = Elem[operand, e, 8]; Elem[result, e, 16] = FP8ConvertFP(element, issrc2, FPCR, FPMR); Z[d+0, VL] = result<VL-1:0>; Z[d+1, VL] = result<2*VL-1:VL>;