FADDP (scalar)
Floating-point add pair of elements (scalar)
This instruction adds two floating-point vector elements in the source SIMD&FP register
and writes the scalar result into the destination SIMD&FP register.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
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FADDP H<d>, <Vn>.2H
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED;
if sz == '1' then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 16;
constant integer datasize = 32;
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FADDP <V><d>, <Vn>.<T>
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 32 << UInt(sz);
constant integer datasize = esize * 2;
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<V>
Is the destination width specifier,
<T>
Is the source arrangement specifier,
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = V[n, datasize];
V[d, esize] = FPReduce(ReduceOp_FADD, operand, esize, FPCR);