FADDP Floating-point add pairwise Add pairs of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. Green True True 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 FADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer m = UInt(Zm); constant integer dn = UInt(Zdn); <Zdn> Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, size <T> 00 RESERVED 01 H 10 S 11 D <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(VL) result = Z[dn, VL]; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then if IsEven(e) then element1 = Elem[operand1, e + 0, esize]; element2 = Elem[operand1, e + 1, esize]; else element1 = Elem[operand2, e - 1, esize]; element2 = Elem[operand2, e + 0, esize]; Elem[result, e, esize] = FPAdd(element1, element2, FPCR); Z[dn, VL] = result;