FAMAX
Multi-vector floating-point absolute maximum
Determine the maximum absolute value from floating-point elements of the two or four second source vectors and the corresponding floating-point elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors.
The behavior is as follows:
When FPCR.DN is 0, if either element is a NaN, the result is a quiet NaN.
When FPCR.DN is 1, if either element is a NaN, the result is the Default NaN.
Denormalized inputs and results are never flushed to zero, as if FPCR.{FZ16, FZ, FIZ} are all 0.
Denormalized inputs never generate an Input Denormal floating-point exception.
This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.
This instruction is unpredicated.
Green
False
SM_1_only
It has encodings from 2 classes:
Two registers
and
Four registers
1
1
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
0
0
FAMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FAMINMAX) then UNDEFINED;
if size == '00' then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer dn = UInt(Zdn:'0');
constant integer m = UInt(Zm:'0');
constant integer nreg = 2;
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
0
1
0
1
0
0
0
FAMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FAMINMAX) then UNDEFINED;
if size == '00' then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer dn = UInt(Zdn:'00');
constant integer m = UInt(Zm:'00');
constant integer nreg = 4;
<Zdn1>
For the two registers variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
<Zdn1>
For the four registers variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.
<T>
Is the size specifier,
size
<T>
00
RESERVED
01
H
10
S
11
D
<Zdn4>
Is the name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.
<Zdn2>
Is the name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.
<Zm1>
For the two registers variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.
<Zm1>
For the four registers variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.
<Zm4>
Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.
<Zm2>
Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.
CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;
for r = 0 to nreg-1
constant bits(VL) operand1 = Z[dn+r, VL];
constant bits(VL) operand2 = Z[m+r, VL];
for e = 0 to elements-1
constant bits(esize) element1 = Elem[operand1, e, esize];
constant bits(esize) element2 = Elem[operand2, e, esize];
Elem[results[r], e, esize] = FPAbsMax(element1, element2, FPCR);
for r = 0 to nreg-1
Z[dn+r, VL] = results[r];