FCADD
Floating-point complex add
This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of
elements, with the more significant element holding the imaginary part of the number and the less
significant element holding the real part of the number. Each element holds a floating-point
value. It performs the following computation on the corresponding complex number element pairs
from the two source registers:
Considering the complex number from the second source register on an Argand diagram, the number
is rotated counterclockwise by 90 or 270 degrees.
The rotated complex number is added to the complex number from the first source register.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
0
1
0
1
1
1
0
0
1
1
1
0
1
FCADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>
if !IsFeatureImplemented(FEAT_FCMA) then UNDEFINED;
if size == '00' then UNDEFINED;
if size == '01' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED;
if Q == '0' && size == '11' then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 8 << UInt(size);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
size
Q
<T>
00
x
RESERVED
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
0
RESERVED
11
1
2D
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
<rotate>
Is the rotation,
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element3;
for e = 0 to (elements DIV 2)-1
case rot of
when '0'
element1 = FPNeg(Elem[operand2, e*2+1, esize], FPCR);
element3 = Elem[operand2, e*2, esize];
when '1'
element1 = Elem[operand2, e*2+1, esize];
element3 = FPNeg(Elem[operand2, e*2, esize], FPCR);
Elem[result, e*2, esize] = FPAdd(Elem[operand1, e*2, esize], element1, FPCR);
Elem[result, e*2+1, esize] = FPAdd(Elem[operand1, e*2+1, esize], element3, FPCR);
V[d, datasize] = result;