FCMPE Floating-point signaling compare (scalar) This instruction compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is any type of NaN. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. An unordered comparison sets the PSTATE condition flags to N=0, Z=0, C=1, and V=1. 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 1 x 0 0 0 1 1 0 FCMPE <Hn>, <Hm> 1 1 (0) (0) (0) (0) (0) 1 FCMPE <Hn>, #0.0 0 0 0 FCMPE <Sn>, <Sm> 0 0 (0) (0) (0) (0) (0) 1 FCMPE <Sn>, #0.0 0 1 0 FCMPE <Dn>, <Dm> 0 1 (0) (0) (0) (0) (0) 1 FCMPE <Dn>, #0.0 if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant integer n = UInt(Rn); constant integer m = UInt(Rm); // ignored when opc<0> == '1' constant integer datasize = 8 << UInt(ftype EOR '10'); constant boolean signal_all_nans = TRUE; constant boolean cmp_with_zero = (opc<0> == '1'); <Hn> For the half-precision variant: is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Hn> For the half-precision, zero variant: is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Hm> Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Sn> For the single-precision variant: is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Sn> For the single-precision, zero variant: is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Dn> For the double-precision variant: is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Dn> For the double-precision, zero variant: is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPEnabled64(); constant bits(datasize) operand1 = V[n, datasize]; constant bits(datasize) operand2 = if cmp_with_zero then FPZero('0', datasize) else V[m, datasize]; PSTATE.<N,Z,C,V> = FPCompare(operand1, operand2, signal_all_nans, FPCR);