FCSEL Floating-point conditional select (scalar) This instruction allows the SIMD&FP destination register to take the value from either one or the other of two SIMD&FP source registers. If the condition passes, the first SIMD&FP source register value is taken, otherwise the second SIMD&FP source register value is taken. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 0 0 1 1 1 1 0 1 1 1 1 1 FCSEL <Hd>, <Hn>, <Hm>, <cond> 0 0 FCSEL <Sd>, <Sn>, <Sm>, <cond> 0 1 FCSEL <Dd>, <Dn>, <Dm>, <cond> if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer datasize = 8 << UInt(ftype EOR '10'); constant bits(4) condition = cond; <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Hm> Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <cond> Is one of the standard conditions, encoded in the standard way, and cond <cond> 0000 EQ 0001 NE 0010 CS 0011 CC 0100 MI 0101 PL 0110 VS 0111 VC 1000 HI 1001 LS 1010 GE 1011 LT 1100 GT 1101 LE 1110 AL 1111 NV <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Dn> Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPEnabled64(); bits(datasize) result; constant boolean condition_holds = ConditionHolds(condition); result = if condition_holds then V[n, datasize] else V[m, datasize]; V[d, datasize] = result;