FCVT Floating-point convert precision (scalar) This instruction converts the floating-point value in the SIMD&FP source register to the precision for the destination register data type using the rounding mode that is determined by the FPCR and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 0 1 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 FCVT <Sd>, <Hn> 1 1 0 1 FCVT <Dd>, <Hn> 0 0 1 1 FCVT <Hd>, <Sn> 0 0 0 1 FCVT <Dd>, <Sn> 0 1 1 1 FCVT <Hd>, <Dn> 0 1 0 0 FCVT <Sd>, <Dn> if ftype == opc || ftype == '10' || opc == '10' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer srcsize = 8 << UInt(ftype EOR '10'); constant integer dstsize = 8 << UInt(opc EOR '10'); <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPEnabled64(); constant bits(srcsize) operand = V[n, srcsize]; bits(128) result = if IsMerging(FPCR) then V[d, 128] else Zeros(128); Elem[result, 0, dstsize] = FPConvert(operand, FPCR, dstsize); V[d, 128] = result;