FCVT Floating-point convert precision (predicated) Convert the size and precision of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. Since the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element. Green True True True It has encodings from 6 classes: Half-precision to single-precision , Half-precision to double-precision , Single-precision to half-precision , Single-precision to double-precision , Double-precision to half-precision and Double-precision to single-precision 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 FCVT <Zd>.S, <Pg>/M, <Zn>.H if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 16; constant integer d_esize = 32; 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 FCVT <Zd>.D, <Pg>/M, <Zn>.H if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 16; constant integer d_esize = 64; 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 FCVT <Zd>.H, <Pg>/M, <Zn>.S if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 16; 0 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 FCVT <Zd>.D, <Pg>/M, <Zn>.S if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 64; 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 0 1 0 1 FCVT <Zd>.H, <Pg>/M, <Zn>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 16; 0 1 1 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 1 FCVT <Zd>.S, <Pg>/M, <Zn>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 32; <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(esize) element = Elem[operand, e, esize]; constant bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR, d_esize); Elem[result, e, esize] = ZeroExtend(res, esize); Z[d, VL] = result;