FCVTAU (scalar) Floating-point convert to unsigned integer, rounding to nearest with ties to away (scalar) This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 FCVTAU <Wd>, <Hn> 1 1 1 FCVTAU <Xd>, <Hn> 0 0 0 FCVTAU <Wd>, <Sn> 1 0 0 FCVTAU <Xd>, <Sn> 0 0 1 FCVTAU <Wd>, <Dn> 1 0 1 FCVTAU <Xd>, <Dn> if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer intsize = 32 << UInt(sf); constant integer fltsize = 8 << UInt(ftype EOR '10'); constant FPRounding rounding = FPRounding_TIEAWAY; constant boolean unsigned = TRUE; <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPEnabled64(); constant bits(fltsize) fltval = V[n, fltsize]; constant integer fracbits = 0; X[d, intsize] = FPToFixed(fltval, fracbits, unsigned, FPCR, rounding, intsize);