FCVTL, FCVTL2
Floating-point convert to higher precision long (vector)
This instruction
reads each element in a vector
in the SIMD&FP source register, converts each value to double
the precision of the source element using the
rounding mode that is determined by the FPCR,
and writes each result to the equivalent element of the vector in the SIMD&FP
destination register.
Where the operation lengthens a 64-bit vector to a 128-bit vector,
the FCVTL2 variant operates on the elements in the top 64 bits of
the source register.
A floating-point exception can be generated by this instruction.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR,
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
1
1
1
1
0
FCVTL{2} <Vd>.<Ta>, <Vn>.<Tb>
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 16 << UInt(sz);
constant integer datasize = 64;
constant integer part = UInt(Q);
constant integer elements = datasize DIV esize;
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Ta>
Is an arrangement specifier,
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Tb>
Is an arrangement specifier,
sz
Q
<Tb>
0
0
4H
0
1
8H
1
0
2S
1
1
4S
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = Vpart[n, part, datasize];
bits(2*datasize) result;
for e = 0 to elements-1
Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR, 2 * esize);
V[d, 2*datasize] = result;