FCVTLT Floating-point up convert long (top, predicated) Convert odd-numbered floating-point elements from the source vector to the next higher precision, and place the results in the active overlapping double-width elements of the destination vector. Inactive elements in the destination vector register remain unmodified. Green True It has encodings from 2 classes: Half-precision to single-precision and Single-precision to double-precision 0 1 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 1 FCVTLT <Zd>.S, <Pg>/M, <Zn>.H if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); 0 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 FCVTLT <Zd>.D, <Pg>/M, <Zn>.S if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant integer halfesize = esize DIV 2; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(halfesize) element = Elem[operand, 2*e + 1, halfesize]; Elem[result, e, esize] = FPConvertSVE(element, FPCR, esize); Z[d, VL] = result;