FCVTXN, FCVTXN2
Floating-point convert to lower precision narrow, rounding to odd (vector)
This instruction reads each vector element
in the source SIMD&FP register, narrows each value to half
the precision of the source element using the Round to Odd rounding mode, writes
the result to a vector, and writes the vector to the destination SIMD&FP
register.
This instruction uses the Round to Odd rounding mode which
is not defined by the IEEE 754-2008 standard.
This rounding mode ensures that if the result of the conversion is inexact the
least significant bit of the mantissa is forced to 1. This rounding mode enables
a floating-point value to be converted to a lower precision format via an
intermediate precision format while avoiding double rounding errors.
For example, a 64-bit floating-point value can be converted to a correctly rounded
16-bit floating-point value by first using this instruction to produce a 32-bit value
and then using another instruction with the wanted rounding mode to convert
the 32-bit value to the final 16-bit floating-point value.
The FCVTXN instruction writes the vector
to the lower half of the
destination register and clears the upper half.
The FCVTXN2 instruction writes the vector
to the upper half of the
destination register without affecting the other bits of the register.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
0
1
1
0
1
0
FCVTXN S<d>, D<n>
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 32;
constant integer datasize = esize;
constant integer elements = 1;
constant integer part = 0;
0
1
0
1
1
1
0
0
1
1
0
0
0
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FCVTXN{2} <Vd>.<Tb>, <Vn>.2D
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 32;
constant integer datasize = 64;
constant integer elements = 2;
constant integer part = UInt(Q);
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Tb>
Is an arrangement specifier,
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
CheckFPAdvSIMDEnabled64();
constant bits(2*datasize) operand = V[n, 2*datasize];
constant boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
for e = 0 to elements-1
Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD, esize);
if merge then
V[d, 128] = result;
else
Vpart[d, part, datasize] = Elem[result, 0, datasize];