FCVTZS (scalar, fixed-point) Floating-point convert to signed fixed-point, rounding toward zero (scalar) This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped. 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 FCVTZS <Wd>, <Hn>, #<fbits> 1 1 1 FCVTZS <Xd>, <Hn>, #<fbits> 0 0 0 FCVTZS <Wd>, <Sn>, #<fbits> 1 0 0 FCVTZS <Xd>, <Sn>, #<fbits> 0 0 1 FCVTZS <Wd>, <Dn>, #<fbits> 1 0 1 FCVTZS <Xd>, <Dn>, #<fbits> if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if sf == '0' && scale<5> == '0' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer intsize = 32 << UInt(sf); constant integer decode_fltsize = 8 << UInt(ftype EOR '10'); constant integer fracbits = 64 - UInt(scale); constant FPRounding rounding = FPRounding_ZERO; constant boolean unsigned = FALSE; <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <fbits> For the double-precision to 32-bit, half-precision to 32-bit and single-precision to 32-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32, encoded as 64 minus "scale". <fbits> For the double-precision to 64-bit, half-precision to 64-bit and single-precision to 64-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64, encoded as 64 minus "scale". <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPEnabled64(); constant bits(decode_fltsize) fltval = V[n, decode_fltsize]; X[d, intsize] = FPToFixed(fltval, fracbits, unsigned, FPCR, rounding, intsize);