FCVTZU (vector, fixed-point) Floating-point convert to unsigned fixed-point, rounding toward zero (vector) This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped. It has encodings from 2 classes: Scalar and Vector 0 1 1 1 1 1 1 1 0 != 0000 1 1 1 1 1 1 FCVTZU <V><d>, <V><n>, #<fbits> if immh IN {'000x'} || (immh IN {'001x'} && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16; constant integer datasize = esize; constant integer elements = 1; constant integer fracbits = (esize * 2) - UInt(immh:immb); constant boolean unsigned = TRUE; constant FPRounding rounding = FPRounding_ZERO; 0 1 0 1 1 1 1 0 != 0000 1 1 1 1 1 1 FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits> if immh == '0000' then SEE(asimdimm); if immh IN {'000x'} || (immh IN {'001x'} && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if immh<3>:Q == '10' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16; constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; constant integer fracbits = (esize * 2) - UInt(immh:immb); constant boolean unsigned = TRUE; constant FPRounding rounding = FPRounding_ZERO; <V> Is a width specifier, immh <V> 0001 RESERVED 001x H 01xx S 1xxx D <d> Is the number of the SIMD&FP destination register, in the "Rd" field. <n> Is the number of the first SIMD&FP source register, encoded in the "Rn" field. <fbits> For the scalar variant: is the number of fractional bits, in the range 1 to the operand width, immh <fbits> 0001 RESERVED 001x 32 - UInt(immh:immb) 01xx 64 - UInt(immh:immb) 1xxx 128 - UInt(immh:immb) <fbits> For the vector variant: is the number of fractional bits, in the range 1 to the element width, immh <fbits> 0001 RESERVED 001x 32 - UInt(immh:immb) 01xx 64 - UInt(immh:immb) 1xxx 128 - UInt(immh:immb) <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, immh Q <T> 0001 x RESERVED 001x 0 4H 001x 1 8H 01xx 0 2S 01xx 1 4S 1xxx 0 RESERVED 1xxx 1 2D <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; constant boolean merge = elements == 1 && IsMerging(FPCR); bits(128) result = if merge then V[d, 128] else Zeros(128); bits(esize) element; for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPToFixed(element, fracbits, unsigned, FPCR, rounding, esize); V[d, 128] = result;