FJCVTZS Floating-point Javascript convert to signed fixed-point, rounding toward zero This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. If the result is too large to be represented as a signed 32-bit integer, then the result is the integer modulo 2³², as held in a 32-bit signed integer. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 FJCVTZS <Wd>, <Dn> if !IsFeatureImplemented(FEAT_JSCVT) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer intsize = 32; constant integer fltsize = 64; <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(fltsize) fltval = V[n, fltsize]; bits(intsize) intval; bit z; (intval, z) = FPToFixedJS(fltval, FPCR, intsize); X[d, intsize] = intval; PSTATE.<N,Z,C,V> = '0':z:'00';