FMINV Floating-point minimum recursive reduction to scalar Floating-point minimum horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as +Infinity. When FPCR.AH is 0, the behavior is as follows: Negative zero compares less than positive zero. When FPCR.DN is 0, if either value is a NaN, the result is a quiet NaN. When FPCR.DN is 1, if either value is a NaN, the result is Default NaN. When FPCR.AH is 1, the behavior is as follows: If both values are zeros, regardless of the sign of either zero, the result is the second value. If either value is a NaN, regardless of the value of FPCR.DN, the result is the second value. Green True 0 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 1 FMINV <V><d>, <Pg>, <Zn>.<T> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Vd); <V> Is a width specifier, size <V> 00 RESERVED 01 H 10 S 11 D <d> Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. <T> Is the size specifier, size <T> 00 RESERVED 01 H 10 S 11 D CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); constant bits(esize) identity = FPInfinity('0', esize); V[d, esize] = FPReducePredicated(ReduceOp_FMIN, operand, mask, identity, FPCR);