FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)
8-bit floating-point multiply-add long-long to single-precision (vector)
This instruction widens the first (bottom bottom), second (bottom top),
third (top bottom), or fourth (top top) 8-bit element of each 32-bit
container in the first and second source vectors to single-precision
format and multiplies the corresponding elements. The intermediate products
are scaled by 2-UInt(FPMR.LSCALE), before being destructively
added without intermediate rounding to the single-precision elements of the
destination vector that overlap with the corresponding 8-bit floating-point
elements in the source vectors.
The 8-bit floating-point encoding format for the elements of the first
source vector is selected by FPMR.F8S1.
The 8-bit floating-point encoding format for the elements of the second
source vector is selected by FPMR.F8S2.
0
0
0
1
1
1
0
0
x
0
1
1
0
0
0
1
0
0
FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B
0
1
FMLALLBT <Vd>.4S, <Vn>.16B, <Vm>.16B
1
0
FMLALLTB <Vd>.4S, <Vn>.16B, <Vm>.16B
1
1
FMLALLTT <Vd>.4S, <Vn>.16B, <Vm>.16B
if !IsFeatureImplemented(FEAT_FP8FMA) then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer elements = 128 DIV 32;
constant integer sel = UInt(Q:size<0>);
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
CheckFPMREnabled(); CheckFPAdvSIMDEnabled64();
constant bits(128) operand1 = V[n, 128];
constant bits(128) operand2 = V[m, 128];
constant bits(128) operand3 = V[d, 128];
bits(128) result;
for e = 0 to elements-1
constant bits(8) element1 = Elem[operand1, 4 * e + sel, 8];
constant bits(8) element2 = Elem[operand2, 4 * e + sel, 8];
constant bits(32) element3 = Elem[operand3, e, 32];
Elem[result, e, 32] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR);
V[d, 128] = result;