FMLALLBB (vectors) 8-bit floating-point multiply-add long long to single-precision (bottom bottom) This 8-bit floating-point multiply-add long-long instruction widens the first 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2^{-UInt(FPMR.LSCALE)} before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. This instruction is unpredicated. Green False True 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B if !HaveSVE2FP8FMA() then UNDEFINED; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); <Zda> Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. CheckFPMREnabled(); if IsFeatureImplemented(FEAT_FP8FMA) then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; constant bits(VL) operand3 = Z[da, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(8) element1 = Elem[operand1, 4 * e + 0, 8]; constant bits(8) element2 = Elem[operand2, 4 * e + 0, 8]; constant bits(32) element3 = Elem[operand3, e, 32]; Elem[result, e, 32] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR); Z[da, VL] = result;