FMOV (vector, immediate)
Floating-point move immediate (vector)
This instruction copies an immediate
floating-point constant into every element of the SIMD&FP destination register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
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FMOV <Vd>.<T>, #<imm>
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED;
constant integer rd = UInt(Rd);
constant integer datasize = 64 << UInt(Q);
constant bits(8) imm8 = a:b:c:d:e:f:g:h;
constant bits(16) imm16 = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>, 2):imm8<5:0>:Zeros(6);
constant bits(datasize) imm = Replicate(imm16, datasize DIV 16);
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FMOV <Vd>.<T>, #<imm>
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FMOV <Vd>.2D, #<imm>
if cmode:op == '11111' then
// FMOV Dn,#imm is in main FP instruction set
if Q == '0' then UNDEFINED;
constant integer rd = UInt(Rd);
constant integer datasize = 64 << UInt(Q);
constant bits(64) imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h);
constant bits(datasize) imm = Replicate(imm64, datasize DIV 64);
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the half-precision variant: is an arrangement specifier,
<T>
For the single-precision variant: is an arrangement specifier,
<imm>
Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h". For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in A64 floating-point instructions.
CheckFPAdvSIMDEnabled64();
V[rd, datasize] = imm;