FMOV (general) Floating-point move to or from general-purpose register without conversion This instruction transfers the contents of a SIMD&FP register to a general-purpose register, or the contents of a general-purpose register to a SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 1 1 1 1 0 1 0 x 1 1 x 0 0 0 0 0 0 0 1 1 0 0 FMOV <Wd>, <Hn> 1 1 1 0 0 FMOV <Xd>, <Hn> 0 1 1 0 1 FMOV <Hd>, <Wn> 0 0 0 0 1 FMOV <Sd>, <Wn> 0 0 0 0 0 FMOV <Wd>, <Sn> 1 1 1 0 1 FMOV <Hd>, <Xn> 1 0 1 0 1 FMOV <Dd>, <Xn> 1 1 0 1 1 FMOV <Vd>.D[1], <Xn> 1 0 1 0 0 FMOV <Xd>, <Dn> 1 1 0 1 0 FMOV <Xd>, <Vn>.D[1] if ftype == '10' && opcode<2:1>:rmode != '11 01' then UNDEFINED; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer intsize = 32 << UInt(sf); constant integer fltsize = if ftype == '10' then 64 else (8 << UInt(ftype EOR '10')); constant integer part = UInt(rmode<0>); FPConvOp op; case opcode<2:1>:rmode of when '11 00' // FMOV if fltsize != 16 && fltsize != intsize then UNDEFINED; op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; when '11 01' // FMOV D[1] if intsize != 64 || ftype != '10' then UNDEFINED; op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; otherwise Unreachable(); <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Wn> Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Xn> Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPEnabled64(); bits(fltsize) fltval; bits(intsize) intval; case op of when FPConvOp_MOV_FtoI fltval = Vpart[n, part, fltsize]; X[d, intsize] = ZeroExtend(fltval, intsize); when FPConvOp_MOV_ItoF intval = X[n, intsize]; Vpart[d, part, fltsize] = intval<fltsize-1:0>; otherwise Unreachable();