FMULX
Floating-point multiply extended
This instruction multiplies corresponding floating-point values in the vectors
of the two source SIMD&FP registers,
places the resulting floating-point values in a vector,
and writes the vector to the destination SIMD&FP register.
If one value is zero and the other value is infinite, the result is 2.0. In this case, the
result is negative if only one of the values is negative,
otherwise the result is positive.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR,
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 4 classes:
Scalar half precision
,
Scalar single-precision and double-precision
,
Vector half precision
and
Vector single-precision and double-precision
0
1
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
FMULX <Hd>, <Hn>, <Hm>
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 16;
constant integer datasize = esize;
constant integer elements = 1;
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1
0
1
1
1
1
0
0
1
1
1
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1
1
1
FMULX <V><d>, <V><n>, <V><m>
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 32 << UInt(sz);
constant integer datasize = esize;
constant integer elements = 1;
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 16;
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;
0
0
0
1
1
1
0
0
1
1
1
0
1
1
1
FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if sz:Q == '10' then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 32 << UInt(sz);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Hm>
Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
<V>
Is a width specifier,
<d>
Is the number of the SIMD&FP destination register, in the "Rd" field.
<n>
Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
<m>
Is the number of the second SIMD&FP source register, encoded in the "Rm" field.
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the half-precision variant: is an arrangement specifier,
<T>
For the single-precision and double-precision variant: is an arrangement specifier,
sz
Q
<T>
0
0
2S
0
1
4S
1
0
RESERVED
1
1
2D
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
if elements == 1 then
CheckFPEnabled64();
else
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(esize) element1;
bits(esize) element2;
constant boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);
for e = 0 to elements-1
element1 = Elem[operand1, e, esize];
element2 = Elem[operand2, e, esize];
Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
V[d, 128] = result;