FNEG (scalar) Floating-point negate (scalar) This instruction negates the value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 FNEG <Hd>, <Hn> 0 0 FNEG <Sd>, <Sn> 0 1 FNEG <Dd>, <Dn> if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(ftype EOR '10'); <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPEnabled64(); constant bits(esize) operand = V[n, esize]; bits(128) result = if IsMerging(FPCR) then V[d, 128] else Zeros(128); Elem[result, 0, esize] = FPNeg(operand, FPCR); V[d, 128] = result;