FNEG Floating-point negate (predicated) Negate each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. This inverts the sign bit and cannot signal a floating-point exception. Inactive elements in the destination vector register remain unmodified. Green True True True 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <T> Is the size specifier, size <T> 00 RESERVED 01 H 10 S 11 D <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(esize) element = Elem[operand, e, esize]; Elem[result, e, esize] = FPNeg(element, FPCR); Z[d, VL] = result;