FRINTN (scalar)
Floating-point round to integral, to nearest with ties to even (scalar)
This instruction rounds a floating-point value in the SIMD&FP source register
to an integral floating-point value of the same size using the
Round to Nearest rounding mode, and writes the
result to the SIMD&FP destination register.
A zero input
gives a zero result with the same sign, an infinite input gives an infinite
result with the same sign, and a NaN is
propagated as for normal arithmetic.
A floating-point exception can be generated by this instruction.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR,
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
0
0
0
1
1
1
1
0
1
0
0
1
0
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1
0
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1
FRINTN <Hd>, <Hn>
0
0
FRINTN <Sd>, <Sn>
0
1
FRINTN <Dd>, <Dn>
if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 8 << UInt(ftype EOR '10');
constant boolean exact = FALSE;
constant FPRounding rounding = FPRounding_TIEEVEN;
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dn>
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
CheckFPEnabled64();
constant bits(esize) operand = V[n, esize];
bits(128) result = if IsMerging(FPCR) then V[d, 128] else Zeros(128);
Elem[result, 0, esize] = FPRoundInt(operand, FPCR, rounding, exact);
V[d, 128] = result;