FRINTP (vector)
Floating-point round to integral, toward plus infinity (vector)
This instruction rounds a vector of floating-point values
in the SIMD&FP source register
to integral floating-point values of the same size using the
Round towards Plus Infinity rounding mode,
and writes the result to the SIMD&FP destination register.
A zero input
gives a zero result with the same sign, an infinite input gives an infinite
result with the same sign, and a NaN is
propagated as for normal arithmetic.
A floating-point exception can be generated by this instruction.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR,
or a synchronous exception being generated.
For more information, see
Floating-point exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
0
0
0
1
1
1
0
1
1
1
1
1
0
0
1
1
0
0
0
1
0
FRINTP <Vd>.<T>, <Vn>.<T>
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 16;
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;
constant boolean exact = FALSE;
constant FPRounding rounding = FPRounding_POSINF;
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
0
1
0
FRINTP <Vd>.<T>, <Vn>.<T>
if sz:Q == '10' then UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 32 << UInt(sz);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;
constant boolean exact = FALSE;
constant FPRounding rounding = FPRounding_POSINF;
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the half-precision variant: is an arrangement specifier,
<T>
For the single-precision and double-precision variant: is an arrangement specifier,
sz
Q
<T>
0
0
2S
0
1
4S
1
0
RESERVED
1
1
2D
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(esize) element;
for e = 0 to elements-1
element = Elem[operand, e, esize];
Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
V[d, datasize] = result;