FSCALE
Floating-point adjust exponent by vector
This instruction multiplies the floating-point elements of the first
source vector by 2.0 to the power of the signed integer values in the
corresponding elements of the second source vector, and places the
results in the corresponding elements of the destination vector.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
0
1
0
1
1
1
0
1
1
0
0
0
1
1
1
1
FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED;
constant integer esize = 16;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV esize;
0
1
0
1
1
1
0
1
x
1
1
1
1
1
1
1
FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED;
if Q == '0' && size == '11' then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV esize;
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the half-precision variant: is an arrangement specifier,
<T>
For the single-precision and double-precision variant: is an arrangement specifier,
size<0>
Q
<T>
0
0
2S
0
1
4S
1
0
RESERVED
1
1
2D
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
for e = 0 to elements-1
constant bits(esize) op1 = Elem[operand1, e, esize];
constant integer op2 = SInt(Elem[operand2, e, esize]);
Elem[result, e, esize] = FPScale(op1, op2, FPCR);
V[d, datasize] = result;