INS (element) Insert vector element from another vector element This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register. This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. This instruction is used by the alias MOV (element) Unconditionally The alias is always the preferred disassembly. 0 1 1 0 1 1 1 0 0 0 0 0 1 INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] if imm5 IN 'x0000' then UNDEFINED; constant integer size = LowestSetBitNZ(imm5<3:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer dst_index = UInt(imm5<4:size+1>); constant integer src_index = UInt(imm4<3:size>); constant integer idxdsize = 64 << UInt(imm4<3>); // imm4<size-1:0> is IGNORED constant integer esize = 8 << size; <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Ts> Is an element size specifier, imm5 <Ts> x0000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D <index1> Is the destination element index imm5 <index1> x0000 RESERVED xxxx1 UInt(imm5<4:1>) xxx10 UInt(imm5<4:2>) xx100 UInt(imm5<4:3>) x1000 UInt(imm5<4>) <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <index2> Is the source element index imm5 <index2> x0000 RESERVED xxxx1 UInt(imm4) xxx10 UInt(imm4<3:1>) xx100 UInt(imm4<3:2>) x1000 UInt(imm4<3>) Unspecified bits in "imm4" are ignored but should be set to zero by an assembler. Alias Conditions CheckFPAdvSIMDEnabled64(); constant bits(idxdsize) operand = V[n, idxdsize]; bits(128) result; result = V[d, 128]; Elem[result, dst_index, esize] = Elem[operand, src_index, esize]; V[d, 128] = result;