INSR (SIMD&FP scalar) Insert SIMD&FP scalar register in shifted vector Shift the destination vector left by one element, and then place a copy of the SIMD&FP scalar register in element 0 of the destination vector. This instruction is unpredicated. Green False True True 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 1 1 0 INSR <Zdn>.<T>, <V><m> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer dn = UInt(Zdn); constant integer m = UInt(Vm); <Zdn> Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, size <T> 00 B 01 H 10 S 11 D <V> Is a width specifier, size <V> 00 B 01 H 10 S 11 D <m> Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant bits(VL) dest = Z[dn, VL]; constant bits(esize) src = V[m, esize]; Z[dn, VL] = dest<(VL-esize)-1:0> : src;