LD1H (vector plus immediate) Gather load unsigned halfwords to vector (immediate index) Gather load of unsigned halfwords to active elements of a vector register from memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled. Green True True True SM_0_only It has encodings from 2 classes: 32-bit element and 64-bit element 1 0 0 0 0 1 0 0 1 0 1 1 1 0 LD1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = UInt(imm5); 1 1 0 0 0 1 0 0 1 0 1 1 1 0 LD1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = UInt(imm5); <Zt> Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the base scalable vector register, encoded in the "Zn" field. <imm> Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field. CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(VL) base; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, esize) then base = Z[n, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(64) baddr = ZeroExtend(Elem[base, e, esize], 64); constant bits(64) addr = AddressAdd(baddr, offset * mbytes, accdesc); data = Mem[addr, mbytes, accdesc]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(esize); Z[t, VL] = result;