LD1Q Gather load quadwords Gather load of quadwords to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled. Green True True True SM_0_only 1 1 0 0 0 1 0 0 0 0 0 1 0 1 LD1Q { <Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}] if !IsFeatureImplemented(FEAT_SVE2p1) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); <Zt> Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the base scalable vector register, encoded in the "Zn" field. <Xm> Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. constant integer VL = CurrentVL; constant integer PL = VL DIV 8; CheckNonStreamingSVEEnabled(); constant integer elements = VL DIV 128; constant bits(PL) mask = P[g, PL]; bits(VL) base; bits(64) offset; bits(VL) result; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, 128) then base = Z[n, VL]; offset = X[m, 64]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, 128) then constant bits(64) baddr = Elem[base, 2*e, 64]; constant bits(64) addr = AddressAdd(baddr, offset, accdesc); Elem[result, e, 128] = Mem[addr, 16, accdesc]; else Elem[result, e, 128] = Zeros(128); Z[t, VL] = result;