LD1ROB (scalar plus scalar) Contiguous load and replicate thirty-two bytes (scalar index) Load thirty-two contiguous bytes to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector. The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first thirty-two predicate elements are used and higher numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled. Green True True True SM_0_only 1 0 1 0 0 1 0 0 0 0 1 0 0 0 LD1ROB { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>] if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_F64MM) then UNDEFINED; if Rm == '11111' then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 8; <Zt> Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xm> Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; if VL < 256 then UNDEFINED; constant integer elements = 256 DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; // low bits only bits(64) offset; bits(64) addr; bits(256) result; constant integer mbytes = esize DIV 8; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = Mem[addr, mbytes, accdesc]; else Elem[result, e, esize] = Zeros(esize); addr = AddressIncrement(addr, mbytes, accdesc); Z[t, VL] = ZeroExtend(Replicate(result, VL DIV 256), VL);