LD2D (scalar plus immediate) Contiguous load two-doubleword structures to two vectors (immediate index) Contiguous load two-doubleword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which is a multiple of 2 in the range -16 to 14 that is multiplied by the vector's in-memory size, irrespective of predication, Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers. Green True True True 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 LD2D { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer offset = SInt(imm4); constant integer nreg = 2; <Zt1> Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. <Zt2> Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> Is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(64) addr; constant integer mbytes = esize DIV 8; array [0..1] of bits(VL) values; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; addr = AddressAdd(base, offset * elements * nreg * mbytes, accdesc); for e = 0 to elements-1 for r = 0 to nreg-1 if ActivePredicateElement(mask, e, esize) then Elem[values[r], e, esize] = Mem[addr, mbytes, accdesc]; else Elem[values[r], e, esize] = Zeros(esize); addr = AddressIncrement(addr, mbytes, accdesc); for r = 0 to nreg-1 Z[(t+r) MOD 32, VL] = values[r];